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JPS5614353A - Control clock switching system - Google Patents

Control clock switching system

Info

Publication number
JPS5614353A
JPS5614353A JP8856679A JP8856679A JPS5614353A JP S5614353 A JPS5614353 A JP S5614353A JP 8856679 A JP8856679 A JP 8856679A JP 8856679 A JP8856679 A JP 8856679A JP S5614353 A JPS5614353 A JP S5614353A
Authority
JP
Japan
Prior art keywords
register
clocks
instruction
held
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8856679A
Other languages
Japanese (ja)
Inventor
Takeshi Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8856679A priority Critical patent/JPS5614353A/en
Publication of JPS5614353A publication Critical patent/JPS5614353A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To detect previously degradation of functions of various logical elements of a data processing unit, by selecting plural control clocks from the generating means, which generates control clocks, by a selecting means and by controlling this selecting means by microinstructions.
CONSTITUTION: Plural kinds of control clock CL0WCLn generated by a clock generating means are transferred to clock switching circuit 6, and one of clocks CL0WCLn is selected by circuit 6 and is output according to the control signal transferred from decoder 5. Information stored at the address of memory 2 is held in data register 3 by indication of data held in address register 1, and further, information held in register 3 is held in instruction register 4, and the instruction in information of register 4 is decoded by decoder 5. In case that this instruction is the switching instruction for control clocks, the switching control signal is transferred from decoder 5 to circuit 6, and one of clocks CL0WCLn is selected and output, so that functions of various logical elements of the data proccessing unit can be checked.
COPYRIGHT: (C)1981,JPO&Japio
JP8856679A 1979-07-12 1979-07-12 Control clock switching system Pending JPS5614353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8856679A JPS5614353A (en) 1979-07-12 1979-07-12 Control clock switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8856679A JPS5614353A (en) 1979-07-12 1979-07-12 Control clock switching system

Publications (1)

Publication Number Publication Date
JPS5614353A true JPS5614353A (en) 1981-02-12

Family

ID=13946406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8856679A Pending JPS5614353A (en) 1979-07-12 1979-07-12 Control clock switching system

Country Status (1)

Country Link
JP (1) JPS5614353A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840642A (en) * 1981-09-04 1983-03-09 Anritsu Corp Emulator clock circuit
JPH0829496A (en) * 1994-07-13 1996-02-02 Nec Corp Semiconductor integrated circuit and method for testing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840642A (en) * 1981-09-04 1983-03-09 Anritsu Corp Emulator clock circuit
JPH0115096B2 (en) * 1981-09-04 1989-03-15 Anritsu Corp
JPH0829496A (en) * 1994-07-13 1996-02-02 Nec Corp Semiconductor integrated circuit and method for testing the same

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