JPS57193847A - Memory bank dividing circuit - Google Patents
Memory bank dividing circuitInfo
- Publication number
- JPS57193847A JPS57193847A JP7820981A JP7820981A JPS57193847A JP S57193847 A JPS57193847 A JP S57193847A JP 7820981 A JP7820981 A JP 7820981A JP 7820981 A JP7820981 A JP 7820981A JP S57193847 A JPS57193847 A JP S57193847A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- signal
- instruction
- bank
- bank dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To make a high-speed instruction execution possible, by providing a preset counter or shift register which performs the counting or shift operation at the timing of a memory read signal and using the output signal as a bank dividing signal.
CONSTITUTION: A preset counter or shift register is provided which performs the counting or shift operation at the timing of a memory read signal. For example, an address read out from a CPU 1 at a prescribed time is transmitted to an address bus (a) to read out an instruction word from a memory, and this instruction word is inputted to an instruction decode memory 3-4. Next, data written in the address selected by the instruction decode memory 3-4 is outputted and is inputted to an instruction counter 3-5, and the output signal is inputted to a bank dividing memory switch 3-3 through a gate 3-6. A bank signal is switched from data of a bank dividing memory 3-1 to data of a bank dividing memory 3-2 in accordance with the change of the output signal of the gate 3-6.
COPYRIGHT: (C)1982,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7820981A JPS57193847A (en) | 1981-05-22 | 1981-05-22 | Memory bank dividing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7820981A JPS57193847A (en) | 1981-05-22 | 1981-05-22 | Memory bank dividing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57193847A true JPS57193847A (en) | 1982-11-29 |
Family
ID=13655646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7820981A Pending JPS57193847A (en) | 1981-05-22 | 1981-05-22 | Memory bank dividing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57193847A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59134841U (en) * | 1983-02-25 | 1984-09-08 | ソニー株式会社 | information processing equipment |
| JPS6033644A (en) * | 1983-08-05 | 1985-02-21 | Nippon Sheet Glass Co Ltd | Memory bank switching method and its device |
-
1981
- 1981-05-22 JP JP7820981A patent/JPS57193847A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59134841U (en) * | 1983-02-25 | 1984-09-08 | ソニー株式会社 | information processing equipment |
| JPS6033644A (en) * | 1983-08-05 | 1985-02-21 | Nippon Sheet Glass Co Ltd | Memory bank switching method and its device |
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