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JPS5789173A - Data processing control system - Google Patents

Data processing control system

Info

Publication number
JPS5789173A
JPS5789173A JP55164100A JP16410080A JPS5789173A JP S5789173 A JPS5789173 A JP S5789173A JP 55164100 A JP55164100 A JP 55164100A JP 16410080 A JP16410080 A JP 16410080A JP S5789173 A JPS5789173 A JP S5789173A
Authority
JP
Japan
Prior art keywords
access
input
access start
adder
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55164100A
Other languages
Japanese (ja)
Inventor
Keiichiro Uchida
Hiroshi Tamura
Tetsuo Okamoto
Shigeaki Okuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55164100A priority Critical patent/JPS5789173A/en
Priority to KR1019810004304A priority patent/KR860001434B1/en
Priority to US06/322,717 priority patent/US4435765A/en
Priority to AU77596/81A priority patent/AU533634B2/en
Priority to DE8181305481T priority patent/DE3169741D1/en
Priority to ES507355A priority patent/ES507355A0/en
Priority to CA000390501A priority patent/CA1175576A/en
Priority to EP81305481A priority patent/EP0053457B1/en
Priority to BR8107582A priority patent/BR8107582A/en
Publication of JPS5789173A publication Critical patent/JPS5789173A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To process data, by placing consecutive elements of a vector register in sequence of corresponding banks so that each bank corresponds to an element of the same rank at every vector register, and prescribing a time limit for accessing the element. CONSTITUTION:A shift register consisting of 8 bits is used for generating the timings A-H, so that start signals of addition processing, multiplication processing, load processing and store processing are outputted from between A and B, D and E, and G, H and A, respectively. Access of one input of an adder 3 is started by the timing A, access of the other input of the adder 3 is started by the timing B in the same way, and after that, in the same way, access start of an output of the adder 3, access start of one input pf a multiplier 4, access start of the other input of 4, access start of an output of 4, operand access start of a load processing device 1, and operand access start of a store processor 2 are executed by C, D, E, F, G and H, respectively.
JP55164100A 1980-11-21 1980-11-21 Data processing control system Pending JPS5789173A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP55164100A JPS5789173A (en) 1980-11-21 1980-11-21 Data processing control system
KR1019810004304A KR860001434B1 (en) 1980-11-21 1981-11-10 Bank interleaved vector processor having a fixed relationship between start timing signals
US06/322,717 US4435765A (en) 1980-11-21 1981-11-18 Bank interleaved vector processor having a fixed relationship between start timing signals
AU77596/81A AU533634B2 (en) 1980-11-21 1981-11-18 Data processing system
DE8181305481T DE3169741D1 (en) 1980-11-21 1981-11-20 Data processing apparatus
ES507355A ES507355A0 (en) 1980-11-21 1981-11-20 DATA PROCESSING SYSTEM.
CA000390501A CA1175576A (en) 1980-11-21 1981-11-20 Data processing system for vector operations
EP81305481A EP0053457B1 (en) 1980-11-21 1981-11-20 Data processing apparatus
BR8107582A BR8107582A (en) 1980-11-21 1981-11-20 DATA PROCESSING SYSTEM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164100A JPS5789173A (en) 1980-11-21 1980-11-21 Data processing control system

Publications (1)

Publication Number Publication Date
JPS5789173A true JPS5789173A (en) 1982-06-03

Family

ID=15786757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164100A Pending JPS5789173A (en) 1980-11-21 1980-11-21 Data processing control system

Country Status (1)

Country Link
JP (1) JPS5789173A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120905A (en) * 1984-07-09 1986-01-29 Masami Fujii Overhead optical communication line

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120905A (en) * 1984-07-09 1986-01-29 Masami Fujii Overhead optical communication line

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