JPH0477945B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a vector processing device that uses bank-configured vector registers, when there is a bank that is not used by a vector instruction during execution, it is possible to make it usable by other vector instructions and execute the vector instruction. promotes multiplexing.

[Industrial application field]

The present invention relates to an execution control method for vector instructions in a vector processing device, and more particularly to an execution control method for parallel processing of vector instructions in a vector processing device that uses vector registers with an interleaved bank configuration. .

[Conventional technology]

First, an example of the basic configuration of a conventional vector processing device to which the present invention is directed will be explained with reference to FIG.

In the figure, 41 is a vector register VR;
42 is a mask register MR, 43 and 44 are A pipelines and A pipelines that perform loads/stores, 45 is an ADD pipeline for addition, 46 is a MULTI pipeline for multiplication, and 47 is a MASK pipe for mask operations. A line 48 indicates an instruction management control unit, and 49 indicates a main storage unit MSU.

Vector register VR41 holds vector data and is composed of eight banks. Each bank can be accessed in parallel by different pipelines.

Mask register MR42 holds mask data for masking vector data.

A pipeline 43 and B pipeline 44
are vector register VR41 or mask register MR42 and main memory MSU, respectively.
49, data is loaded/stored.

The ADD pipeline 45 and the MURTI pipeline 46 each have a vector register VR.
41 and mask register MR42 to perform addition or multiplication operations.

MASK pipeline 47 executes operations on mask data in mask register MR42.

The instruction management control unit 48 includes an instruction management port, a timing control mechanism, etc. for controlling each pipeline based on a given vector instruction.

By the way, since the A, B, ADD, and MULTI pipelines share the vector register VR41, a method is used to allocate access timing to each pipeline so that access conflicts do not occur in each bank. There is.

In such a system, once a vector instruction acquires a certain access timing for accessing a vector register, processing is performed using the same access timing during execution of that instruction.

Next, a conventional vector instruction execution control system will be described using a specific example.

FIG. 5 shows an instruction start control circuit provided in the instruction management control section for vector instructions.

In the figure, 50 is an instruction input terminal, 51 is a Q register that temporarily holds execution request instructions, 52 to 55 are registers that hold execution instructions represented by A, B, C, and D, respectively, and 56 is an instruction decoder. , 511 to 551 are VALID latches, 522 to 522 are VALID setting circuits, and 523 to 533 are control lines. In addition,
A, B, C, and D correspond to so-called command management ports.

It is assumed that the vector register (hereinafter abbreviated as VR) has eight banks and eight timings.

A vector instruction is input from the instruction input terminal 50 and set in the Q register 51. At this time, the VALID latch 511 is turned on at the same time. This input vector instruction is processed until it can start execution.
It is held in the Q register 51 and placed in the WAIT state.

The instructions held in the A, B, C, and D registers 52 to 55 are each held by a VALID latch 52.
Validity/invalidity is managed by 1 to 551. For example, each register is an A register 52 for a Load instruction, a B register 53 for a Store instruction,
Arithmetic instructions are sent to C register 54 and D register 55
The commands to be set are determined in advance.

Furthermore, the timing for accessing VR for each register A, B, C, and D is determined in advance.

FIG. 6 shows each vector instruction, namely A, B,
An example of a timing table defining the access timing of each register C and D is shown. Access timing is 8 timings T ₀ to
The corresponding position of T ₇ is marked with a circle.
For example, the A register is associated with _T0 .

This allows separate timing to be assigned to each instruction, allowing parallel processing.

The instruction decoder 56 includes, for example, the Q register 51
If a Load command is entered in , only the control line 523 is turned ON. At this time, the A register 52
If the VALID latch 521 is ON, the preceding instruction is currently processing using _T0 , so the Load instruction of the Q register 51 becomes WAIT.

When VALID latch 521 turns OFF,
The output of the VALID setting circuit 522 turns ON, and the Q
The A register 52 instruction is transferred from the register 51. At the same time, the VALID latch is also set to ON by the VALID setting circuit 522, and the new instruction is executed.

Similar control is performed for the other B, C, and D registers, so the circuit shown in FIG. 5 can execute four instructions in parallel.

[Problem that the invention seeks to solve]

In conventional instruction execution control methods, tables that define access timing ensure that each instruction is
The timing of access is fixed,
Therefore, the maximum number of instructions that can be processed in parallel is also limited (maximum 4 in the examples of FIGS. 5 and 6).

By the way, vector operation instructions include vector
There are instructions, such as the scalar addition instruction, that only use one general-purpose register and two VRs. but,
Since the same three timings as normal vector operation instructions are assigned to such an instruction, there is a problem in that one timing is wasted.

[Means for solving problems]

The present invention makes it possible to execute other instructions by utilizing the idle timing of the vector operation instruction being executed.

Therefore, when it is determined whether a vector operation instruction to be executed has an empty timing or not, and when a vector operation instruction with an empty timing is identified, one of the three access timings assigned to a normal vector operation instruction is used. To make it possible to further allocate one timing to other vector instructions and increase the number of instructions that can be processed in parallel.

FIG. 1 shows a schematic configuration of an instruction start control circuit illustrating the principle of the present invention.

In the figure, 10 is an instruction input terminal, 11 is a Q register that temporarily holds an execution request instruction, 12 to 16 are A to E registers that hold execution instructions, 17 is an instruction decoder, and 18 is an empty timing instruction detection circuit. represent.

A vector instruction required to be executed is input from an instruction input terminal 10 and set in a Q register 11, and an instruction decoder 17 identifies the type of instruction.

The A to E registers 12 to 16 for holding execution instructions are each associated with a specific access timing for the vector register. The input vector instruction set in the Q register 11 for holding execution request instructions is sent to the instruction decoder 17.
Accordingly, it is set in one of the A to Q registers 12 to 16 depending on its type. However, it is necessary that the register of the other party to be set is empty.

In particular, the E register 16 becomes usable when the D register 15 holds an instruction with empty timing.

That is, when an instruction with empty timing is set in the D register 15 and is being executed, the empty timing instruction detection circuit 18 detects this,
Next, when an instruction that can be executed using the vacant timing is input, it can be set in the E register 16.

As a result, A to E registers 12 to 1
Input sequential instructions can be processed in parallel until all of 6 are filled with instructions.

[Effect]

For example, vector arithmetic instructions such as a vector scalar addition instruction that adds a fixed number to vector data, or a vector expand or compress instruction that expands or compresses the vector length, respectively, use only two vector registers. Therefore, one timing becomes vacant.

Here, when a vector instruction such as a Load instruction or a Store instruction that can only use one timing is input, a register for holding an execution instruction that is fixedly specified for that instruction in advance (for example, 1
2) is not free, the free timing instruction detection circuit 18 in FIG. , a vector instruction that uses only one input timing is set in the E register 16.

A vector instruction set in the E register 16, such as a Load instruction, is assigned one free timing of a vector instruction in the D register 15, such as a vector scalar addition instruction, and is enabled to access the vector register in parallel. .

〔Example〕

FIG. 2 is a main part configuration diagram of an instruction start control circuit in one embodiment of the present invention, and FIG. 3 is an access/start control circuit diagram.
This is a timing table that defines timing.

In the figure, 20 is an instruction input terminal, 21 is a register denoted by Q that temporarily holds the input execution request instruction, and 22 to 26 are denoted by A, B, C, D, and E, which hold the instruction being executed. register,
27 is an instruction recorder, 28 is an idle timing instruction detection circuit, 211, 221, 231, 241, 2
51, 261 are VALID latches, 222,
232, 242, 252 are VALID setting circuits, and 254 is an empty timing instruction latch 22.
3,233,243,253,263,264,
265 each represents a control line.

The embodiment circuit shown in FIG. 2 is an improved version of the conventional circuit shown in FIG. 5, but since the basic operating functions are common to both circuits,
In FIG. 2, explanations of parts not particularly related to the present invention will be omitted.

FIG. 3 shows an example of access timing corresponding to instructions set in the A, B, C, D, and E registers.

In this embodiment, when the instruction set in the D register 25 does not use timing T 6 out of the three timings T ₅ , T ₆ , and T ₇ , the instruction set in the E register ₂₆ makes it usable. ing. Further, when timing T ₆ is in use by an instruction set in the E register 26, an instruction using three timings T ₅ , T ₆ , and T ₇ cannot be set in the D register 25 .

Vector instructions that are sequentially input to the instruction input terminal 20 are first set in the Q register 21, the instruction type is identified by the instruction decoder 27, and one of the corresponding instruction execution registers 22 to 26 is selected by the control line. 223, 233, 243, 253,
263 is turned on.

When the control line 253 turns ON, the VALID setting circuit 252 sets the VALID latch 2 of the D register.
The VALID latch 251 is set to ON (valid) on the condition that the VALID latch 261 of the 51 and E registers are both OFF (invalid), that is, both registers are empty.

When identifying an instruction to turn on the control line 253, the instruction decoder 27 simultaneously identifies whether or not the instruction is a vector operation instruction with one free timing _T6 , and・If it is a scalar addition instruction), control line 2
Turn on 55. Thus, when the VALID latch 251 is set ON, the idle timing command latch 254 is also set ON.

Here, this D register 25 has an empty timing.
An instruction with T ₆ is set and VALID latch 2
51 is ON, and idle timing command latch 2
54 is set to ON, and further A register 22 is set to ON.
Consider a case where a Load command is input to the Q register 21 while the VALID latch 221 is set to ON.

In this state, control lines 263, 264, 265
is ON and the VALID latch 261 of the E register 26 is OFF, the output of the idle timing instruction detection circuit 28 is ON, and the VALID latch 261 is set to ON. That is, the Load instruction of the Q register 21 is set in the E register 26 and executed.

Note that in the above-described embodiment, when an instruction with an empty timing is set in the D register, an instruction that uses the empty timing of the E register can be set, but a similar configuration can be applied to the B register as well. and can be expanded arbitrarily.

〔Effect of the invention〕

According to the present invention, the availability of vector register access timing is reduced, and the utilization efficiency of vector registers is improved. Furthermore, since the parallel processing rate of vector instructions increases, processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of an instruction start control circuit according to the present invention, and FIG.
2 is an explanatory diagram showing an example of access timing used in the embodiment of FIG. 2, FIG. 4 is a basic configuration diagram of a conventional vector processing device, and FIG. 5 is a configuration diagram of a conventional instruction start control circuit. FIG. 6 is an explanatory diagram showing an example of access timing used in the conventional circuit shown in FIG. In FIG. 1, 10: command input terminal, 11:
Q register, 12, which holds the instruction requested for execution;
~16: A to E registers holding execution instructions, 1
7: Instruction decoder, 18: Idle timing instruction detection circuit.

Claims (1)

[Scope of Claims] 1. A vector register composed of a plurality of interleaved banks, and further has a plurality of timings for accessing each bank, and the plurality of timings are set in advance for each instruction for each instruction type. At least one instruction is assigned a plurality of timings in a predetermined manner, and a vector instruction that uses a vector register acquires a predetermined timing that is previously assigned to the vector instruction. In a vector processing device that accesses vector registers and executes processing, the number of timings pre-assigned to the vector instruction to be executed depending on the instruction type is greater than the number of timings required to execute the vector instruction. An empty timing instruction detection circuit 18 is provided for identifying that a vector instruction is a vector instruction having an empty timing, and when the empty timing instruction detection circuit 18 detects a vector instruction having an empty timing,
A vector instruction execution control method characterized by using the vacant timing to make other vector instructions executable.