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JPS5515246A - Bonding method for semiconductor substrate - Google Patents

Bonding method for semiconductor substrate

Info

Publication number
JPS5515246A
JPS5515246A JP8820078A JP8820078A JPS5515246A JP S5515246 A JPS5515246 A JP S5515246A JP 8820078 A JP8820078 A JP 8820078A JP 8820078 A JP8820078 A JP 8820078A JP S5515246 A JPS5515246 A JP S5515246A
Authority
JP
Japan
Prior art keywords
layer
bonding
solder
supporter
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8820078A
Other languages
Japanese (ja)
Inventor
Hiroyuki Fujii
Kenichi Tateno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP8820078A priority Critical patent/JPS5515246A/en
Publication of JPS5515246A publication Critical patent/JPS5515246A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To obtain a good bonding with no bubble and others on a bonding surface by making a Au-Si alloy layer on a supporter bonding surface of a Si substrate and by laminating a Au thin film thereon and bonding the layer to the supporter through a solder.
CONSTITUTION: A Au plating is provided for the bonding surface of a Si substrate and the plated surface is heated up to 400°C approximately and a Au-Si alloy layer is provided. Thereafter, a gold plating film of 0.1 to 0.5μm is added thereto. Because the weakness would be caused in a thermal cycle by the difference of thermalexpansion between AuSi and Si, the Au-Si layer thickness is restricted less than 0.1μm. According to this method, a cavity may not be caused in the Au layer if the intervention of the Au into the Au-Si layer is occurred, the Au serves only for improving the applying with the solder. Therefore, a uniform bonding can be established and the thermal fatigue be completely removed.
COPYRIGHT: (C)1980,JPO&Japio
JP8820078A 1978-07-18 1978-07-18 Bonding method for semiconductor substrate Pending JPS5515246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8820078A JPS5515246A (en) 1978-07-18 1978-07-18 Bonding method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8820078A JPS5515246A (en) 1978-07-18 1978-07-18 Bonding method for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS5515246A true JPS5515246A (en) 1980-02-02

Family

ID=13936247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8820078A Pending JPS5515246A (en) 1978-07-18 1978-07-18 Bonding method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5515246A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205370A (en) * 1984-03-30 1985-10-16 Tokyo Keiki Co Ltd Accelerometer
CN111785614A (en) * 2020-06-18 2020-10-16 上海空间电源研究所 A bonding structure for reducing voltage loss and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4939223A (en) * 1972-08-23 1974-04-12
JPS5286064A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4939223A (en) * 1972-08-23 1974-04-12
JPS5286064A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205370A (en) * 1984-03-30 1985-10-16 Tokyo Keiki Co Ltd Accelerometer
JPH037907B2 (en) * 1984-03-30 1991-02-04 Tokimetsuku Kk
CN111785614A (en) * 2020-06-18 2020-10-16 上海空间电源研究所 A bonding structure for reducing voltage loss and preparation method thereof
CN111785614B (en) * 2020-06-18 2022-04-12 上海空间电源研究所 A bonding structure for reducing voltage loss and preparation method thereof

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