JP5380244B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5380244B2 JP5380244B2 JP2009243258A JP2009243258A JP5380244B2 JP 5380244 B2 JP5380244 B2 JP 5380244B2 JP 2009243258 A JP2009243258 A JP 2009243258A JP 2009243258 A JP2009243258 A JP 2009243258A JP 5380244 B2 JP5380244 B2 JP 5380244B2
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- sealing body
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- semiconductor device
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
1.本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、本実施の形態の半導体装置1の構成について、図1〜図3を用いて説明する。
次に、半導体装置1の内部に搭載される半導体チップ4について、図4〜図6を用いて説明する。
次に、本実施の形態における半導体装置1の製造工程について、説明する。本実施の形態における半導体装置1は、図7に示す組立てフローに沿って製造される。各工程の詳細については、図8〜図37を用いて、以下に説明する。
まず、図7に示すリードフレーム準備工程S1として、図8に示すようなリードフレーム10を準備する。本実施の形態で使用するリードフレーム10には、枠体(枠部)10bの内側に複数のデバイス領域10aが形成されており、本実施の形態では、4つのデバイス領域10aを備えている。なお、枠体10bには、リードフレーム10を搬送するための送り穴(スプロケットホール)10cが形成されている。
次に、図7に示すダイボンディング工程S2について説明する。なお、ここからの説明で使用する図面については、図8のF部を抜粋した図面を使用する。また、図8のF部に対応する断面図では、見易さのため図面のアスペクト比を変更し、各部材の厚さを図2と比較して厚く示している。
次に、図7に示すワイヤボンディング工程S3について説明する。
次に、図7に示す封止工程S4について説明する。
次に、図7に示すベーク工程S5について説明する。
次に、図7に示すダムバーカット工程S6について説明する。
次に、図7に示すダム内樹脂除去工程(レーザ照射工程)S7について説明する。
次に、図7に示す洗浄工程S8について説明する。
次に、図7に示すめっき工程S9について説明する。
次に、図7に示すマーク工程S10について説明する。
次に、図7に示すリード成形工程S11について説明する。
次に、図7に示す個片化工程S12について説明する。
次に、本実施の形態で説明した半導体装置1を実装した電子装置(電子機器)について説明する。
2 封止体
2a 上面
2b 下面
2c 側面
2d マーク
2e 封止体(チップ封止用樹脂)
2f 封止体(ダム内樹脂)
2g 残留樹脂(封止体)
2h レジンバリ
3 リード
3a インナリード
3b アウタリード
3c 上面
3d 下面
3e 屈曲部形成領域
3f、3g 突出部
4 半導体チップ
4a 主面
4b 裏面
4c 側面
4d 電極パッド
4e 基板層
4f 絶縁膜
4g 開口部
4h めっき膜
4j 配線層
5 チップ搭載部
5a 上面
5b 下面
6 ダイボンド材
7 導電性部材
8 めっき膜
10 リードフレーム
10a デバイス領域
10b 枠体(枠部)
10c 送り穴(スプロケットホール)
11 吊りリード
11a インナ部
11b アウタ部
12 ダムバー
13 めっき膜
14 ピックアップ治具
15 ヒートステージ
15a 凹部
16 キャピラリ
20 成形金型
21 上型
21a 金型面
21b 凹部
22 下型
22a 金型面
22b 凹部
25 樹脂
26 切断刃
30 レーザ照射装置
31 レーザ
32 レーザ光源
33 ガルバノミラー
34 集光レンズ
35 電解液
36 浴槽
37 陽極
38 陰極
40 マスク
40a 開口部
41 高圧水
42 支持部材
45 めっき液
46 めっき槽
47 陰極
48 陽極
50 レーザ
51、53、53a、53b、55、55a、55b、57 ダイ
52、54、56、58 パンチ
53c 対向面
54a 対向面
56a 押さえ部
56b 可動部
56c 切断刃
60 電子装置
61 接合材
62 実装基板
62a 上面
63 電極パッド
71 リード
72 リードフレーム
C 仮想線
K 端部
Claims (18)
- 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)半導体チップを封止する第1封止体、前記第1封止体から露出する複数のリード、前記複数のリードと一体に形成されたダムバー、および前記第1封止体と前記複数のリードと前記ダムバーとで囲まれた領域に形成された第2封止体を有する半導体パッケージを準備する工程;
(b)切断刃を用いて前記ダムバーの一部、および前記第2封止体の一部を除去する工程;
(c)前記(b)工程の後、前記第2封止体の他部にレーザを照射し、前記第2封止体の前記他部を除去する工程;
(d)前記(c)工程の後、前記第1封止体から露出する前記複数のリードのそれぞれの表面を洗浄する工程;
(e)前記(d)工程の後、前記第1封止体から露出する前記複数のリードのそれぞれの前記表面にめっき膜を形成する工程、
ここで、
前記(a)工程で準備する前記半導体パッケージの前記複数のリードのそれぞれの前記表面には、前記第1封止体及び前記第2封止体のそれぞれの体積よりも小さい体積から成るレジンバリが形成されており、
前記(d)工程の前に、前記(c)工程で使用するレーザの出力値よりも低い出力値に設定されたレーザを前記レジンバリに照射し、前記レジンバリを除去する。 - 請求項1において、
前記(b)工程で除去する前記第2封止体の前記一部の量は、前記(c)工程で除去する前記第2封止体の前記他部の量よりも多いことを特徴とする半導体装置の製造方法。 - 請求項2において、
前記(b)工程で使用する前記切断刃の幅は、前記複数のリード間の距離よりも小さいことを特徴とする半導体装置の製造方法。 - 請求項3において、
前記(d)工程では、水圧が50乃至150kgf/cm2に設定された洗浄水を前記複数のリードの表面に向かって噴射することを特徴とする半導体装置の製造方法。 - 請求項1または請求項4において、
前記(c)工程では、前記第2封止体の表面に対して第1角度を有するように、前記レーザを照射することを特徴とする半導体装置の製造方法。 - 請求項1または請求項5において、
前記複数のリードのそれぞれの前記表面は、上面と、前記上面とは反対側の下面と、前記上面と前記下面との間の側面とを有し、
前記側面の平坦度は、前記上面、または前記下面の平坦度よりも低いことを特徴とする半導体装置の製造方法。 - 請求項6において、
前記(c)工程では、前記複数のリードのそれぞれの前記側面を、前記レーザの照射方向に対して傾けた状態で行うことを特徴とする半導体装置の製造方法。 - 請求項5において、
前記(c)工程では、集光レンズを介して前記レーザを照射することを特徴とする半導体装置の製造方法。 - 請求項1において、
前記(b)工程で使用する前記切断刃の幅は、前記複数のリードのうちの隣り合うリード間の距離よりも短く、
前記(b)工程により、前記複数のリードのそれぞれの前記表面に突出部が形成され、
前記第2封止体の前記他部は、前記第1封止体と前記複数のリードと前記突出部とで囲まれた領域に形成されていることを特徴とする半導体装置の製造方法。 - 請求項1において、
前記(e)工程の後、前記突出部を基点として、前記複数のリードのそれぞれを折り曲げることを特徴とする半導体装置の製造方法。 - 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)ダイパッド、前記ダイパッドと一体に形成された複数の吊りリード、前記複数の吊りリードの間に配置され、かつ前記ダイパッドの周囲に配置された複数のインナリード、前記複数のインナリードのそれぞれと一体に形成されたダムバー、前記ダムバーとそれぞれ一体に形成され、かつ前記ダムバーよりも前記複数のインナリードからそれぞれ遠い位置に形成された複数のアウタリード、および前記複数のアウタリードのそれぞれと一体に形成された枠体を有するリードフレームを準備する工程;
(b)主面、前記主面に形成された複数の電極パッド、および前記主面とは反対側の裏面を有する半導体チップを、ダイボンド材を介して前記ダイパッドに搭載する工程;
(c)複数の導電性部材を介して前記半導体チップの前記複数の電極パッドと前記複数のインナリードとをそれぞれ電気的に接続する工程;
(d)第1金型の第1金型面が前記リードフレームの上面に接触し、かつ第2金型の第2金型面が前記リードフレームの下面に接触するように、前記複数のインナリードのそれぞれの一部、前記ダムバー、および前記複数のアウタリードのそれぞれの一部を第1金型及び第2金型でクランプした状態で、前記半導体チップ、前記複数の導電性部材、および前記複数のインナリードのそれぞれの他部を樹脂で封止し、前記半導体チップ、前記複数の導電性部材、および前記複数のインナリードのそれぞれの前記他部を封止する第1封止体、および前記第1封止体と前記複数のインナリードのそれぞれの前記一部と前記ダムバーとで囲まれた領域を封止する第2封止体を形成する工程;
(e)切断刃を用いて前記ダムバーの一部、および前記第2封止体の一部を除去する工程;
(f)前記(e)工程の後、前記第2封止体の他部にレーザを照射し、前記第2封止体の前記他部を除去する工程;
(g)前記(f)工程の後、前記リードフレームのうちの前記第1封止体から露出した部分を洗浄する工程;
(h)前記(g)工程の後、前記リードフレームのうちの前記第1封止体から露出した部分にめっき膜を形成する工程;
ここで、
前記(e)工程で使用する前記切断刃の幅は、前記複数のアウタリードのうちの隣り合うアウタリード間の距離よりも短く、
前記(e)工程により、突出部が形成され、
前記第2封止体の前記他部は、前記第1封止体と前記複数のインナリードのそれぞれの前記一部と前記突出部とで囲まれた領域に形成されており、
前記(d)工程の後、前記リードフレームのうちの前記第1封止体から露出した部分には、前記第1封止体及び前記第2封止体のそれぞれの体積よりも小さい体積から成るレジンバリが形成されており、
前記(g)工程の前に、前記(f)工程で使用するレーザの出力値よりも低い出力値に設定されたレーザを前記レジンバリに照射し、前記レジンバリを除去する。 - 請求項11において、
前記(e)工程で除去する前記第2封止体の前記一部の量は、前記(f)工程で除去する前記第2封止体の前記他部の量よりも多いことを特徴とする半導体装置の製造方法。 - 請求項12において、
前記(h)工程の後、前記突出部を基点として、前記複数のアウタリードのそれぞれを折り曲げることを特徴とする半導体装置の製造方法。 - 請求項13において、
前記(g)工程では、水圧が50乃至150kgf/cm2に設定された洗浄水を前記複数のリードの表面に向かって噴射することを特徴とする半導体装置の製造方法。 - 請求項11または請求項14において、
前記(f)工程では、前記第2封止体の表面に対して第1角度を有するように、前記レーザを照射することを特徴とする半導体装置の製造方法。 - 請求項11または請求項15において、
前記複数のリードのそれぞれの前記表面は、上面と、前記上面とは反対側の下面と、前記上面と前記下面との間の側面とを有し、
前記側面の平坦度は、前記上面、または前記下面の平坦度よりも低いことを特徴とする半導体装置の製造方法。 - 請求項16において、
前記(f)工程では、前記複数のリードのそれぞれの前記側面を、前記レーザの照射方向に対して傾けた状態で行うことを特徴とする半導体装置の製造方法。 - 請求項15において、
前記(f)工程では、集光レンズを介して前記レーザを照射することを特徴とする半導体装置の製造方法。
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JP2007005569A (ja) * | 2005-06-24 | 2007-01-11 | Matsushita Electric Ind Co Ltd | リードフレームおよび半導体装置および切断装置および切断方法 |
JP2008098478A (ja) * | 2006-10-13 | 2008-04-24 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2008117875A (ja) * | 2006-11-02 | 2008-05-22 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2010283303A (ja) * | 2009-06-08 | 2010-12-16 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP5319571B2 (ja) * | 2010-02-12 | 2013-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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TWI532104B (zh) | 2016-05-01 |
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US8435867B2 (en) | 2013-05-07 |
US20110097854A1 (en) | 2011-04-28 |
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