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JP3526788B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP3526788B2
JP3526788B2 JP18765899A JP18765899A JP3526788B2 JP 3526788 B2 JP3526788 B2 JP 3526788B2 JP 18765899 A JP18765899 A JP 18765899A JP 18765899 A JP18765899 A JP 18765899A JP 3526788 B2 JP3526788 B2 JP 3526788B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
bumps
substrate
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18765899A
Other languages
English (en)
Other versions
JP2001015679A (ja
Inventor
伸仁 大内
茂 山田
靖 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP18765899A priority Critical patent/JP3526788B2/ja
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to US09/460,984 priority patent/US6201266B1/en
Priority to US09/757,663 priority patent/US6673651B2/en
Publication of JP2001015679A publication Critical patent/JP2001015679A/ja
Priority to US10/657,139 priority patent/US7723832B2/en
Application granted granted Critical
Publication of JP3526788B2 publication Critical patent/JP3526788B2/ja
Priority to US11/077,145 priority patent/US7592690B2/en
Priority to US11/077,152 priority patent/US7427810B2/en
Priority to US12/759,919 priority patent/US8008129B2/en
Priority to US13/205,581 priority patent/US8486728B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 【０００１】 【発明の属する技術分野】本発明は，半導体装置及びそ
の製造方法に関する。 【０００２】 【従来の技術】近年における携帯型電子機器の急速な普
及には目覚ましいものがある。これに伴って携帯型電子
機器に搭載される樹脂封止型半導体装置も薄型・小型・
軽量のものが要求されるようになっている。かかる要求
に応える高密度化の半導体装置としてチップサイズパッ
ケージと称されるものがある。このチップサイズパッケ
ージの構成の一例を，図１２を参照しながら説明する。 【０００３】半導体装置８２０は，図１２に示したよう
に，４００μｍ程度の厚みを有する半導体素子１ｂ上に
電極パッド６が形成され，電極パッド６に電気的に接続
するＣｕ等による配線２が形成されている。半導体素子
１ｂの表面及び配線２は，厚み１００μｍ程度の封止樹
脂５によって封止されている。封止樹脂５の表面に露出
した配線２の上面にははんだ等によるバンプ３が形成さ
れている。図中符号４は，電極パッド６と配線２とを電
気的に接続するＣｕ等による再配線である。 【０００４】この図１２に示した半導体装置８２０の製
造方法を，図１３を参照しながら説明する。まず，図１
３（Ａ）に示したように，半導体素子１ｂ上にＣｕ等に
よる配線２が形成される。なお，図１３（Ａ）では，上
記電極パッド６及び再配線４は図示していない。そし
て，図１３（Ｂ）に示したように，配線２を完全に覆う
厚みで半導体素子１ｂの表面全体を封止樹脂５により封
止する。次いで，図１３（Ｃ）に示したように，表面全
体を研削して配線２を表面に露出させた後，図１３
（Ｄ）に示したように，はんだ等によるバンプ３を形成
する。さらに，半導体素子１ｂを個々の半導体装置に切
断し分割することによって，半導体装置８２０が製造さ
れる。 【０００５】 【発明が解決しようとする課題】ところで，例えばメモ
リプロセスとロジックプロセスのように，半導体素子製
造のプロセス条件が異なる場合には，これらの異なる複
数の機能を一の半導体素子上に形成することは難しい。
かかる場合には，各機能の半導体装置を個別に製造して
おき，それらをプリント基板上に実装することが行われ
る。 【０００６】例えば，２つの半導体装置をプリント基板
１３に実装する場合について説明する。ここで第１の半
導体装置８１０は，半導体素子８１１及び金線８１５が
設けられたエポキシ基板８１６の片面を封止樹脂８０５
により封止し，裏面にはんだ等のバンプ８０３がエリア
状に形成されたＢＧＡ（ｂａｌｌ ｇｒｉｄ ａｒｒａ
ｙ）構造と称される半導体装置であり，第２の半導体装
置は上述の半導体装置８２０であり，それぞれ個別に製
造されたものである。これら個別に製造された２つの半
導体装置８１０，８２０の実装を，図１４に示したよう
に，プリント基板１３の同一平面上で行うと，高密度基
板実装を図ることが難しいという問題があった。 【０００７】また，上記問題点を解決するために，図１
５に示したように，半導体素子１ａ，１ｂを積み重ね，
金属細線１５ａ，１５ｂを配線１４に接続した後に樹脂
封止する構成がある。かかる構成によれば，基板実装面
積を増加させることなく高密度実装を図ることができ
る。しかしながら，半導体装置全体の歩留まりの点にお
いては，以下の問題点があった。すなわち，通常，半導
体素子はウェハの状態で簡易的な特性チェックがされる
が，最終テスト（出荷テスト）は，組立後の半導体装置
としてのみ実施がされる。したがって，最終テストの済
んでいない２つの半導体素子を搭載して半導体装置を製
造すると，半導体装置全体としての歩留まりは２つの半
導体素子の歩留まりの積となる。このため高密度実装化
に反比例して歩留まりの低下が生じ，コストアップにつ
ながるという問題点があった。 【０００８】本発明は，従来の半導体装置が有する上記
問題点に鑑みてなされたものであり，本発明の目的は，
歩留まりの低下を抑えつつ，高密度実装化を図ることの
可能な，新規かつ改良された半導体装置及びその製造方
法を提供することである。 【０００９】 【課題を解決するための手段】上記課題を解決するた
め，本発明の第１の観点によれば，半導体装置におい
て，表面に複数のバンプが形成された第１の半導体装置
と，複数の端子が形成され，第１の半導体装置の表面の
バンプが形成されていない領域に，端子が形成された面
が第１の半導体装置の表面と接合されることにより，第
１の半導体装置に搭載される第２の半導体装置と；第２
の半導体装置の端子が形成されていない面に貼着された
熱伝導性の高い接着部材と；を含むことを特徴とする，
半導体装置が提供される。 【００１０】第２の半導体装置の第１の半導体装置への
搭載の第１の例としては，請求項２に記載のように，第
２の半導体装置は，第２の半導体装置の端子が形成され
ていない面が第１の半導体装置の表面と接着剤により接
合されることにより第１の半導体装置に搭載される。 【００１１】 【００１２】 【００１３】 【００１４】 【００１５】かかる構成によれば，第１の半導体装置及
び第２の半導体装置がそれぞれ最終テスト済みであるた
め，歩留まりの低下を抑えつつ，高密度実装化を図るこ
とが可能である。さらに，第２の半導体装置の端子が形
成された面側を第１の半導体装置と接合したので，装置
全体の端子が増えず，後工程のプリント基板への実装が
容易になる。また，第２の半導体装置の放熱性を向上さ
せることが可能である。 【００１６】 【００１７】また，第１の半導体装置の表面には，バン
プと第２の半導体装置の端子とを電気的に導通させるた
めの配線パターンが形成されており，第２の半導体装置
の端子は，はんだを介して配線パターンに電気的に接続
されている構成としてもよい。 【００１８】また，第１の半導体装置は，エポキシ基板
と，エポキシ基板の表面に設けられた半導体素子及び配
線と，半導体素子上の電極と配線とを接続する金属細線
と，を含む構成としてもよい。 【００１９】また，第１の半導体装置は封止樹脂によっ
て封止されている構成としてもよい。かかる構成によれ
ば，接着剤やはんだ等の別の固着材が不要である。この
ため，工程の簡略化，コスト低減が可能である。 【００２０】また，上記課題を解決するため，本発明の
第２の観点によれば，表面に複数のバンプが形成された
第１の半導体装置と，表面にバンプと電気的に接続され
る複数の端子が形成され，第１の半導体装置の表面のバ
ンプが形成されていない領域に搭載される第２の半導体
装置とを含む半導体装置の製造方法が提供される。そし
てこの半導体装置の製造方法は，基板表面に複数のバン
プを形成する工程と，第２の半導体装置をマウントテー
プ上に複数並べる工程と，マウントテープ上に並べられ
た複数の第２の半導体装置を基板上に搭載する工程と，
基板を個々の半導体装置に分割する工程とを含むことを
特徴とする。なお，第２の半導体装置をマウントテープ
上に複数並べる工程は，基板上に複数の端子を形成する
工程と，複数の端子を樹脂封止する工程と，樹脂表面か
ら溝を形成し，素子基板の所定深さまで到達させる工程
と，基板の樹脂形成面に研削テープを貼付する工程と，
基板の裏面を溝の底部に達するまで研削する工程と，研
削した面にマウントテープを貼付する工程と，研削テー
プを除去する工程とを含むようにすると容易に実現でき
る。 【００２１】かかる製造方法によれば，第１の半導体装
置の表面のバンプがない領域に容易に第２の半導体装置
を搭載することができるので，上述のすぐれた効果を奏
する半導体装置を容易に製造することが可能である。 【００２２】 【００２３】 【発明の実施の形態】以下に添付図面を参照しながら，
本発明にかかる半導体装置及びその製造方法の好適な実
施の形態について詳細に説明する。なお，本明細書及び
図面において，実質的に同一の機能構成を有する構成要
素については，同一の符号を付することにより重複説明
を省略する。 【００２４】（第１の実施の形態）本実施の形態にかか
る半導体装置１００を，図１を参照しながら説明する。
半導体装置１００は，図１（Ａ）に示したように，表面
にはんだ等のバンプ３が例えば格子状に形成された第１
の半導体装置１１０と，複数の端子２を有し，第１の半
導体装置１１０の表面のバンプ３が形成されていない領
域に搭載される第２の半導体装置１２０とを含んでい
る。第１の半導体装置１１０のバンプ３と第２の半導体
装置１２０の端子２とは，後工程で半導体装置１００が
プリント基板１３に実装される際に，プリント基板１３
上の配線により，電気的に接続される。 【００２５】第１の半導体装置１１０及び第２の半導体
装置１２０の製造方法について，図２及び図３を参照し
ながら説明する。 【００２６】（第１の半導体装置１１０） まず，図２を参照しながら，第１の半導体装置１１０に
ついて説明する。まず，図２（Ａ）に示したように，エ
ポキシ基板１６の表面に半導体素子１ａ及び配線１４を
設ける。そして，図２（Ｂ）に示したように，半導体素
子１ａ上の電極と配線１４とを金属細線１５ａにより接
続する。その後，図２（Ｃ）に示したように，これらエ
ポキシ基板１６上の各構成部材を覆うように封止樹脂５
で封止する。さらに，エポキシ基板１６の裏面にバンプ
３を形成する。このエポキシ基板１６にはスルーホール
１７が形成されており，配線４は裏面のバンプ３と電気
的に導通している。 【００２７】バンプ３の高さは，後工程で第１の半導体
装置１１０に搭載する第２の半導体装置１２０の高さと
実質的に同じか，わずかに高い寸法となっている。ま
た，バンプ３は，後工程で半導体装置１００がプリント
基板１３に実装される際の熱処理により溶融する。 【００２８】（第２の半導体装置１２０） 次いで，図３を参照しながら，第２の半導体装置１２０
の製造方法について説明する。まず，図３（Ａ）に示し
たように，半導体素子１ｂ上に電気メッキ等により，高
さ約５０μｍのＣｕの配線２を形成する。次いで，図３
（Ｂ）に示したように，配線２を完全に覆う厚みで半導
体素子１ｂの表面全体を封止樹脂５ｂにより封止する。
樹脂封止方法はトランスファーモールド法，ポッティン
グ法，印刷法等が用いられる。次いで，図３（Ｃ）に示
したように，表面全体を研削して配線２を表面に露出さ
せる。 【００２９】次いで，図３（Ｄ）に示したように，後工
程で切断し分割する部分に所定の深さで溝９を形成す
る。溝９の深さは最終的に個々の半導体装置とした場合
の半導体素子１ｂの厚みに基づいて決定する。半導体素
子１ｂの厚みを１００μｍとする場合，溝は約２０μｍ
深く形成し約１２０μｍとする。そして，封止樹脂５ｂ
の厚みも加えて合計で１７０μｍの深さとなる。 【００３０】次いで，裏面研削工程を行う。まず，図３
（Ｅ）に示したように，溝９が形成された半導体素子１
ｂの樹脂形成面に研削テープ２０を貼付する。この研削
テープ２０は紫外線を照射することによって，粘着力が
落ち，簡単に剥がせるものである。次いで，研削テープ
２０を貼付した面を研削ステージ（図示しない）に吸着
により固定する。裏面の研削は，図３（Ｆ）に示したよ
うに，上述の溝９の底部に達するまで行う。こうして研
削テープ１２上に個々に分割された半導体装置（第２の
半導体装置１２０）が並ぶ状態となる。 【００３１】次いで，図３（Ｇ）に示したように，研削
した面にマウントテープ２１が貼付される。そして，研
削テープ２０は紫外線が照射されて除去される。この第
２の半導体装置１２０がマウントテープ２１に並べられ
た状態で，第１の半導体装置１１０へと搭載される。 【００３２】第２の半導体装置１２０の第１の半導体装
置１２０への搭載は，第１の半導体装置１１０のバンプ
３が形成されていない領域に第２の半導体装置１２０を
接着剤１１５を用いて搭載する。この接着剤１１５は，
第１の半導体装置１１０に供給しておくこともできる
が，マウントテープ２１に接着剤１１５を設けることも
可能である。以上の工程により，第１の実施の形態にか
かる半導体装置１００が製造される。半導体装置１００
は，後工程により，図１（Ｂ）に示したように，プリン
ト基板１３に実装される。このとき，第２の半導体装置
１２０の端子２は，プリント基板１３にはんだ１８によ
り電気的に接続される。ここで，はんだ１８は，あらか
じめプリント基板１３に塗布されているはんだペースト
であり，このはんだペーストは，バンプ３及び端子２に
対応してそれぞれ形成されている。 【００３３】以上のように半導体装置１００によれば，
第２の半導体装置１２０は，第１の半導体装置１１０の
表面のバンプ３が形成されていない領域に搭載される。
そして，第１の半導体装置１１０及び第２の半導体装置
１２０がそれぞれ最終テスト済みであるため，歩留まり
の低下を抑えつつ，高密度実装化を図ることが可能であ
る。 【００３４】なお，本実施の形態においては，第１の半
導体装置１１０にＢＧＡ構造の半導体装置を採用した場
合の一例につき説明したが，本発明はこれに限定されな
い。例えば図４（Ａ）に示したように，第１の半導体装
置として，第２の半導体装置１２０と同様のチップサイ
ズパッケージの第１の半導体装置１１０’を採用し，半
導体装置１００’を構成することも可能である。この第
１の半導体装置１１０’は，図４（Ｂ）に示したよう
に，上記第１の半導体装置１１０と同様，第２の半導体
装置１２０を搭載する領域には，電極２及びバンプ３が
形成されていない。なお，以下の実施の形態においても
同様である。 【００３５】（第２の実施の形態）本実施の形態にかか
る半導体装置２００は，上記半導体装置１００を改良し
たものであり，第２の半導体装置２２０の端子が形成さ
れていない面が第１の半導体装置２１０の表面と接着剤
２１２により接合されることにより，第１の半導体装置
２１０に搭載される点で上記半導体装置１００と共通す
る。以下に，半導体装置２００の改良点につき，図５を
参照しながら説明する。なお，略同一の構成要素につい
ては同一符号を付すことで詳細な説明を省略する。 【００３６】半導体装置２００においては，第１の半導
体装置２１０のバンプ３が形成されていない所定の領域
に，第２の半導体装置２２０の大きさに合わせて浅く平
滑に削った凹部（座繰り部）２１５が形成されている。
そして，第２の半導体装置２２０はこの座繰り部２１５
に搭載される。 【００３７】半導体装置２００は，後工程により，図５
（Ｂ）に示したように，プリント基板１３に実装され
る。このとき，座繰り部２１５を形成したことにより第
２の半導体装置２２０とプリント基板１３との間に広い
空間をとることができるので，図５（Ｂ）に示したよう
に，素子間の接続の信頼性を向上させるためのはんだ等
のバンプ３ｂを形成することができる。 【００３８】以上のように，半導体装置２００によれ
ば，第２の半導体装置２２０を搭載する領域に厚み方向
の広い空間を取ることができるので，第２の半導体装置
２２０が多少厚みのあるものであっても搭載することが
できる。また，この空間にはんだ等のバンプ３ｂを形成
することにより，素子間の接続の信頼性を向上させるこ
とが可能である。 【００３９】（第３の実施の形態）本実施の形態にかか
る半導体装置３００は，上記半導体装置１００を改良し
たものであり，第２の半導体装置３２０の端子が形成さ
れていない面が第１の半導体装置３１０の表面と接着剤
により接合されることにより，第１の半導体装置３１０
に搭載される点で上記半導体装置１００と共通する。以
下に，半導体装置３００の改良点につき，図６を参照し
ながら説明する。なお，略同一の構成要素については同
一符号を付すことで詳細な説明を省略する。 【００４０】半導体装置３００は，図６（Ａ）に示した
ように，第２の半導体装置３２０の裏面と，第１の半導
体装置３１０とを接合する接着剤に，所定の温度以上で
接着性を失う低分子接着剤３１５を用いたことを特徴と
している。ここで所定の温度とは，半導体装置３００を
プリント基板１３に実装する際のリフロー等の熱処理時
の温度であり，例えば２００℃以上で接着性を失う低分
子接着剤を用いることができる。 【００４１】半導体装置３００は，後工程により，図６
（Ｂ）に示したように，プリント基板１３に実装され
る。このとき，低分子接着剤３１５は接着力を失い，第
１の半導体装置３１０と第２の半導体装置３２０とは分
離される。 【００４２】以上のように半導体装置３００によれば，
半導体装置３００をプリント基板１３に実装する際に，
第１の半導体装置３１０と第２の半導体装置３２０とを
分離して，個別に位置合わせすることができる。かかる
セルフアライメント効果により，正確な位置に実装する
ことが可能である。 【００４３】（第４の実施の形態）本実施の形態にかか
る半導体装置４００を，図７を参照しながら説明する。
なお，第１の実施の形態にかかる半導体装置１００と略
同一の構成要素については同一符号を付すことで詳細な
説明を省略する。 【００４４】上記半導体装置１００では，第２の半導体
装置１２０の端子が形成されていない面が第１の半導体
装置１１０の表面と接着剤１１５により接合されること
により，第１の半導体装置１１０に搭載されていた。本
実施の形態にかかる半導体装置４００では，図７（Ａ）
に示したように，第２の半導体装置４２０の端子２が第
１の半導体装置４１０の表面とはんだ４１５により接合
されることにより，第１の半導体装置４１０に搭載され
ることを特徴としている。 【００４５】第１の半導体装置４１０のバンプ３が形成
されたエポキシ基板１６の裏面には，バンプ３と第２の
半導体装置４２０の端子２とを電気的に導通させるため
の配線パターンが形成されている。上記構成によれば，
エポキシ基板１６の裏面で第１の半導体装置４１０と第
２の半導体装置４２０とは電気的に接続される。 【００４６】以上のように半導体装置４００によれば，
図７（Ｂ）に示したように，後工程でプリント基板１３
に実装する際に，装置全体の端子が増えていないため，
容易に実装することが可能である。 【００４７】なお，本実施の形態においては，第１の半
導体装置４１０にＢＧＡ構造の半導体装置を採用した場
合の一例につき説明したが，本発明はこれに限定されな
い。例えば図８（Ａ）に示したように，第１の半導体装
置として，第２の半導体装置４２０と同様のチップサイ
ズパッケージの第１の半導体装置４１０’を採用し，半
導体装置４００’を構成することも可能である。この第
１の半導体装置４１０’は，図８（Ｂ）に示したよう
に，上記第１の半導体装置４１０と同様，第２の半導体
装置４２０を搭載する領域には，バンプ３が形成されて
おらず，端子２が露出している。そして，この第１の半
導体装置４１０’の端子２と，第２の半導体装置４２０
の端子２とが，はんだ４１５により電気的に接続され
る。なお，以下の実施の形態においても同様である。 【００４８】（第５の実施の形態）本実施の形態にかか
る半導体装置５００は，上記半導体装置４００を改良し
たものであり，第２の半導体装置５２０の端子が第１の
半導体装置５１０の表面とはんだ５１４により接合され
ることにより，第１の半導体装置５１０に搭載される点
で上記半導体装置４００と共通する。以下に，半導体装
置５００の改良点につき，図９を参照しながら説明す
る。なお，略同一の構成要素については同一符号を付す
ことで詳細な説明を省略する。 【００４９】半導体装置５００は，図９（Ａ）に示した
ように，第２の半導体装置５１０の裏面に，熱伝導性の
高い接着部材５１５が貼付されることを特徴としてい
る。この接着部材５１５は，図示した例では，所定厚み
のシート状をしている。 【００５０】半導体装置５００は，後工程により，図９
（Ｂ）に示したように，プリント基板１３に実装され
る。このとき，第２の半導体装置５２０は，接着部材５
１５の接着力によりプリント基板１３に安定して固定さ
れる。 【００５１】以上のように半導体装置５００によれば，
第２の半導体装置５２０は，熱伝導性の高い接着部材６
１７を介してプリント基板１３に接続されているため，
第２の半導体装置５２０の放熱性を向上させることが可
能である。 【００５２】（第６の実施の形態）本実施の形態にかか
る半導体装置６００は，上記半導体装置４００を改良し
たものであり，第２の半導体装置６２０の端子が第１の
半導体装置６１０の表面とはんだにより接合されること
により，第１の半導体装置６１０に搭載される点で上記
半導体装置４００と共通する。以下に，半導体装置６０
０の改良点につき，図１０を参照しながら説明する。な
お，略同一の構成要素については同一符号を付すことで
詳細な説明を省略する。 【００５３】半導体装置６００は，第２の半導体装置６
２０の端子面と，第１の半導体装置６１０とを接合する
はんだに，高融点はんだ６１５を用いたことを特徴とし
ている。ここで高融点とは，後工程で半導体装置６００
をプリント基板１３に実装する際の温度より高い融点で
あり，例えば２００℃以上の融点を持つ高融点はんだ６
１５を用いることができる。 【００５４】以上説明したように半導体装置６００によ
れば，プリント基板１３への実装時のリフロー等の熱処
理を行っても，第２の半導体装置６２０は，第１の半導
体装置６１０に高融点はんだで接合されているため，安
定した基板実装が可能である。 【００５５】（第７の実施の形態）本実施の形態にかか
る半導体装置７００を，図１１を参照しながら説明す
る。なお，第１の実施の形態にかかる半導体装置１００
と略同一の構成要素については同一符号を付すことで詳
細な説明を省略する。 【００５６】上記半導体装置１００では，第２の半導体
装置１２０は，その裏面が第１の半導体装置１１０の表
面と接着剤１１５により接合されることにより，第１の
半導体装置１１０に搭載されていた。本実施の形態にか
かる半導体装置７００では，図１１に示したように，第
２の半導体装置７２０は，その裏面が第１の半導体装置
７１０の表面と封止樹脂７１５により接合されることに
より，第１の半導体装置７１０に搭載されることを特徴
としている。 【００５７】第１の半導体装置７１０は，所定のパター
ン加工が施され，必要に応じて放熱板７０２が設けられ
たエポキシ基板１６に，半導体素子１ａを接着剤により
固着する。そして，半導体素子１ａ上の電極と，エポキ
シ基板１６とを金属細線１５ａで接続する。エポキシ基
板１６はその表面で電気的に導通され，第１の半導体装
置７１０の裏面に形成されたバンプ３と電気的に接続さ
れている。 【００５８】第２の半導体装置７２０は，上記第１の半
導体装置７１０の封止樹脂７１５の直後の封止樹脂７１
５が凝固しないうちに，この封止樹脂７１５に接するよ
うに載置される。封止樹脂７１５が凝固すると，第１の
半導体装置７１０と第２の半導体装置７２０とは，一体
となって固着される。 【００５９】以上のように半導体装置７００によれば，
第２の半導体装置は，第１の半導体装置の樹脂封止部に
直接接着されており，接着剤などの別の固着材は不要で
あるため，工程の簡略化，コスト低減が可能である。 【００６０】以上，添付図面を参照しながら本発明にか
かる半導体装置及びその製造方法の好適な実施形態につ
いて説明したが，本発明はかかる例に限定されない。当
業者であれば，特許請求の範囲に記載された技術的思想
の範疇内において各種の変更例または修正例に想到し得
ることは明らかであり，それらについても当然に本発明
の技術的範囲に属するものと了解される。 【００６１】 【発明の効果】以上説明したように，本発明によれば，
歩留まりの低下を抑えつつ，高密度実装化を図ることが
可能である。さらに，半導体装置の放熱性を向上させる
ことができる。 【００６２】 【００６３】 【００６４】 【００６５】 【００６６】
【図面の簡単な説明】 【図１】第１の実施の形態にかかる半導体装置の説明図
である。 【図２】第１の半導体装置の製造方法の説明図である。 【図３】第２の半導体装置の製造方法の説明図である。 【図４】第１の実施の形態にかかる半導体装置の応用例
の説明図である。 【図５】第２の実施の形態にかかる半導体装置の説明図
である。 【図６】第３の実施の形態にかかる半導体装置の説明図
である。 【図７】第４の実施の形態にかかる半導体装置の説明図
である。 【図８】第４の実施の形態にかかる半導体装置の応用例
の説明図である。 【図９】第５の実施の形態にかかる半導体装置の説明図
である。 【図１０】第６の実施の形態にかかる半導体装置の説明
図である。 【図１１】第７の実施の形態にかかる半導体装置の説明
図である。 【図１２】従来の半導体装置の説明図である。 【図１３】従来の半導体装置の製造方法の説明図であ
る。 【図１４】従来の半導体装置の問題点の説明図である。 【図１５】従来の半導体装置の問題点の説明図である。 【符号の説明】 １ａ，１ｂ半導体素子 ２ 配線 ３，３ｂ バンプ ５ａ，５ｂ 封止樹脂 １３ プリント基板 １４ 配線 １５ 金属配線 １６ エポキシ基板 １７ スルーホール １００，２００，・・・，７００，１００’，４００’
半導体装置 １１０，２１０，・・・，７１０，１１０’，４１０’
第１の半導体装置 １２０，２２０，・・・，７２０ 第２の半導体装置 １１５ 接着剤 ２１５ 座繰り部 ３１５ 低分子接着剤 ４１５ はんだ ５１５ 熱伝導性接着部材 ６１５ 高融点はんだ ７１５ 封止樹脂
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平10−93013（ＪＰ，Ａ) 特開 平９−181256（ＪＰ，Ａ) 特開 昭59−117146（ＪＰ，Ａ) 特開 平10−12810（ＪＰ，Ａ) 特開 平７−240496（ＪＰ，Ａ) 特開2000−340736（ＪＰ，Ａ) 特開 平11−312780（ＪＰ，Ａ) 実開 平３−83940（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/065 H01L 25/07 H01L 25/18

Claims (1)

  1. (57)【特許請求の範囲】 【請求項１】 表面に複数のバンプが形成された第１の
    半導体装置と、表面に前記バンプと電気的に接続される
    複数の端子が形成され、前記第１の半導体装置の表面の
    前記バンプが形成されていない領域に搭載される第２の
    半導体装置とを含む半導体装置の製造方法において： 基板表面に複数の前記バンプを形成する工程と； 前記第２の半導体装置をマウントテープ上に複数並べる
    工程と； 前記マウントテープ上に並べられた複数の前記第２の半
    導体装置を前記基板上に搭載する工程と； 前記基板を個々の半導体装置に分割する工程と； を含み、 前記第２の半導体装置をマウントテープ上に複数並べる
    工程は、素子 基板上に複数の前記端子を形成する工程と； 前記複数の前記端子を樹脂封止する工程と； 前記樹脂表面から溝を形成し、前記素子基板の所定の深
    さまで到達させる工程と； 前記素子基板の樹脂形成面に研削テープを貼付する工程
    と； 前記素子基板の裏面を前記溝の底部に達するまで研削す
    る工程と； 前記工程で研削した面に前記マウントテープを貼付する
    工程と； 前記研削テープを除去する工程と； を含むことを特徴とする半導体装置の製造方法。
JP18765899A 1999-07-01 1999-07-01 半導体装置の製造方法 Expired - Fee Related JP3526788B2 (ja)

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US09/460,984 US6201266B1 (en) 1999-07-01 1999-12-15 Semiconductor device and method for manufacturing the same
US09/757,663 US6673651B2 (en) 1999-07-01 2001-01-11 Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US10/657,139 US7723832B2 (en) 1999-07-01 2003-09-09 Semiconductor device including semiconductor elements mounted on base plate
US11/077,145 US7592690B2 (en) 1999-07-01 2005-03-11 Semiconductor device including semiconductor elements mounted on base plate
US11/077,152 US7427810B2 (en) 1999-07-01 2005-03-11 Semiconductor device including semiconductor element mounted on another semiconductor element
US12/759,919 US8008129B2 (en) 1999-07-01 2010-04-14 Method of making semiconductor device packaged by sealing resin member
US13/205,581 US8486728B2 (en) 1999-07-01 2011-08-08 Semiconductor device including semiconductor elements mounted on base plate

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