JP2019501519A - コンタクトにおいて黒鉛インタフェースを備えるグラフェンfet - Google Patents
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Abstract
Description
Claims (16)
- グラフェン電界効果トランジスタ(FET)のためのコンタクトを形成するための方法であって、
基板上にグラフェン表面を有するグラフェン層を提供すること、
前記グラフェン表面上に4.3eVより大きい仕事関数(WF)を有する第1の金属層を堆積すること、
第1の金属酸化物層を形成するため、前記第1の金属層を酸化させること、
それぞれ、グラフェン表面ソースコンタクト及びグラフェン表面ドレインコンタクトを提供するため、前記グラフェン層の第1及び第2の領域を含むオープン表面コンタクト領域を提供するように前記第1の金属酸化物層をエッチングすること、
前記グラフェン表面ソースコンタクトの上にソースコンタクトを備えるソースを提供する第2の金属層の部分と、前記グラフェン表面ドレインコンタクトの上にドレインコンタクトを備えるドレインを提供する第2の金属層の部分とを含む第2の金属層を堆積すること、及び
前記ソースコンタクトと前記グラフェン表面ソースコンタクトとの間及び前記ドレインコンタクトと前記グラフェン表面ドレインコンタクトとの間のインタフェースにおいて、グロウンイン(grown-in)黒鉛インタフェース層を形成すること、
を含む、方法。 - 請求項1に記載の方法であって、前記黒鉛インタフェース層を形成することが、200℃を超える温度で炭素前駆物質ガスを含む雰囲気において前記基板を加熱することを含む、方法。
- 請求項1に記載の方法であって、
前記第2の金属層を形成することが、炭素事前飽和された第2の金属層を形成するために第2の金属層を炭素で事前飽和させることを含み、
前記黒鉛インタフェース層を形成することが、前記黒鉛インタフェース層を形成するため前記炭素事前飽和された第2の金属層から前記炭素を沈殿させるために、前記第2の金属層のCでの等温過飽和、及び前記インタフェースへのC拡散、又は前記炭素事前飽和された第2の金属層の冷却を含む、
方法。 - 請求項1に記載の方法であって、前記黒鉛インタフェース層を形成することが、前記第2の金属層の炭素イオン注入、又は前記第2の金属層の頂部上にアモルファスC層を堆積すること、及びその後、200℃〜1,000℃の温度範囲でアニーリングすることを含む、方法。
- 請求項1に記載の方法であって、前記第1の金属層が、Al、Ti、Hf、Zr、V、Y、La、Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、又はLuを含む、方法。
- 請求項1に記載の方法であって、前記第2の金属層が、Ni、Co、Cu、Ru、Rh、又はPdを含む、方法。
- 請求項1に記載の方法であって、前記第1の金属酸化物層を形成することが、
前記グラフェン表面上に前記第1の金属層を堆積すること、
前記第1の金属酸化物層を形成するため前記第1の金属層を酸化させること、及び
前記オープン表面コンタクト領域を提供するため、前記第1の金属酸化物層をパターニングすること、
を含む、方法。 - 請求項1に記載の方法であって、前記グラフェン層がカーボンナノチューブ(CNT)の形態である、方法。
- 請求項1に記載の方法であって、前記黒鉛インタフェース層が、2〜30層のグラフェンを含む、方法。
- グラフェン電界効果トランジスタ(FET)であって、
基板上にグラフェン表面を有するグラフェン層、
前記グラフェン層のチャネル部の上に形成されるゲート誘電体層、
それぞれ、グラフェン表面ソースコンタクト及びグラフェン表面ドレインコンタクトを提供するために、前記グラフェン層の第1及び第2の領域を含むオープン表面コンタクト領域(コンタクト領域)を備える4.3eVより大きい仕事関数(WF)を有する第1の金属を含むパターニングされる第1の金属酸化物、
前記グラフェン表面ソースコンタクトの上にソースコンタクトを備えるソースを提供する第2の金属層の部分と、前記グラフェン表面ドレインコンタクトの上にドレインコンタクトを備えるドレインを提供する第2の金属層の部分とを含む第2の金属層であって、少なくとも1017atms/cm3の炭素濃度を含む、前記第2の金属層、
前記ソースコンタクトと前記グラフェン表面ソースコンタクトとの間、及び前記ドレインコンタクトと前記グラフェン表面ドレインコンタクトとの間の黒鉛インタフェース層、及び
前記グラフェン層の前記チャネル部の上の頂部ゲート構造及びバックゲート構造のうち少なくとも一方、
を含む、グラフェンFET。 - 請求項10に記載のFETであって、前記第1の金属が、Al、Ti、Hf、Zr、V、Y、la、Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、又はLuを含む、グラフェンFET。
- 請求項10に記載のFETであって、前記第2の金属層が、Ni、Co、Cu、Ru、又はPdを含む、グラフェンFET。
- 請求項10に記載のFETであって、前記基板がシリコンを含む、グラフェンFET。
- 請求項10に記載のFETであって、グラフェン層がカーボンナノチューブ(CNT)の形態である、グラフェンFET。
- 請求項10に記載のFETであって、前記黒鉛インタフェース層が、2〜30層のグラフェンを含む、グラフェンFET。
- 請求項10に記載のFETであって、前記黒鉛インタフェース層がBernal積層される、グラフェンFET。
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US20180130882A1 (en) | 2018-05-10 |
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WO2017078750A1 (en) | 2017-05-11 |
CN108352323A (zh) | 2018-07-31 |
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CN116387343A (zh) | 2023-07-04 |
US20170133468A1 (en) | 2017-05-11 |
US10923567B2 (en) | 2021-02-16 |
US9882008B2 (en) | 2018-01-30 |
US20200185498A1 (en) | 2020-06-11 |
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EP3371822A1 (en) | 2018-09-12 |
US10593763B2 (en) | 2020-03-17 |
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US20190115433A1 (en) | 2019-04-18 |
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