DE68922817D1 - Halbleiteranordnungen mit eng beabstandeten Gebieten, hergestellt unter Verwendung eines selbstausrichtenden Umkehrbildverfahrens. - Google Patents
Halbleiteranordnungen mit eng beabstandeten Gebieten, hergestellt unter Verwendung eines selbstausrichtenden Umkehrbildverfahrens.Info
- Publication number
- DE68922817D1 DE68922817D1 DE68922817T DE68922817T DE68922817D1 DE 68922817 D1 DE68922817 D1 DE 68922817D1 DE 68922817 T DE68922817 T DE 68922817T DE 68922817 T DE68922817 T DE 68922817T DE 68922817 D1 DE68922817 D1 DE 68922817D1
- Authority
- DE
- Germany
- Prior art keywords
- manufactured
- self
- semiconductor devices
- closely spaced
- image process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/009—Bi-MOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/261,952 US5015594A (en) | 1988-10-24 | 1988-10-24 | Process of making BiCMOS devices having closely spaced device regions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE68922817D1 true DE68922817D1 (de) | 1995-06-29 |
| DE68922817T2 DE68922817T2 (de) | 1995-11-30 |
Family
ID=22995583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE68922817T Expired - Fee Related DE68922817T2 (de) | 1988-10-24 | 1989-09-26 | Halbleiteranordnungen mit eng beabstandeten Gebieten, hergestellt unter Verwendung eines selbstausrichtenden Umkehrbildverfahrens. |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5015594A (de) |
| EP (1) | EP0366587B1 (de) |
| JP (1) | JPH07105457B2 (de) |
| CA (1) | CA1300764C (de) |
| DE (1) | DE68922817T2 (de) |
Families Citing this family (65)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5223449A (en) * | 1989-02-16 | 1993-06-29 | Morris Francis J | Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors |
| US5138420A (en) * | 1989-11-24 | 1992-08-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having first and second type field effect transistors separated by a barrier |
| US5234847A (en) * | 1990-04-02 | 1993-08-10 | National Semiconductor Corporation | Method of fabricating a BiCMOS device having closely spaced contacts |
| JPH03286562A (ja) * | 1990-04-03 | 1991-12-17 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| US5198374A (en) * | 1990-04-03 | 1993-03-30 | Oki Electric Industry Co., Ltd. | Method of making biCMOS integrated circuit with shallow N-wells |
| US5102809A (en) * | 1990-10-11 | 1992-04-07 | Texas Instruments Incorporated | SOI BICMOS process |
| JP2625602B2 (ja) * | 1991-01-18 | 1997-07-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 集積回路デバイスの製造プロセス |
| US5202591A (en) * | 1991-08-09 | 1993-04-13 | Hughes Aircraft Company | Dynamic circuit disguise for microelectronic integrated digital logic circuits |
| JPH05110003A (ja) * | 1991-10-16 | 1993-04-30 | Nec Corp | 半導体集積回路装置およびその製造方法 |
| JP3175973B2 (ja) * | 1992-04-28 | 2001-06-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US5376816A (en) * | 1992-06-24 | 1994-12-27 | Nec Corporation | Bi-cmos integrated circuit device having buried region use in common for bipolar and mos transistors |
| US5407841A (en) * | 1992-10-30 | 1995-04-18 | Hughes Aircraft Company | CBiCMOS fabrication method using sacrificial gate poly |
| JPH07169771A (ja) * | 1993-12-15 | 1995-07-04 | Nec Corp | 半導体装置及びその製造方法 |
| US5376578A (en) * | 1993-12-17 | 1994-12-27 | International Business Machines Corporation | Method of fabricating a semiconductor device with raised diffusions and isolation |
| KR0137974B1 (ko) * | 1994-01-19 | 1998-06-15 | 김주용 | 반도체 장치 및 그 제조방법 |
| US5604159A (en) | 1994-01-31 | 1997-02-18 | Motorola, Inc. | Method of making a contact structure |
| KR0120572B1 (ko) * | 1994-05-04 | 1997-10-20 | 김주용 | 반도체 소자 및 그 제조방법 |
| KR0131723B1 (ko) * | 1994-06-08 | 1998-04-14 | 김주용 | 반도체소자 및 그 제조방법 |
| US5432105A (en) * | 1994-09-19 | 1995-07-11 | United Microelectronics Corporation | Method for fabricating self-aligned polysilicon contacts on FET source/drain areas |
| US6445043B1 (en) * | 1994-11-30 | 2002-09-03 | Agere Systems | Isolated regions in an integrated circuit |
| JPH08172100A (ja) * | 1994-12-16 | 1996-07-02 | Mitsubishi Electric Corp | 半導体装置 |
| US5571733A (en) * | 1995-05-12 | 1996-11-05 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry |
| KR0155536B1 (ko) * | 1995-06-24 | 1998-10-15 | 양승택 | BiCMOS 소자의 제조방법 |
| US5627097A (en) * | 1995-07-03 | 1997-05-06 | Motorola, Inc. | Method for making CMOS device having reduced parasitic capacitance |
| US5637525A (en) * | 1995-10-20 | 1997-06-10 | Micron Technology, Inc. | Method of forming a CMOS circuitry |
| US5718800A (en) * | 1995-11-08 | 1998-02-17 | Micron Technology, Inc. | Self-aligned N+/P+ doped polysilicon plugged contacts to N+/P+ doped polysilicon gates and to N+/P+ doped source/drain regions |
| US5731619A (en) * | 1996-05-22 | 1998-03-24 | International Business Machines Corporation | CMOS structure with FETS having isolated wells with merged depletions and methods of making same |
| FR2756104B1 (fr) * | 1996-11-19 | 1999-01-29 | Sgs Thomson Microelectronics | Fabrication de circuits integres bipolaires/cmos |
| FR2756103B1 (fr) * | 1996-11-19 | 1999-05-14 | Sgs Thomson Microelectronics | Fabrication de circuits integres bipolaires/cmos et d'un condensateur |
| FR2756100B1 (fr) | 1996-11-19 | 1999-02-12 | Sgs Thomson Microelectronics | Transistor bipolaire a emetteur inhomogene dans un circuit integre bicmos |
| FR2756101B1 (fr) * | 1996-11-19 | 1999-02-12 | Sgs Thomson Microelectronics | Procede de fabrication d'un transistor npn dans une technologie bicmos |
| US5874328A (en) * | 1997-06-30 | 1999-02-23 | Advanced Micro Devices, Inc. | Reverse CMOS method for dual isolation semiconductor device |
| US5937287A (en) | 1997-07-22 | 1999-08-10 | Micron Technology, Inc. | Fabrication of semiconductor structures by ion implantation |
| US6177339B1 (en) * | 1998-08-27 | 2001-01-23 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
| US6395623B1 (en) * | 1998-08-27 | 2002-05-28 | Micron Technology, Inc. | Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions |
| US6331481B1 (en) | 1999-01-04 | 2001-12-18 | International Business Machines Corporation | Damascene etchback for low ε dielectric |
| US6399993B1 (en) | 1999-07-07 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2001085442A (ja) * | 1999-09-09 | 2001-03-30 | Mitsubishi Electric Corp | トランジスタを備えた半導体装置 |
| CN1252809C (zh) * | 1999-09-17 | 2006-04-19 | 因芬尼昂技术股份公司 | 在浅槽中形成深槽以隔离半导体器件的自对准方法 |
| CN1148788C (zh) * | 1999-12-08 | 2004-05-05 | 三星电子株式会社 | 半导体器件中的自对准接触结构及其形成方法 |
| JP2002237575A (ja) * | 2001-02-08 | 2002-08-23 | Sharp Corp | 半導体装置及びその製造方法 |
| SE0103036D0 (sv) * | 2001-05-04 | 2001-09-13 | Ericsson Telefon Ab L M | Semiconductor process and integrated circuit |
| US6492238B1 (en) | 2001-06-22 | 2002-12-10 | International Business Machines Corporation | Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit |
| US6566208B2 (en) * | 2001-07-25 | 2003-05-20 | Chartered Semiconductor Manufacturing Ltd. | Method to form elevated source/drain using poly spacer |
| US6927476B2 (en) | 2001-09-25 | 2005-08-09 | Internal Business Machines Corporation | Bipolar device having shallow junction raised extrinsic base and method for making the same |
| JP4531343B2 (ja) * | 2003-03-26 | 2010-08-25 | 株式会社半導体エネルギー研究所 | 駆動回路 |
| US6809024B1 (en) | 2003-05-09 | 2004-10-26 | International Business Machines Corporation | Method to fabricate high-performance NPN transistors in a BiCMOS process |
| US6777302B1 (en) * | 2003-06-04 | 2004-08-17 | International Business Machines Corporation | Nitride pedestal for raised extrinsic base HBT process |
| US6936522B2 (en) * | 2003-06-26 | 2005-08-30 | International Business Machines Corporation | Selective silicon-on-insulator isolation structure and method |
| US20050179111A1 (en) * | 2004-02-12 | 2005-08-18 | Iwen Chao | Semiconductor device with low resistive path barrier |
| KR101118652B1 (ko) * | 2004-12-17 | 2012-03-07 | 삼성전자주식회사 | 씨모스 공정과 통합될 수 있는 높은 이득을 갖는 바이폴라접합 트랜지스터 및 그 형성 방법 |
| US7648869B2 (en) * | 2006-01-12 | 2010-01-19 | International Business Machines Corporation | Method of fabricating semiconductor structures for latch-up suppression |
| US20070158779A1 (en) * | 2006-01-12 | 2007-07-12 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a buried damage layer |
| US7491618B2 (en) * | 2006-01-26 | 2009-02-17 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
| US7276768B2 (en) * | 2006-01-26 | 2007-10-02 | International Business Machines Corporation | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures |
| US20070194403A1 (en) * | 2006-02-23 | 2007-08-23 | International Business Machines Corporation | Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods |
| US7818702B2 (en) * | 2007-02-28 | 2010-10-19 | International Business Machines Corporation | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates |
| US7754513B2 (en) * | 2007-02-28 | 2010-07-13 | International Business Machines Corporation | Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures |
| US7808055B2 (en) * | 2007-06-21 | 2010-10-05 | Gigadevice Semiconductor Inc. | Methods and apparatus for semiconductor memory devices manufacturable using bulk CMOS process manufacturing |
| US7812367B2 (en) * | 2008-10-15 | 2010-10-12 | Semiconductor Components Industries, Llc | Two terminal low capacitance multi-channel ESD device |
| US8039326B2 (en) * | 2009-08-20 | 2011-10-18 | Globalfoundries Inc. | Methods for fabricating bulk FinFET devices having deep trench isolation |
| US8581347B2 (en) * | 2010-07-22 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming bipolar transistor through fast EPI-growth on polysilicon |
| US9401410B2 (en) * | 2014-11-26 | 2016-07-26 | Texas Instruments Incorporated | Poly sandwich for deep trench fill |
| US20160372360A1 (en) * | 2015-06-17 | 2016-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with junction leakage reduction |
| CN114695113A (zh) * | 2020-12-28 | 2022-07-01 | 芯恩（青岛）集成电路有限公司 | 一种BiCMOS器件及其中的异质结双极晶体管制造方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4252579A (en) * | 1979-05-07 | 1981-02-24 | International Business Machines Corporation | Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition |
| US4608589A (en) * | 1980-07-08 | 1986-08-26 | International Business Machines Corporation | Self-aligned metal structure for integrated circuits |
| CA1186808A (en) * | 1981-11-06 | 1985-05-07 | Sidney I. Soclof | Method of fabrication of dielectrically isolated cmos device with an isolated slot |
| JPS59124141A (ja) * | 1982-12-28 | 1984-07-18 | Toshiba Corp | 半導体装置の製造方法 |
| JPS60128656A (ja) * | 1983-12-16 | 1985-07-09 | Hitachi Ltd | 半導体装置 |
| US4593459A (en) * | 1984-12-28 | 1986-06-10 | Gte Laboratories Incorporated | Monolithic integrated circuit structure and method of fabrication |
| US4808548A (en) * | 1985-09-18 | 1989-02-28 | Advanced Micro Devices, Inc. | Method of making bipolar and MOS devices on same integrated circuit substrate |
| US4686763A (en) * | 1985-10-02 | 1987-08-18 | Advanced Micro Devices, Inc. | Method of making a planar polysilicon bipolar device |
| US4755476A (en) * | 1985-12-17 | 1988-07-05 | Siemens Aktiengesellschaft | Process for the production of self-adjusted bipolar transistor structures having a reduced extrinsic base resistance |
| IT1189976B (it) * | 1986-02-21 | 1988-02-10 | Sgs Microelettronica Spa | Processo per la fabbricazione di transistori ad effetto di campo a "gate" isolato con giunzioni a profondita' nulla mediante planarizzazione |
| JP2537936B2 (ja) * | 1986-04-23 | 1996-09-25 | エイ・ティ・アンド・ティ・コーポレーション | 半導体デバイスの製作プロセス |
| JPH0628266B2 (ja) * | 1986-07-09 | 1994-04-13 | 株式会社日立製作所 | 半導体装置の製造方法 |
| JP2581548B2 (ja) * | 1986-10-13 | 1997-02-12 | 株式会社日立製作所 | 半導体装置の製造方法 |
| US4745087A (en) * | 1987-01-13 | 1988-05-17 | Advanced Micro Devices, Inc. | Method of making fully self-aligned bipolar transistor involving a polysilicon collector contact formed in a slot with an oxide sidewall |
| JP2633559B2 (ja) * | 1987-03-31 | 1997-07-23 | 株式会社東芝 | バイポーラ―ｃｍｏｓ半導体装置の製造方法 |
| US4774204A (en) * | 1987-06-02 | 1988-09-27 | Texas Instruments Incorporated | Method for forming self-aligned emitters and bases and source/drains in an integrated circuit |
| US4800171A (en) * | 1987-10-02 | 1989-01-24 | Advanced Micro Devices, Inc. | Method for making bipolar and CMOS integrated circuit structures |
-
1988
- 1988-10-24 US US07/261,952 patent/US5015594A/en not_active Expired - Lifetime
-
1989
- 1989-06-12 CA CA000602547A patent/CA1300764C/en not_active Expired - Lifetime
- 1989-09-26 EP EP89480155A patent/EP0366587B1/de not_active Expired - Lifetime
- 1989-09-26 DE DE68922817T patent/DE68922817T2/de not_active Expired - Fee Related
- 1989-10-19 JP JP1270502A patent/JPH07105457B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE68922817T2 (de) | 1995-11-30 |
| EP0366587B1 (de) | 1995-05-24 |
| CA1300764C (en) | 1992-05-12 |
| JPH02164059A (ja) | 1990-06-25 |
| US5015594A (en) | 1991-05-14 |
| JPH07105457B2 (ja) | 1995-11-13 |
| EP0366587A2 (de) | 1990-05-02 |
| EP0366587A3 (de) | 1991-04-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |