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DE3580330D1 - Dynamisches ram in mos-technologie und verfahren zu seiner herstellung. - Google Patents

Dynamisches ram in mos-technologie und verfahren zu seiner herstellung.

Info

Publication number
DE3580330D1
DE3580330D1 DE8585302356T DE3580330T DE3580330D1 DE 3580330 D1 DE3580330 D1 DE 3580330D1 DE 8585302356 T DE8585302356 T DE 8585302356T DE 3580330 T DE3580330 T DE 3580330T DE 3580330 D1 DE3580330 D1 DE 3580330D1
Authority
DE
Germany
Prior art keywords
production
dynamic ram
mos technology
mos
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585302356T
Other languages
English (en)
Inventor
Mitsugi C O Patent Divis Ogura
Masaki C O Patent Div Momodomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3580330D1 publication Critical patent/DE3580330D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H10D1/665—Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/911—Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/92—Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE8585302356T 1984-09-11 1985-04-03 Dynamisches ram in mos-technologie und verfahren zu seiner herstellung. Expired - Lifetime DE3580330D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59190002A JPH0793365B2 (ja) 1984-09-11 1984-09-11 半導体記憶装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE3580330D1 true DE3580330D1 (de) 1990-12-06

Family

ID=16250744

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585302356T Expired - Lifetime DE3580330D1 (de) 1984-09-11 1985-04-03 Dynamisches ram in mos-technologie und verfahren zu seiner herstellung.

Country Status (4)

Country Link
US (1) US4630088A (de)
EP (1) EP0175433B1 (de)
JP (1) JPH0793365B2 (de)
DE (1) DE3580330D1 (de)

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US5102817A (en) * 1985-03-21 1992-04-07 Texas Instruments Incorporated Vertical DRAM cell and method
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US5124764A (en) * 1986-10-21 1992-06-23 Texas Instruments Incorporated Symmetric vertical MOS transistor with improved high voltage operation
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JPH01125858A (ja) * 1987-11-10 1989-05-18 Fujitsu Ltd 半導体装置およびその製造方法
JP2606857B2 (ja) * 1987-12-10 1997-05-07 株式会社日立製作所 半導体記憶装置の製造方法
JP2655859B2 (ja) * 1988-02-03 1997-09-24 株式会社日立製作所 半導体記憶装置
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US4958206A (en) * 1988-06-28 1990-09-18 Texas Instruments Incorporated Diffused bit line trench capacitor dram cell
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US5136534A (en) * 1989-06-30 1992-08-04 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell
US5192704A (en) * 1989-06-30 1993-03-09 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell
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JPH0775247B2 (ja) * 1990-05-28 1995-08-09 株式会社東芝 半導体記憶装置
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DE4447730B4 (de) * 1993-03-15 2006-05-18 Kabushiki Kaisha Toshiba, Kawasaki Halbleiteranordnung mit Grabentypelementtrennbereich und Transistorstruktur
JPH06268173A (ja) * 1993-03-15 1994-09-22 Toshiba Corp 半導体記憶装置
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JP3745392B2 (ja) 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
DE19519160C1 (de) * 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19519159C2 (de) * 1995-05-24 1998-07-09 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
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US6389582B1 (en) * 1995-12-21 2002-05-14 John Valainis Thermal driven placement
US5929476A (en) 1996-06-21 1999-07-27 Prall; Kirk Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors
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US6337497B1 (en) * 1997-05-16 2002-01-08 International Business Machines Corporation Common source transistor capacitor stack
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EP0899790A3 (de) * 1997-08-27 2006-02-08 Infineon Technologies AG DRAM-Zellanordnung und Verfahren zu deren Herstellung
US6528837B2 (en) * 1997-10-06 2003-03-04 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
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EP0945901A1 (de) 1998-03-23 1999-09-29 Siemens Aktiengesellschaft DRAM-Zellenanordnung mit vertikalen Transistoren und Verfahren zu deren Herstellung
DE19813169A1 (de) 1998-03-25 1999-10-07 Siemens Ag Halbleiterspeicher mit streifenförmiger Zellplatte
US5949700A (en) * 1998-05-26 1999-09-07 International Business Machines Corporation Five square vertical dynamic random access memory cell
US6225158B1 (en) 1998-05-28 2001-05-01 International Business Machines Corporation Trench storage dynamic random access memory cell with vertical transfer device
US6107133A (en) * 1998-05-28 2000-08-22 International Business Machines Corporation Method for making a five square vertical DRAM cell
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EP1116270A1 (de) 1998-09-25 2001-07-18 Infineon Technologies AG Integrierte schaltungsanordnung mit vertikaltransistoren und verfahren zu deren herstellung
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JP4246400B2 (ja) 1999-05-13 2009-04-02 株式会社日立製作所 半導体記憶装置
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JP4898226B2 (ja) * 2006-01-10 2012-03-14 セイコーインスツル株式会社 縦形ｍｏｓトランジスタの製造方法
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US9443844B2 (en) * 2011-05-10 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Gain cell semiconductor memory device and driving method thereof
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JP5779739B1 (ja) * 2014-02-18 2015-09-16 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
US9425788B1 (en) 2015-03-18 2016-08-23 Infineon Technologies Austria Ag Current sensors and methods of improving accuracy thereof
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CN112908994B (zh) * 2021-01-28 2023-05-26 长鑫存储技术有限公司 半导体结构
JP7454683B2 (ja) 2021-01-28 2024-03-22 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体構造

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US4491936A (en) * 1982-02-08 1985-01-01 Mostek Corporation Dynamic random access memory cell with increased signal margin

Also Published As

Publication number Publication date
JPH0793365B2 (ja) 1995-10-09
EP0175433B1 (de) 1990-10-31
JPS6167953A (ja) 1986-04-08
US4630088A (en) 1986-12-16
EP0175433A2 (de) 1986-03-26
EP0175433A3 (en) 1986-12-30

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