DE3216712A1 - Electronic counter in BCD 8421 code - Google Patents

Abstract

The subject matter of the invention is a special electronic BCD 8421 counter which also consists of decades and is virtually of no significance because four half adders each are additionally required per decade in comparison with other BCD 8421 counters. Since this counter can also be constructed as down counter and as up/down counter, it represents in any case an interesting further solution of a BCD 8421 counter. In the case of the down counter, it is not four half adders but four half subtractors which are required for each decade. In the case of the up/down counter, four switchable half adder/substractors are required per decade, which are switched by the change of potential on the control lines h and k. Figure 1 attached shows one decade of the type A up/down counter. <IMAGE>

Description

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The invention relates to an electronic counter in the. BCD-34-21 code, the decades of which consist of 4 double flip flops and M half adders each. To display the four-digit BCD numbers as deciraal digits, a decoding S.; HalGu :: ^ is also required for each De .-: ad, as is the case with all Β03-β ^ 21 counters. According to the same basic principle, hu; a backward counter possible, as well as a forward / backward counter. With the RüciCw-ircs-counter.-Coaraen per decade M- half-subtractor for use and with the Vcrwärtsö-Rüc.-cvvärus-Zär-ler per De.-cade M- half-adder-subtractor, which from Adjici to subtraction and uragekehrc . are not switchable.

The electronic forward / forward counter type A, bz-.v. a De.-caie of this counter is shown in FIG. The electronic forward counter type 3, or a decade of this counter is shown in Figure 2. The electronic counter type A, or a decade of this counter is shown in Figure 3 l-.r site. The electronic VorV / AERTS-Ru ^ Kwarus counter Type a, or a decade counter is iieses dargesceilt in FIG M-. in figure 5 in component symbols there is shown a half adder and in Figure 6, a half subtractor also in 3ai partial symbols. In FIG. 7 a single-switchable half-adder-subtractor is shown in component syaboles and in FIG. 5 a decade of the forward-backward counter type 3 is shown.

A decade of the up counter (Figure 1) besuehfc from ^ - take flip flopps (master flip flopps) 1 to M- uni M- storage flip flopps (slave flip flopps) 11 to ΛΜ- uni M- half-j Aidierer 21 to 2.M-. Other parts of this De-cade! from the flip-flop singangs statements $ 1 to 3 - ^ - · αη1 * - '\ bi MM- and the negation circuit M-5 and the AND circuits ^ c \ ιϊ M-7 and the decade-. -transfer-pre-control-and-circuit M-1 and the De.iaden-transfer-control-and-circuit 49. Part 50 is a further negating circuit. The Flipp-Flopp- ^ ingangs-;

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Circuits 3 '' to 3 ^ consist of a ! ', E ^ ier-ll : n: il cu:.; ·; ui.i two AND circuits. The outputs A to D (display -Aus g'-length A to D ") are with the associated numerical values (3, ^ -, 2, 1) ge Ktirui :: ei.; R _; - e t. The Z-inlinpuiu -rJmu-ynfs has ii · ';3e.:eichj.ui.··; Z and the DeKadeii-'JbfcrtraK-AuJgunK the 3ezeichr.u: .g J. The Hu ^ ksteli-Leitu .'- that: the Bezeicimun «.- 3 and d ^ ren 3e .-: aden -.-. Czv; inclination the designation t. As Halc-Adiierer 21 to 2 - K ~ -m ~ ei: normal half-Adiierer or 5Leziul-H- iiu- / vddierer according to Figure 3 with the following table of values for use:

a _b C. d L. L. L. 'L H L. U L. L. K ± j H ■ K L. A.A.

jjie "A'ir.-cuniraweise de? Vorw-irts-Z-ihi-ers Type A, consisting of De- <ad-jn r.ac.i figure Ί, results as follows: Leg first Z.-ihli. iipuls a: a fii ^ gang Z rip the flip-flopps 1 ui.i 11 one after the other into their left position (H-Potential ac lm.-cs-sided output shown); so the output A has H-Fotentiai. Then, in the second number pulse, the flip-flopps 1 ui-d ' ¹ I flip one after the other into their right position and the füpp flopps 2 and 12 one after the other into their Lm.-cs position, so that the output B has Η-potential Third counting pulse then flip-flopps 1 and 1 I flip one after the other into their Lin.-cs position; thus outputs A and B have Η-potential. At the fourth counting pulse then flip-^ lops 1 and 11 flip one after the other into their Right position, also the flip-flopps 2 and ¹ ^; in addition, the flip-flopps 3 ^ - * i 13 flip one after the other into their Lin.-cs position; so the output C has K potential. With the fifth count then flip the flip ficpps "and 1'i one after the other in their left position; thus the outputs A and C have H potential. At the sixth count then the flip-flopps 1 and 11 tilt one after the other into their right-Ctellu-.Λ · u: .i the flip-fiopps 2 uni 12 na ζ one after the other in ir.rj LinKS-otel-unc; with it the Auo ^ an ^ e 3 uni Z H-Pctentι xl. Ξα im sieDt ^ n Zi :: limpul3 κι or en d ^ n :. .lie flip: -Fl. ::: p ^ ^; .i: .ü "'E'ichiir.'ind ·: · in her ^ i Ll: .kj — ät'? iiu ;. _; "; iamit h ^ oer: ii-; .-! ^ --- i:. ^

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A to O Η potential. At the eighth counting pulse, they then tilt Flip-flopps 1 and 11, 2 and 12, 3 and 13 in their right position and flip-flops 4 and 14 in their left position; so only the output D has H-Fotential. At the new The counting pulse then flips the flip-flopps 1 and 11 again one after the other in their left position; so the outputs A and D have Η-potential. ' So that the AND circuit 48 has on her Output Η-potential and is therefore the decade carry forward and has the negating circuit 50 at its output

L potential. The tenth counting impulse starts with the and ^; Circuit 49 a carry-over pulse to the next decade from ur.cl · the flip-flopps 1 and 11 turn one after the other into their right-hand position because the calf adder 21 is at both inputs. (aj and b) has Η-potential and thus the output c has L-Pctentiai:. The flip-flopps 2 and 12 do not rip here for this reason. in their left 3 position because the Una circuit'46 with L-rocdr. tial pre-controlled .is. The FÜpp flopps $ u: .d 15 therefore do not tilt in their Lmxssteiligung, - because the H ^: iib adder 23 has L-potential at both inputs. The flip-flopps 4 and 14 therefore tip in the right position because the AND circuit 4? L-potential-before-approached is. This means that all outputs A to D L-Fotential and isc j the counter reading of the next decade has increased by the number 1 (LLLK) 'and the counter reading of the present dexade has fallen from ϊ j (HLLH) to 0 (LLLL) and begins with the next Count pulse, the next cycle of the current dexade.

The electronic forward counting type E, consisting of De.-raien :: ach Figure 2, has in comparison with the forward counting type A, consisting of decades according to Figure 1, the difference that not the Input circuit 32 controlled via an additional “AND circuit 46; vird, but the Haib-Adilerer! 22 via an AND Gchaltung 5 '· In sonscig -, - r relationship are] these two decades the same.

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A Decade des Rue.-Rv.irts-Zähle rs Type A '' Figure 3) sees; consists of 4 takeover flip-flopps (iaaster-flipp-f-lopps) 1 to ^ urid 4 memory flip-flopps (slave flip-flopps) 11 to 14 and 4 · half-subtractors 61 to 64. Other parts this De.-cade from the flip-flop input circuits 31 to 34 and 4-1 to 4-4 and the N --- greed circuit 45 and the AND circuits 53 and 5 ^ - and the decade transfer -Voransteuer-And-circuit 55 and the decade carry-over control circuit 56. Part 57 is a further negating circuit. The flip-flopp singangs circuits 31 to 3 ^ - also consist of a Ne-5ier circuit and zv / ei AND circuits. The display outputs A to D are also marked with the corresponding 3 numbers ^- .verten (8, 4-, 2, 1). The counting pulse input also has the designation Z and the dercaden transfer output the designation ^r J. The backward direction also has the designation S and aeren decade branching also the designation t. Normal Kalo subtractors or special half subtractors according to FIG. 6 come as Haib subtractors 61 to 64; following table of values for use:

L. L. L. L. H E. H K L. H H L. H K L. L.

The decades of this down-counter are also still rait the control inputs E bi.s H provided, which also with the associated Numerical values (3, 4, 2, 1) are marked.

A decade of the fore-keeper- "ücicv ^ ir es-counter. Type A (Figure ^) also consists of 4 takeover flip flopps (iilaster flip flopps) 1 to 4 and 4 memory i'iipp flopps (slave r "lipp flopps) 11 to 14 and 4 ums Expensive Daren half-adiator-subtracter 71 to 7 ^. In other parts, this De.-cade consists of the flip-flop input circuits 31 to 3 ^ and 41 to ⁱ ~ ^ and the negating circuit 45 and the and- Circuits 47, y \ 53 and 5 ^ - U- ^ d of the De.-caden-Transfer-Vorans expensive- "Jhä se attitude (yorw.-irts-Z-ijilrich.tung) and the DeiC-iden-Ubertrair-Voran -

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Steuer-UndschaltunK 55 (backward payment direction) and the Uegier circuits 50 and 57 and the De ^ aden-transfer-Schiilt !. 76, consisting of the AND circuits 77 u :: d 73 and the Ode circuit 79 and the AND circuit 30. The display outputs gu: .- e A to D are also with the associated numerical values (3, a-, ~ _t 1). The number pulse input also has the designation Z and the decade transfer output the designation U. The reset line also has the designation S and the decade branch also the designation t. Special half-adder-out are available as convertible j half-adder-subtractors; Tractor according to Figure 7 for use. The setting for counting up is done by applying K potential ar. i. Control line V, with the control line R having L potential via a Ne = ie: circuit. The setting to RüctC.vartslen is done by applying L potential to the 3 control line V, whereby iie control line R has Η potential via the already ez-trAr ^ z negating circuit.

In -iigur β is a decade of the forward-backward counter
Type B shown. In this electronic circuits are voters and \ cr two of the line arranged (53 '? -I ^ -d ό] Instead of the AND circuit 5' ^1-i ί- the carry line i - \\ here is to say in the Line cr the second and-ochaltur 53 is arranged, which is also driven by the line ρ wi

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Claims (1)

Claims Electronic up counter in BC D-84-21 code, thereby marked that his De. <aden from 4 double flip flopps (Master-slave flip-flopps or simplified I / Iaster-slave flip-flopps) and 4-half adders (21 to 24-). 2) Electronic backwards counter in BCD-e4-21 code, thereby marked that. his decades of 4 double flip flops (Master-slave flip-flopps or simplified iiaster-slave flip-flopps) and 4-half subtractors (61 to 64 ·). 3) Electronic up / down counter in the 3CD-5 ^ 21-Iode, characterized in that its decades of 4-Dopr.el flip-flopps (.-. laster-slave flip-flopps or simplified Master-Slave-Fiipp-Flopps) and 4-Half-Adders-Subcractors (71 to 74-) exist. 4-) Electronic forward counter according to claim 1, characterized marked that it is for the nine-to-zero state change an additional pre-control, which a reset control of the flip-flop 4- bewir.-cr ur.d which- a blocking of the flip-fl ^ pps 2 thereby causes-c wir.-ct that an AND circuit (46 ") is arranged in line e is, which atia zehi- ^ on counting pulse is not preceded is. (Up counter type A). 5) ^ electronic prewarcs counter according to claim 1, characterized by: that it has an additional pre-key control for the nine-to-zero addition, which includes a reset triggering of the flip -Flopps 4. cause <- \ ir.d which causes a block of flip-flop 2 by the fact that an AND circuit (5 "O ax. ^ Is arranged in the lead f, compared with the tenth count impulse mchc precedes: sc . (Vorwärcs-wihler Type 3). BADORIGINAL _copY 6 "! ELeictrcnischer RückwLr es counter .isoh. Claim 2, since lurch ge. <Eniizei3hi.ee, απ.ϊ it has an additional: - Yc r control for the zero-to-ITeuii state change, which advertises a Bi-jc-cierui-g ier ^£ iipp-r iopps 2 urld 3 on the first count. ? ^v : Electronic Vcrv / -irt: s-Ruc _! c.vHrr; sZ - ihler xiach claim ρ thereby geiceiinzeichi.ee that it has for the Keun-auf-NuIl-Zuseaiids change an additional pre-control according to claim 5 and that it has for the Kull-auf- Neur. Zuseands change corresponds to a Zusaes-Yor approach. end claim 6 has. 3) Electronic Vcrwfires-Z'ihler according to "claim 1, dadur> SRN terized d'aa it in sonatiger // else is formed 9 ") Electronic backward-Z ^ here to ... Alis or uch 2, thereby indicates that he is educating himself in a different way 10) Electronic Vorwar-sis'-HüciCA '.- urts-ziiler according to claims. 5, Identified by the fact that he was trained in other things durcU l — rUlaf-u ^^ sou * BATH