DE3019082A1 - Electronic binary adder and subtractor circuit - has decimal display and has five flip=flops per decade, numbers 0 to 9 being represented by 10 to 19 - Google Patents

Abstract

The electronic binary adder and subtractor circuit has two or more decade stages, each consisting of five flip-flops, i.e each decade can store zero to 31. Only the decade 10 to 19 is in fact used and this is decoded to display 0 to 9. Following addition, each stage is reset when it exceeds 9 by subtracting 10 and, following subtraction, 10 is added when the total is equal to or less than zero. The reset line, when active, resets alternate flip-flops (11,12), resulting in binary 01010. Pulses entering (at E1,E2 etc) are steered by diodes (13,14,19) to the destined flip-flops.

Description

Electronic adding and subtracting circuit

in the 8421 code with decimal display The invention relates to a electronic adding and subtracting circuit in 8421 code with decimal display. This adding and subtracting circuit also consists of decades with the numerical value ratio 1 to 10. According to the invention, each decade consists of 5 flip-flopps, which means that each decade Can store the numbers 0 to 31. In this adding and subtracting circuit the memory area 10 to 19 is thus used according to the invention and by means of a corresponding decoding circuit, the decimal digits 0 to 9 are displayed. Instead of the number 10, the number 0 is displayed and instead of the number 11, the Digit 1. To enter the decimal digits in dual numbers, a Decimal-to-dual converter required to allow dual-coded decimal digits to be entered get, e.g. 9 = HLSH. A decade is reset after adding Exceeding the decade number 9 by subtracting the number 10; with subtraction the reset takes place one decade after falling below the decade number 0 by adding the number 10. The carry-over pulse required for the next higher one Decade, which causes +1 with addition and -1 with subtraction, is taken from the associated Decoder circuit supplied. Each decade therefore has a decoding circuit according to Figure 1. The decoder circuit of the last decade has no reset circuit, because this decade is only reset to zero together with the other decades. So every decade actually has the number zero for the decade display digit 10 saved.

This adding and subtracting circuit is made with normal transistors shown. If field effect transistors are more suitable, they are used.

A decoding circuit for a dexade is shown in FIG and the first decade in FIG. 2. FIG. 3 shows the additional switching circuit for the first and the second decade and Figure 4 shows a detail with differently designed Impulse passing on. FIG. 5 shows the different detail from FIG. 2; at this Special version, the decades have an additional circuit that allows an input which causes impulses with a sufficient time interval. With this additional circuit there are also two additional inputs for resetting by +10 or -10. In Figure 6, the same different detail is shown as a simpler design: because this simpler version may also be good enough.

The first decade of this adding and subtracting circuit shown in FIG. 2 consists of 5 flip-flops 1 to 5, of which the last (fifth) flip-flop has no negating circuit because it does not have to drive a toggle pulse line transistor. The operating voltage supply lines have the designations a and the zero line is labeled c.

The tilting impulse line has the designation d and consists of the sections e. The control line has the designation f and the reset line for the reset the entire circuit consisting of n decades is designated h. With this provision the decades are reset to the memory value BEXEL and not to BLBLL, with which every decade shows the digit zero. The flip-flopp 1 consists of the transistors 11 and 12 and the diodes 13 and 14 and the resistors 15 and 16. The associated Toggle pulse line transistor has the number 17 and the input transistor the Number 18. The associated diode has the number 19. The associated negative circuit consists of transistors 20 to 22; the associated resistor has the number 23. Part 24 is a resistor with which the relevant piece of the tilting impulse line is set to the rest potential zero. If these resistors 24 are not required these are omitted. Part 25 is the reset capacitor, which is used in the Flip-flopps 1, 3 and 5 are arranged so that they are at H potential on the right Output to be reset; Flipp-Flopp 2 and 4 are reset when the total is reset at the count output (left output) brought to H potential. The Lahl exits the flip-flopps 1 to 5 have the designation A 1 to A 5 and the inputs of the Flipp-Flopps 1 to 4 are labeled E 1 to E 4. The secondary input of Flipp-Flopp 1 has the designation E 1 b. The side input of Flipp-Flopp 2 has the name E 2 b and the secondary input of flip-flop 4 is labeled E 4 b. E 1 b is the Connection point for the carry pulse, which does not exist in the first decade is.

E 2 b is the connection point for resetting to the dual number HL and E 4 b the connection point for resetting by the binary number HLLL. As already mentioned, a decade is reset when adding by subtracting the Dual number HLHL and, in the case of subtraction, by adding the dual number HLHL The changeover additional circuit is shown twice in Figure 3 (for 2 decades). Section i is part of the first Decade and the section k to the second decade. The operating voltage supply line has also the designation a and the zero line the designation c. For every decade Reversal therefore 3 transistors 31, 32 and 33 are required and 2 diodes 34 and 35.

The setting for addition is made by applying L potential to the connection point m and the setting for subtraction by applying H potential to the connection point m.

In the case of addition, the connection point m is at L potential and the connection point p at H potential and output n, to which line f is connected, has L potential. With addition reset, p changes from H potential to L potential and the output n has H potential.

In the case of subtraction, the connection point m is at H potential and connection point p is also at H potential and has output n to which line f is connected is, H potential. When subtraction is reset, p also changes from H potential to L potential and the output n has L potential.

When adding, the line f is at L potential and is therefore the transistor 17 is conductive for all flip-flopps that are connected to their counting output (left Output) have H potential.

When resetting the decade due to exceeding the upper limit (+19) the line f is placed on H-potential and thus comes with the following automatic entry of the binary numbers LLHL and HLLL not an addition, but an Subtraction comes about. The carry-over pulse to flip-flop 1 of the next higher dexade is not subtracted here because its line f is not switched to H potential is.

When subtracting lies. the line f at H potential and is thus the transistor 17 is conductive for all flip-flopps that are connected to their counting output (left Output) have L potential. When setting the decade as a result of falling short the lower limit (+10), the line f is placed on L potential and thus comes with the subsequent automatic entry of the binary numbers LLHL and HLLL none Subtraction, but rather an hddition. The carry-over impulse to the flip-flop 1 of the next higher decade is not added because its line f is not is switched to L potential.

The same pulses are used for adding and subtracting because in both cases the L-H edge of positive pulses to tip the flip-flopps is used. If the circuit is designed accordingly, the H-L flank can also be of negative pulses can be used to flip the flip-flopps.

If the. first decade has the display value 6 and the memory value 16 and the flip-flop chain of this decade at its counting outputs (left outputs) thus has the potential series HLBLL and the number 8 (HLLL) is added to it, a pulse is entered at input E 4 of the first decade. The Flipp-Flopp-4 tips over here because it is controlled directly. Flip-flop 1 to 3 of this decade don't tip over because. the diode 19 of Flipp-Flbpp 3 to the right no positive Impulse lets through. The flip-flop 5 does not tip over because of the counting output of flip-flopp 4 has L potential and thus transistor 17 of flip-flop 4 is not conductive. Thus, this decade points to the counting outputs of its flip-flopps after this addition, the potential series HELLL = 24. So this decade has the Memory value 19 is exceeded and is determined by the OR circuit 40 and the non-circuit 41 the resetting of the first decade and the carryover triggered. Here is first of output B 1, the terminal p is set to L potential, whereby the output n and thus the line f has H potential and thus this decade has been switched to subtraction is. The output B 2 causes its L-H potential change via a corresponding Conducting a toggle impulse with the first flip-flop of the next higher decade, # däs this has the secondary input E 1 b. From output B 3 causes its L-H potential change A tilting pulse at the secondary input E 2 -b via a corresponding line first decade and output B 4 a somewhat delayed one in the same way Tilting impulse at the secondary input E 4 b of the first decade. The automatic Subtraction of the dual numbers LLHL and HLLL and the automatic addition of the number 1 at the next higher decade and the resetting of the decade is thus ended. The first decade has the storage value 14 and # the display value 4 and the second Decade the memory value 11 and the display value 1.

(6. + | 8 = 4 + 10 = 1.4).

If the first decade has the display value 5 and the memory value 15 and the flip-flop chain of this decade at its counting outputs (left outputs) thus has the potential series LHHHH and subtracts the number 8 (HLLL) from it a pulse is also entered at input E 4 of the first decade. The flip flop 4 tilts because it is controlled directly. Flip flop 1 to 3 of these The decade does not flip because the diode 19 of the flip flopp 3 to the right does not allows positive impulse to pass. The Elipp-Flopp 5 does not tip over here either because the The counting output of the flip-flop 4 has H potential and thus the transistor 17 of the flip-flop Zi is not conductive (line f at H potential). Thus this decade points to the Count outputs of the flip-flopps after this subtraction the potential series LLHHH = 7 on. This decade has fallen below the storage value 10 and is from the OR circuit 40 and the non- # circuit 41 the resetting of the first decade and the transfer triggered. In this case, first of all, port p. Is connected to output B 1 placed on L potential, whereby the output n and thus the line f L potential and thus this decade has been switched to addition.

With its L-H potential change, output B 2 causes a corresponding line a toggle pulse at the first flip-flop of the next higher Decade and thus the subtraction of the number 1 via the secondary input E 1 b of the second Decade. The output B 3 causes its L-H potential change via a corresponding Line a tilting pulse at the secondary input E 2 b of the first decade and the output B 4 a somewhat delayed toggle pulse at the secondary input in the same way E 4 b of the first decade. The dual numbers were then automatically added LLHL and HLLL in the first decade and the automatic subtraction of the binary number LLLH on the second decade and thus the resetting of the first decade is completed. The first decade thus has the memory value 17 and the display value 7. Below the The prerequisite is that the second decade before this subtraction begins 12 and the display value 2, the second decade now has the memory value 11 and the display value 1.

(25 - 8 = 7 + 10 = 17).

In FIG. 5, the detail deviating from FIG. 2 is shown.

With this additional circuit a consecutive input which causes adding pulses and subtracting pulses.

The time interval between the input pulses is of course like this Made as small as possible so that the maximum computing speed is achieved. This additional circuit, which is required for each decade, is not complete # shown in detail, but with the use of AND circuit symbols. Per This additional circuit consists of an AND circuit 51 and a flip-flopp Transistor 52 and a resistor 53. The time interval is due to this comes about that the voltage is delayed because of the resistors 23 at the base of the next transistor arrives. A simplified version of this additional circuit is shown in FIG. The secondary input E 1 b is also the input for -den Carry-over pulse to and the input for the L-E-Auslöse-J? Lanke.

In the embodiment of Figure 2 with the addition of Figure 5, the Tilt pulse forwarding can also be configured in accordance with FIG.

In Figure 7 is another embodiment of the decoding circuit according to Figure 1 shown, which additionally has blocking transistors, so for example with memory number> 15 (display number 5) not also the display digits 0, 1, Lighten 2, 3 and 4 of the memory numbers 10, 11, 12, 13 and 14.

If necessary, the flip-flopps are also on the spots u arranged resistors.

Claims (1)

Claims (i) -Electronic adding circuit with i? Lipp flopps in dual code, ½ the one toggle impulse line (c) or something else that has a similar effect Eipp impulse pipeline system, - characterized in that it consists of 2 or there are more decades with a value ratio of 1 to 10. ?) Electronic adding circuit according to claim 1, characterized in that that every decade consists of 5 or more flip-flops. - (Type A) --3) -Elextronic Adding circuit according to Claim 1 and 2, characterized in that it is not used as a Adding circuit, but is designed as a subtracting circuit. (Type B). 4) Electronic @ddierschaltung according to claim 1 and 2, characterized in, that this is designed as a combined adding and subtracting circuit. (Type C). 5) Electronic circuit according to claim 1 and 2 or 1 to 3 or 1 and 2 and 4 #, characterized in that the functionality is based on that the memory values 10 to 19 are used for the digit range 0 to 9 -or-a other memory value range that does not start at zero. .6) Electronic circuits according to claim 1 to 5, characterized in that that time intervals are brought about by one or more transistor chains, where the bases of the transistors come from the emitters of the previous-to transistors can be controlled. 7) -Electronic -circuits-according-claim 6, characterized in that that in order to increase the time intervals, if necessary, resistors (60) are arranged 8) Other electronic circuits, thereby gekennzeichæ net that time intervals are caused by chains of transistors, where the bases of the transistors from the emitters of the previous transistors can be controlled. 9) other elextronic circuits according to claim 8, characterized in that that resistors (60) are arranged in order to increase the time intervals.