DE3032898A1 - Electronic adder and subtractor in 8421 code with decimal display - has combined function circuit with flip=flop stages coupled to display decoder - Google Patents

Abstract

A combined adder and subtractor circuit operates in 8421 BCD code with capability to generate a decimal display of the result. The unit has a number of full subtractor stages and two half subtractor stages. These operate together with two series each consisting of four flip-flops. The flip-flops outputs connect with a logic array performing a decoding function. The 'A' inputs are provided from decimal to binary encoder and the 'B' inputs from a decimal to binary plus six-encoder circuit.

Description

Electronic adding and subtracting mechanism

in BCD-8421 - <'# ode with decimal display subject of the invention is an electronic parallel adding and subtracting mechanism, the feedback lines and that does not have decades with one complete adder set and one each has complete subtractor set, but special circuits 30 with each 2 controllable carry outputs. This makes it possible to use these computing circuits 30 can be set to addition or subtraction by activating a carry output. The application of this principle is made possible by the fact that every decade two memory rows in which the # result numbers are stored. Even with this parallel Adding and subtracting units, the numbers are entered via a decimal-dual coding circuit each and each one decimal-dual-plus-6 coding circuit per decade, because also with this one Arithmetic unit the decade storage value 15 corresponds to the decade display value 9. That additionally required control unit is not shown. The rlaype A of this arithmetic unit is only a parallel adder because there is only one set of adders per decade is. Type B of this arithmetic value is only a parallel subtracter, because pro Decade only one set of subtractors is arranged. Also with these types A and B are Feedback lines d arranged, which is why all three arithmetic units are special arithmetic units are.

The basic decade circuit of these three arithmetic units is shown in FIG. 1 and a set of adders for one decade of the parallel adder in FIG 2. In FIG. 3 there is a set of subtractors for one decade of the parallel subtracter and in Figure 4 a set of computing circuits for a decade of parallel Adder urid subtractor. In Figure 5, the detail C is shown. In figure 6, a decimal-dual coding circuit is shown which corresponds to the A-ring lengths upstream and in Figure 7 a decimal-dual-plus - @ - coding circuit, which the B-Einangen the decades is switched.

The electronic parallel adding unit (arithmetic unit type A) exists without an additional control unit from an arbitrarily large number of decades according to Figure 1. The special design of an adding decade in its lower area is shown in FIG. The full adders V each consist of two half adders 10 (Figure 2). A half adder thus has the designation 10 in FIG. 2 and in FIG 1 the designation H, because in Figure 1 other designations are required. At further parts consists of a decade of this parallel adder from the memory rows E and F, which each consist of 4 memory flip-flopps 3 and the decoding circuit 4, which consists of 10 AND circuits 5 and four non-circuits (negative circuits) 6 consists. A decimal-dual coding circuit according to FIG. 6 is connected upstream of the A inputs and the B inputs a decimal-dual-plus-6 coding circuit according to FIG. 7.

The electronic parallel subtracter (arithmetic unit type B) exists without an additional control unit from any number of decades according to Figure 1, because this figure is shown only once and the different Details are shown in Figures 2-4. The special training of this Decade in its lower area as a subtraction decade is shown in FIG. The parts V are full subtractors, each consisting of 2 Haib subtractors 20 (Figure 3). A half subtracter is thus designated 20 in FIG. 3 and in Figure 1, the designation H. There is a decade of this parallel subtracter in other parts from the memory rows E and F, which each consist of 4 memory flip-flopps 3 and of the decoding circuit 4, which consists of 10 AND circuits 5 urld 4 non-circuits (Negating circuits) 6 consists. The A-inputs is also a decimal-dual-coding switching path 6 in front of # and the B-rings a decimal-dual-plus-6 coding circuit flat figure?.

The electronic parallel adding and subtracting unit (arithmetic unit type C) consists of an arbitrarily coarse control unit without an additional control unit Number of decades according to Figure 1.

The special training of this decade in its lower area as Adding and subtracting decades are shown in FIG. Parts V are here combined adding-subtracting circuits 30 in a double arrangement (FIG. 4). the two individually arranged circuits 30 have the designation H. An in FIG There is also a decade of this combined parallel adding and subtracting unit from the memory rows E and F, which also consist of 4 memory flip-flopps 3 each and the decoding circuit 4, which is composed of 10 AND circuits 5 and 4 non-circuits (Negating circuits) 6 consists. The A inputs is also a decimal-dual coding circuit upstream of Figure 6 and the B inputs a decimal-dual-plus-b coding circuit according to Figure 7. The control lines s and i are not shown in Figure 1 because they are not available for types A and B. The arrangement of these control lines i and s, which are arranged in the same direction as the control lines p and q, can be seen in FIG.

If, instead of the transistors 7 to 9, field effect transistors are more suitable or if only field effect transistors can be used for this purpose instead of transistors 7, 8 and 9, field effect transistors are used.

The mode of operation of the combined adding and subtracting unit (arithmetic unit Type C) with DeKaden according to FIG. 1 and detailed design according to FIG. 4 is how follows: In the case of Ad ~.

In addition, the control line is at H potential and is therefore all Circuits 30 set to addition. When adding two summands together one of these summands comes dual coded at the A inputs to the system and the others are dualplus-6 coded at the B inputs. This means that at the outputs k, 1, m and n and thus the potential series of the sum result number at the transistors 7 and is entered into the memory row E by means of an H-current pulse on control line p, which like control line q and #control lines i and s traversed all decades. This is the potential series of this total result number into the memory.

Row E is entered and follows No H-current pulse on the control line q, by means of which the potential series of this result sum into the memory series F is entered. This sum result number is on the one hand as a decimal number at the outputs of the decoding circuit 4 and on the other hand via the feedback lines d as memory value at the B inputs. As a result of the fact that there is per decimal place a decade is required, a decoding circuit 4 shows only for a specific one Decimal place the corresponding decimal digit of the result number. If to this one Result sum additional numbers (summands) are to be added, these come one after the other to the A # Ebjgingen to the system and are each time one after the other (temporally one after the other) the control lines p and q are charged with an H-current pulse and thus one subtotal after the other as a memory number over the lines d brought to the system at the B-ring lengths and thus the addition of the next Significantly simplified summands. In this way, the addition takes place unequally large summands. If to a number already stored (previous Addition result number or previous subtraction result number) n times a number (Summand) is to be added, it is also coded dual on the A-ring lines brought to the system and then the control lines p and q n-fold one after the other with fed with an H-current pulse.

If no result number has yet been saved, the multiple Addition of a number (summand) can be initiated by adding this summand once is zero-added to the number; so this summand is up to the next addition as the first result sum at the B inputs.

When subtracting, the control line i is at H potential and are so that all circuits 30 are set to subtraction.

The subtraction of a number. (Subtrahend) from another number (Minuend) takes place by the fact that the minuend is dual-plus-6-coded at the B-entrances to the system comes and the subtrahend is dual coded at the A inputs, and that the potential series the subtraction result number ddnn with an H current pulse on the control line p is entered into the memory row E and then by means of an H current pulse is entered into the memory row F on the control line q. Entering the thereby The resulting number of results in the memory rows E and F is therefore carried out on the same Way, like entering an addition ons result number. After the subtraction result number is also stored in the memory row b ~, it is immediately available at the B inputs and to the decoding circuits 4. If there are other subtrahends of different sizes This subtraction is carried out to be subtracted from this subtraction result number by dtilj these come one after the other at the A entrances to the system and there after each system of a bubtrahenden at the A inputs the control lines p and q one after the other be charged with an H-current pulse. The minuend is only as long as this at the B inputs until the first subtraction result number in the memory row E is stored. If a number (subtrahend) is subtracted n times from a minute end is to be, the Minuend is first also coded dual-plus plus-6 at the B inputs brought to the system and then by subtracting the number zero into the memory rows E and F entered. The subtraction of the number zero (LLLL) is done by that no number is attached to the A-iiien and that the Steuerleiturlgerl and q are fed one after the other with an H-current pulse. This is followed by the n-fold Subtract the subtrahend in the manner already described.

L e r s e i t e

Claims (5)

Claims @ Electronic parallel adder with mixed Input coding (decimal-dual and decimal-dual-plus-6) characterized that each De kaden adder set consists of 12 half adders (10) or 11 half adders and a reduced half adder, which instead of the half adder (10 b) is used. 2) Electronic parallel adder according to claim 1, characterized in that that its embodiment has B feedback lines (d). 3) Electronic parallel subtracter with mixed input coding (Decimal # l-dual and decimal-dual-plus 6) characterized in that each decade subtracter set consists of 12 half subtractors (20) or 11 Haib subtractors and one reduced Half-subtracter, which can be used instead of the half-subtracter (20 b). 4) Electronic parallel subtracter according to claim 3, characterized characterized in that its embodiment has B feedback lines (d). 5) Electronic parallel adder with mixed input coding (Decimal-dual and decimal-dual-plus-6) characterized d it combined Has circuits (30), which consist of a base part (w) for addition and subtraction is equal, and there are two additional parts (x and y) of which the The additional part (x) has a function as a half adder and the additional part (y) has a function Functions as a calf subtracter and in this way as a combined electronic Parallel adding and subtracting is formed. Electronic parallel adding and subtracting mechanism according to claim 5, characterized in that its embodiment has B feedback ducts (d). t) Other electronic arithmetic units, characterized in that these are designed as combined adding and subtracting units in that only combination circuits (30) that have two controllable outputs are used (r and z), of which one (r) is controlled by addition and the other (z) is driven on subtraction.