CN117012649A - Trench MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing on-resistance based on P-type epitaxy and preparation method - Google Patents

Abstract

The invention provides a trench MOSFET that reduces on-resistance based on P-type epitaxial crystals and a preparation method thereof, which belongs to the field of semiconductor technology. The method includes: using an epitaxial crystal process to form a body region above the drift region; and forming an upper layer of the body region by ion implantation. Source region; etching via holes in the body region and the source region, etching trenches in the upper layer of the drift region, and the via holes are connected to the trenches; depositing a drain electrode below the substrate, A source electrode is deposited above the source electrode region, and a gate electrode is deposited in the trench. The present invention uses the epitaxial process to replace the ion implantation and diffusion methods used in the prior art to form the body region. Since the epitaxial process can accurately control the depth of the body region, it can effectively shrink the channel length and reduce the channel resistance. , it can also make the doping ions in the channel evenly distributed, effectively reduce the on-resistance of the trench MOSFET, and improve the electrical performance of the trench MOSFET.

Description

A trench MOSFET that reduces on-resistance based on P-type epitaxial crystals and its preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to a trench MOSFET that reduces on-resistance based on P-type epitaxial crystals and a preparation method.

Background technique

The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc., and can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. Silicon carbide devices have high electron saturation rate, small forward conduction resistance, and low power loss. They are suitable for high-current and high-power applications and reduce the requirements for heat dissipation equipment. MOSFET made of silicon carbide material is a field effect transistor that can be widely used in analog circuits and digital circuits. MOSFETs can be divided into "N-type" and "P-type" MOSFETs according to the polarity of their "channels", usually also called NMOSFETs and PMOSFETs.

The majority carriers in the N-type semiconductor drift from the source to the drain through the N-type semiconductor. This N-type semiconductor forms a channel for free electrons or current, called a "channel." The resistance of the channel is controlled by the internal electric field of the PN junction between the P-type gate and the N-type channel, because the current is formed by the drift of the majority carriers in the N-type semiconductor. The main effects of channel resistance on MOSFET are: Channel resistance affects the switching characteristics of MOSFET. Channel resistance is an internal dissipation of the MOSFET when it is turned off. It reduces the available energy of the MOSFET when it is turned off, making the MOSFET more susceptible to failure when switching. Therefore, reducing the channel resistance can improve the switching characteristics of the MOSFET. Channel resistance affects power output capability. As the channel resistance increases, the power output capability also decreases. Therefore, if you want the MOSFET to exert its maximum power output capability, you should try to keep the channel resistance as low as possible. Forward conduction characteristics are also affected. As the channel resistance increases, the forward conduction saturation decreases. This means that if you want to ensure that the MOSFET has good forward conduction characteristics, the channel resistance must be made as low as possible.

Channel resistance is a key factor affecting the on-resistance of low-voltage trench MOSFET devices. The current channel formation method uses ion implantation and diffusion to form the body region. However, due to process technology limitations, the channel length cannot be effectively reduced, and the channel length The uneven distribution of doping concentration on the chip leads to an increase in on-resistance and reduces the electrical performance of trench MOSFETs.

Contents of the invention

The purpose of the present invention is to provide a trench MOSFET that reduces on-resistance based on P-type epitaxy and a preparation method. This method uses the epitaxial process to replace the ion implantation and diffusion methods used in the prior art to form the body region. The crystal process can accurately control the depth of the body region, thereby effectively shrinking the channel length, reducing the channel resistance, and evenly distributing the doped ions in the channel, effectively reducing the on-resistance of the trench MOSFET, and improving the Electrical performance of trench MOSFETs.

A method for preparing trench MOSFETs based on P-type epitaxy to reduce on-resistance, including:

The epitaxial process is used to form the body region above the drift region;

A source region is formed by ion implantation in the upper layer of the body region;

Via holes are etched in the body region and the source region, trenches are etched in the upper layer of the drift region, and the via holes are connected to the trenches;

A drain is deposited under the substrate, a source is deposited over the source region, and a gate is deposited in the trench.

Preferably, the body region formed using an epitaxial process above the drift region is specifically:

Fill the reaction chamber with the reaction gas at the preset flow rate, adjust the temperature in the reaction chamber to the preset temperature, and adjust the pressure in the reaction chamber to the preset pressure;

The reactive gas reacts on the surface of the drift zone to form a body zone film;

The body region film grows to a preset value and then stops reacting.

Preferably, stopping the reaction after the body region film grows to a preset value specifically includes: when the body region film grows to 0.1-2um, the reaction gas stops filling the reaction chamber.

Preferably, adjusting the temperature in the reaction chamber to a preset temperature specifically includes: adjusting the temperature in the reaction chamber to 950-1150°C.

Preferably, the reaction gas includes: H ₂ , N ₂ , CH ₄ , O ₂ and SiH ₄ .

Preferably, adjusting the pressure in the reaction chamber to a preset pressure specifically includes: adjusting the pressure in the reaction chamber to 101.325KPa.

Preferably, the thickness of the body region is 0.1-2um.

Preferably, the doping concentration of the body region is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 .

Preferably, before using an epitaxial process to form the body region above the drift region, the method further includes: epitaxially forming the drift region above the substrate.

A trench MOSFET based on P-type epitaxy to reduce on-resistance, including: substrate, drift region, body region, source region, source, drain and gate;

The drain electrode is deposited under the substrate;

The substrate is located below the drift region;

The drift region is located below the body region;

The body region is located below the source region;

The source is deposited above the source region;

The gate is deposited in the trench.

When manufacturing trench MOSFETs in the existing process, the trench is etched in the drift area, and then ions are implanted in the drift area to form the body region and source area, and finally electrodes are deposited to form the trench MOSFET. During the ion implantation process, the channel length cannot be determined. Effective shrinkage, and the channel length and doping concentration are unevenly distributed on the chip, resulting in a greatly increased on-resistance, thereby reducing the device performance of the trench MOSFET. In order to overcome the shortcomings of the existing technology, the present invention uses an epitaxial process Instead of the traditional ion implantation method to form the body region, the epitaxial process can accurately control the depth of the body region, effectively shrink the channel length, reduce the channel resistance, and have a better channel doping concentration distribution. The body region formed by the epitaxial process can effectively reduce the on-resistance of trench MOEFST and improve the device performance of trench MOSFET.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic diagram of the trench MOSFET preparation process method of the present invention;

Figure 2 is a schematic structural diagram of the trench MOSFET preparation process of the present invention;

Figure 3 is a schematic structural diagram of the trench MOSFET of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

When manufacturing trench MOSFETs in the existing process, the trench is etched in the drift area, and then ions are implanted in the drift area to form the body region and source area, and finally electrodes are deposited to form the trench MOSFET. During the ion implantation process, the channel length cannot be determined. Effective shrinkage, and the channel length and doping concentration are unevenly distributed on the chip, resulting in a greatly increased on-resistance, thereby reducing the device performance of the trench MOSFET. In order to overcome the shortcomings of the existing technology, the present invention uses an epitaxial process Instead of the traditional ion implantation method to form the body region, the epitaxial process can accurately control the depth of the body region, effectively shrink the channel length, reduce the channel resistance, and have a better channel doping concentration distribution. The body region formed by the epitaxial process can effectively reduce the on-resistance of trench MOEFST and improve the device performance of trench MOSFET.

Example 1

A method of preparing trench MOSFET based on P-type epitaxy to reduce on-resistance, refer to Figures 1 and 2, including:

S100, the epitaxial process is used to form the body region above the drift region;

In the epitaxial process, chemical vapor deposition is usually used for body region growth. During the body region growth process, the temperature in the reaction chamber, the concentration and gas composition of the reaction gas, the flow rate of the reaction gas, and the pressure in the reaction chamber will all affect Only by strictly controlling the rate and quality of body region generation and the above-mentioned main parameters can trench MOSFETs that meet market demand be grown.

Chemical vapor deposition is a technique used in the semiconductor industry to deposit a wide range of materials, including a wide range of insulating materials, most metallic materials, and metal alloy materials. Chemical vapor deposition is a process in which two or more gaseous raw materials are introduced into a reaction chamber, and then the reactants chemically react with each other to form a new material, which is deposited on the wafer surface. For example: the deposited silicon nitride film (Si ₃ N ₄ ) is formed by the reaction of silane and nitrogen. Chemical vapor deposition is a technology for preparing body region semiconductor crystal thin films. Its principle is to use gaseous precursor reactants to decompose certain components in the gaseous precursor through chemical reactions between atoms and molecules to form on the substrate. film. Chemical vapor deposition includes plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHV CVD), microwave plasma chemical vapor deposition (MPCVD), low pressure chemical vapor deposition (LPCVD), thermal chemical vapor deposition (TCVD), wait.

Plasma-enhanced chemical vapor deposition: Plasma-enhanced chemical vapor deposition is a method in chemical vapor deposition that excites gas to generate low-temperature plasma to enhance the chemical activity of the reacting substances, thereby performing epitaxy. This method can form solid films at lower temperatures. For example, in a reaction chamber, the matrix material is placed on the cathode, the reaction gas is introduced to a lower pressure (1~600Pa), the matrix is maintained at a certain temperature, and a glow discharge is generated in a certain way. The gas near the surface of the matrix is ionized, and the reaction gas is obtained Activation, while cathode sputtering occurs on the surface of the substrate, thereby improving surface activity. Not only common thermochemical reactions occur on the surface, but also complex plasma chemical reactions occur. The deposited film is formed under the combined action of these two chemical reactions. The main methods for stimulating glow discharge are: radio frequency excitation, DC high voltage excitation, pulse excitation and microwave excitation. The main advantages of plasma-enhanced chemical vapor deposition are low deposition temperature and little impact on the structure and physical properties of the substrate; good thickness and composition uniformity of the film; dense film structure and few pinholes; strong adhesion of the film layer; range of applications wide.

Microwave plasma chemical vapor deposition: Microwave plasma chemical vapor deposition technology is suitable for preparing high-quality hard films and crystals with large area, good uniformity, high purity and good crystalline form. Microwave plasma chemical vapor deposition is one of the effective methods to prepare large-size single crystals. This method uses electromagnetic wave energy to excite reactive gases. Because it is an electrodeless discharge, the plasma is pure. At the same time, the microwave discharge area is concentrated and does not expand. It can activate and produce various atomic groups such as atomic hydrogen. The maximum kinetic energy of the generated ions is low and will not corrode the generated crystals. By adjusting the structure of the microwave plasma chemical vapor deposition reaction chamber, a large-area and stable plasma ball can be generated in the deposition chamber, which is conducive to large-area and uniform deposition of crystals. Therefore, the microwave plasma method can prepare large-sized single The superiority of crystal films is very prominent among all preparation methods.

Ultra-high vacuum chemical vapor deposition: Ultra-high vacuum chemical vapor deposition is a thin film technology used to prepare high-quality sub-micron crystal films, nanostructured materials, and develop silicon-based high-speed high-frequency devices and nanoelectronic devices. Ultra-high vacuum chemical vapor deposition technology refers to a chemical vapor deposition process performed in an ultra-high vacuum reactor below 10 ^-6 Pa (10 ^-8 Torr). It is suitable for depositing single crystal thin films on the surface of highly chemically active substrates. Different from traditional vapor phase epitaxy, ultra-high vacuum chemical vapor deposition technology uses low pressure and low temperature growth, which can effectively reduce the solid-state diffusion of doping sources and inhibit the three-dimensional growth of epitaxial films. The ultra-high vacuum of the ultra-high vacuum chemical vapor deposition system reactor avoids oxidation of the Si substrate surface and effectively reduces the incorporation of impurities generated by the reaction gas into the growing film. Under ultra-high vacuum conditions, reactive gas molecules can be directly transferred to the substrate surface. There is no diffusion of reactive gases and complex interactions between molecules. The deposition process mainly depends on the reaction at the gas-solid interface. In traditional vapor phase epitaxy, the diffusion of vapor phase precursors to the substrate surface through the boundary layer determines the growth rate of the epitaxial film. Ultra-high vacuum causes the gas phase precursor molecules to directly impact the substrate surface, and the growth of the film is mainly controlled by chemical reactions on the surface. Therefore, the molecular flow of the gas phase precursor silane or germane on the surface of all substrates (substrates) on the support base is the same, and epitaxial growth can be achieved on multiple substrates at the same time.

Low-pressure chemical vapor deposition: a chemical vapor deposition reaction that reduces the operating pressure of the reaction gas during the deposition reaction in the reactor to below approximately 133 Pa. The pressure of low-pressure chemical vapor deposition drops below about 133Pa. Correspondingly, the free path and gas diffusion coefficient of molecules increase, which accelerates the mass transfer rate of gaseous reactants and by-products, and increases the reaction rate of forming thin films, even if they are placed parallel and vertically The distance between the substrates is reduced to 5~10mm, and the mass transmission limit can still be ignored compared with the chemical reaction rate on the substrate surface. This creates conditions for upright close-packed chip mounting and greatly increases the number of chips per batch. Thin films deposited by low-pressure chemical vapor deposition will have better step coverage, good composition and structure control, high deposition rate and output. In addition, low-pressure chemical vapor deposition does not require carrier gas, thus greatly reducing the source of particle pollution, and is widely used in the high value-added semiconductor industry for thin film deposition.

Thermochemical vapor deposition: A method of vapor growth using high temperatures to activate chemical reactions. Thermal chemical vapor deposition is divided into several categories according to its chemical reaction form: Chemical transport method: the substance that makes up the film reacts with another solid or liquid substance in the source area to generate gas. Then it is transported to the growth zone at a certain temperature, and the required materials are generated through reverse thermal reactions. The forward reaction is the thermal reaction of the transport process, and the reverse reaction is the thermal reaction of the crystal growth process. (2) Pyrolysis method: Transport certain volatile substances containing film elements to the growth area, and generate the required substances through thermal decomposition reaction. Its growth temperature is 1000-1050 degrees Celsius. (3) Synthesis reaction method: The process in which several gaseous substances react in the growth zone to generate the grown substances. The chemical transport method is generally used for the growth of bulk crystals. The decomposition reaction method is usually used for the growth of thin film materials. There are two synthesis reaction laws. Used in any situation. Thermal chemical vapor deposition is applied to semiconductor materials, such as Si, GaAs and other oxides and other materials.

In the embodiment of the present invention, different epitaxial processes need to be selected according to the actual requirements for the body region parameters. For example, when a body region with a larger area needs to be generated, the low-pressure chemical vapor deposition method can be used, and the method can be used in batches. Produce large quantities of MOSFETs with larger chip areas. When it is necessary to produce microchips, ultra-high vacuum chemical vapor deposition can be used because ultra-high vacuum chemical vapor deposition can produce high-quality sub-micron crystal films and nanostructured materials. In order to save production costs, the thermal chemical vapor deposition method can also be used, because the reaction conditions required by the chemical vapor deposition method are easier to achieve, the items required for the reaction are also easier to obtain, and the quality of the produced body area is also very good, which is suitable for large-scale applications. Industrial production of partial body area growth.

S200, ion implantation is performed on the upper layer of the body region to form the source region;

The present invention adopts ion implantation to form the source region by ion implantation in the upper layer of the body region. The source region is formed after the body region is formed. In the embodiment of the present invention, the source region is an N-type heavily doped semiconductor. The N-type semiconductor is formed by ion implanting pentavalent ions, such as nitrogen (N), into the semiconductor. ), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and enrium (Mc). + is heavily doped (high doping concentration), - is lightly doped (low doping concentration). The formation method of P-type semiconductor is to ion implant trivalent ions in the semiconductor, such as: boron, aluminum, gallium, indium, thallium. Using heavily doped N+ type semiconductor in the source region can reduce the resistivity of the semiconductor and form a good ohmic contact with the metal electrode. Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and retained in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. The "mass" selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or "slits" that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

S300, etching via holes in the body region and source region, etching trenches in the upper layer of the drift area, and connecting the via holes to the trenches;

The present invention uses a one-time etching method to etch through holes in the body region and the source region, etching trenches in the upper layer of the drift area, and the through holes are connected to the trenches. Etching is the process of selectively removing unwanted materials from the surface of silicon wafers using chemical or physical methods. It is a general term for stripping and removing materials through solutions, reactive ions or other mechanical means. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are radiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they hit the material on the surface. With the wafer vertical or tilted into the ion beam, the etching process is absolutely anisotropic. Selectivity is low as there is no difference between layers. The gases and ground material are removed by a vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched using this method, with very low wear on vertical walls due to vertical radiation.

Plasma etching is a chemical etching process that has the advantage that the wafer surface will not be damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove the entire film layer (e.g. backside cleaning after thermal oxidation). One type of reactor used for plasma etching is the downstream reactor. Thus, plasma is ignited at a high frequency of 2.45GHz through impact ionization, and the location of impact ionization is separated from the wafer.

The etch rate depends on the pressure, power of the high frequency generator, process gas, actual gas flow and wafer temperature. Anisotropy increases with increasing high-frequency power, decreasing pressure, and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes, and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed unevenly, resulting in inhomogeneity. If the distance between the electrodes is increased, the etch rate decreases because the plasma is distributed in an enlarged volume. For electrodes, carbon has proven to be the material of choice. Because fluorine and chlorine gases also attack carbon, the electrodes create a uniformly strained plasma so the edges of the wafer are affected in the same way as the center of the wafer. Selectivity and etch rate are highly dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S400, deposit a drain electrode under the substrate, deposit a source electrode above the source region, and deposit a gate electrode in the trench.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). Chemical vapor deposition refers to the method of depositing coatings on the surface of wafers through chemical methods, usually by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In embodiments of the present invention, a chemical vapor deposition method is used to deposit metal electrodes. The chemical vapor deposition process is divided into three stages: diffusion of reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form solid deposition. The substances and the gas phase by-products produced are separated from the surface of the matrix. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions. Usually, to deposit TiC or TiN, gases such as TiCl ₄ , H ₂ , and CH ₄ are introduced into a reaction chamber at 850 to 1100°C. After chemical reaction, a coating is formed on the surface of the substrate.

The gate electrode is deposited using the polysilicon deposition method. Polysilicon deposition is when silicide is stacked on the first layer of polysilicon (Poly1) to form the gate electrode and local connections, and the second layer of polysilicon (Poly2) forms the source/drain and cell connections. contact plug. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection. The fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor. Sandwiched between them is a high dielectric coefficient of dielectric. To maintain the desired capacitance value, the size of the capacitor can be reduced by using a high-k dielectric. Polycrystalline silicon deposition is a type of low-pressure chemical vapor deposition (LPCVD), by placing arsenic (AH ₃ ), phosphorus (PH ₃ ) or diborane (B ₂ H ₆ ) in a reaction chamber (i.e., a furnace tube). By directly inputting the doping gas into the silicon material gas of silane or DCS, the polysilicon doping process of on-site low-pressure chemical vapor deposition can be carried out. Polysilicon deposition is carried out under low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane with a purity of 20% to 30% after dilution with nitrogen. The deposition rate of both deposition processes is between 100-200Å/min, mainly determined by the temperature during deposition.

The epitaxial process is used to form the body region above the drift region. The details are as follows:

Fill the reaction chamber with the reaction gas at the preset flow rate, adjust the temperature in the reaction chamber to the preset temperature, and adjust the pressure to the preset pressure;

Reactants enter the reaction chamber in gaseous form and are activated within the reaction chamber. Activation methods include: heating, plasma, or a combination of heating and plasma. Therefore, it is necessary to adjust the temperature and pressure in the reaction chamber to a preset value in order to increase the reaction rate and obtain products of better quality faster.

The reactive gas reacts on the surface of the drift zone to form a body zone film;

The activated reactants react on the substrate surface (drift zone surface) to form a thin film. The reactions that occur include: oxidation, reduction, deposition and other chemical reactions.

The body region film grows to a preset value and then stops reacting.

When the film begins to grow, the reactants are continuously filled into the reaction chamber and react with the surface of the substrate to form thin sheets. The growth rate of flakes is affected by reaction conditions and reactant concentrations. The higher the reactant concentration is within a certain range, the growth rate of the flakes will be faster. When the reactant concentration exceeds the maximum value, side reactions will occur and a large amount of by-products will be generated, resulting in waste of raw materials and reduced crystal quality.

Stopping the reaction after the body region film grows to a preset value specifically includes: when the body region film grows to 0.1-2um, the reaction gas stops filling the reaction chamber.

Different types of trench MOSFETs have different body region thicknesses. The thickness of the body region is between 0.1-2um. Controlling the progress and stop of the reaction according to actual production requirements can control the thickness of the body region. In addition, during the epitaxy process, the thickness of the body region The thickness is easy to control, but during the ion implantation process, due to the diffusion effect, the thickness of the body region is often difficult to control, and the ion concentration in the body region is also easily distributed unevenly, resulting in a large on-resistance of the final trench MOSFET. Does not meet the needs of industrial production. Therefore, using the epitaxial process to replace the traditional ion implantation method to generate the body region can achieve good electrical performance improvement at a lower production cost. As a preferred embodiment, the present invention stops filling the gas and lowers the temperature to terminate the reaction when the body region film grows to 0.5um.

Adjusting the temperature in the reaction chamber to the preset temperature specifically includes: adjusting the temperature in the reaction chamber to 950-1150°C.

The reaction temperature is an important parameter in the epitaxial process and needs to be strictly controlled. In the embodiment of the present invention, the temperature in the reaction chamber is controlled at 1000°C, so that the reaction gas can react with the substrate faster and deposit crystals. It can increase the chemical activity of reactants and make reactions easier to occur.

Reactive gases include: H ₂ , N ₂ , CH ₄ , O ₂ and SiH ₄ .

The reaction materials of chemical vapor deposition reaction usually include gas, liquid, solid and other forms. Commonly used reaction materials include oxygen, chloride, hydride, organic metal, metal oxide, etc. Different reacting substances have different chemical properties and therefore play different roles in the reaction mechanism. For example, oxygen can provide oxygen atoms in the reaction and play the role of oxidation reaction; while organic metals can provide metal atoms and play the role of reduction reaction. The reactants used in chemical vapor deposition reactions must be of extremely high purity because any impurities will eventually be incorporated into the deposited film. These impurities can cause uncontrolled changes in film material properties, which can be detrimental to device performance. Using H ₂ , N ₂ , CH ₄ , O ₂ and SiH ₄ as gaseous material sources in the epitaxial process can save production costs because H ₂ , N ₂ , CH ₄ , O ₂ and SiH ₄ are relatively easy to obtain and have physical and chemical properties. It has stable properties and has mature equipment in process production, which can obtain high-quality body region components with a high yield, so that the ion concentration in the produced body region is uniform, the surface is smooth, and the structure is stable, which can greatly improve the groove. Device performance of slot MOSFETs.

Adjusting the pressure in the reaction chamber to the preset pressure specifically includes: adjusting the pressure in the reaction chamber to 101.325KPa.

In the embodiment of the present invention, the pressure in the reaction chamber is controlled at atmospheric pressure to allow the reaction to occur. In the process of depositing the body zone, a higher deposition rate and thick coating capability can be obtained without the need for ultra-high vacuum, and it can also Save production costs.

The thickness of the body area is 0.1-2um.

Different types of trench MOSFETs have different body region thicknesses. The thickness of the body region is between 0.1-2um. Controlling the progress and stop of the reaction according to actual production requirements can control the thickness of the body region. In addition, during the epitaxy process, the thickness of the body region The thickness is easy to control, but during the ion implantation process, due to the diffusion effect, the thickness of the body region is often difficult to control, and the ion concentration in the body region is also easily distributed unevenly, resulting in a large on-resistance of the final trench MOSFET. Does not meet the needs of industrial production. Therefore, using the epitaxial process to replace the traditional ion implantation method to generate the body region can achieve good electrical performance improvement at a lower production cost. As a preferred embodiment, the present invention stops filling the gas when the body region film grows to 0.5um and lowers the temperature in the reaction chamber to terminate the reaction.

The doping concentration of the body region is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 .

The doping concentration of the body region is lightly doped, and the ion concentration range is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 . As a preferred embodiment, the present invention sets the doping concentration of the body region to 1×10 ¹⁶ cm ^-3 . A body region with uniform doping concentration distribution can conduct electricity better and reduce on-resistance.

Before using the epitaxial process to form the body region above the drift region, it also includes: epitaxially forming the drift region above the substrate.

The drift region of a semiconductor device refers to the region in the semiconductor device where current is transmitted within the drift region. The drift region is one of the most important parts of semiconductor devices, which directly affects the performance and working results of the device. In semiconductor devices, the drift region is usually formed by doped materials. Doping refers to the introduction of impurity atoms into a semiconductor crystal to change its conductive properties. In the drift region, the type and concentration of dopant material determines the current transfer characteristics. The main function of the drift region is to provide a channel for current transmission. When an external voltage is applied to a semiconductor device, the charges in the drift region are moved by the electric field force. This movement creates the transmission of electrical current. The width and length of the drift region determine the speed and efficiency of current transmission.

In semiconductor devices, the design and optimization of drift regions is very important. First, the width and length of the drift region need to be reasonably selected according to the requirements of the device. If the drift region is too narrow or too short, the current transmission speed will be limited, affecting the performance of the device. If the drift region is too wide or too long, it will increase the size and power consumption of the device and reduce the efficiency of the device. Secondly, the selection of doping materials and concentration control of the drift region are also key. Different doped materials have different conductive properties and can be used to achieve different device functions. The concentration of the doping material determines the conductive properties of the drift region. Too high or too low a concentration will affect the performance of the device.

Example 2

A trench MOSFET based on P-type epitaxy to reduce on-resistance, refer to Figure 3, including: substrate, drift region, body region, source region, source, drain and gate;

The drain is deposited beneath the substrate;

The drain is the charge sink in the MOSFET. It is connected to the channel and is the entrance to the charge. When the MOSFET is in the on state, a conductive path is formed between the drain and source, and electrons flow from the source to the drain to complete the transmission of current. The voltage change of the drain has little impact on the working state of the MOSFET, and mainly plays the role of current inflow.

The substrate is located below the drift region;

The electric field distribution in the drift region plays a key role in the conduction characteristics and current control of MOSFET. When a gate voltage is applied to a MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. When the MOSFET is operating, the current between the source and drain is mainly transmitted through the drift region. The doping type and concentration of the drift region determine the conduction type (N-type or P-type) and size of the current. The structure and characteristics of the drift region directly affect the current control capability of the MOS tube. By adjusting the shape, size and doping concentration of the drift region, precise control of the current can be achieved to meet the requirements of different applications.

The drift zone is located below the body zone;

The body region is used to form the channel of the MOSFET, and the doping concentration of the body region will affect the on-resistance of the MOSFET.

The body region is located below the source region;

The source region is connected to the source electrode and is a highly doped semiconductor region with low resistivity and forms ohmic contact with the metal electrode. The contact surface between metal and semiconductor is divided into two types: Schottky contact and Ohmic contact. Ohmic contact is when the doping concentration of the semiconductor is very high. When the semiconductor with high doping concentration comes into contact with the metal, a low barrier layer is formed. Electrons can pass through the barrier through the tunnel effect, thus forming a low resistance ohmic contact. Ohmic contact The characteristic is that the current-voltage characteristics of the contact surface are linear, and the contact resistance is negligible compared to the bulk resistance of the semiconductor. When a current passes through, the voltage drop generated is smaller than the voltage drop on the device.

The source is deposited above the source region;

The source is the source of charge in the MOSFET and is the outlet of the charge. When the MOSFET is in the on state, a conductive path is formed between the source and drain, and electrons flow from the source to the drain to complete the transmission of current. At the same time, the source also plays the role of modulating the gate voltage. By controlling the change of the source voltage, the MOSFET is controlled.

The gate is deposited in the trench.

The gate is the control electrode in the MOSFET. It is separated from the channel by an insulating layer and is a key part of the MOSFET. Changes in gate voltage can change the charge density in the channel, thereby controlling the amount of current between the drain and source.

When manufacturing trench MOSFETs in the existing process, the trenches are etched in the drift area, and then ions are implanted in the drift area to form the body and source areas. Finally, electrodes are deposited to form the trench MOSFET. During the ion implantation process, the channel length cannot be determined. Effective shrinkage, and the channel length and doping concentration are unevenly distributed on the chip, resulting in a greatly increased on-resistance, thereby reducing the device performance of the trench MOSFET. In order to overcome the shortcomings of the existing technology, the present invention uses an epitaxial process Instead of the traditional ion implantation method to form the body region, the epitaxial process can accurately control the depth of the body region, effectively shrink the channel length, reduce the channel resistance, and have a better channel doping concentration distribution. The body region formed by the epitaxial process can effectively reduce the on-resistance of trench MOEFST and improve the device performance of trench MOSFET.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. The preparation method of the trench MOSFET based on the P-type epitaxy for reducing the on-resistance is characterized by comprising the following steps of:

forming a body region above the drift region by adopting an epitaxial process;

forming a source region by ion implantation on the upper layer of the body region;

etching a through hole in the body region and the source region, and etching a groove in the upper layer of the drift region, wherein the through hole is connected with the groove;

a drain is deposited under the substrate, a source is deposited over the source region, and a gate is deposited in the trench.

2. The method for manufacturing a trench MOSFET with reduced on-resistance based on P-type epitaxy as claimed in claim 1, wherein forming a body region above a drift region by epitaxy process specifically comprises:

filling reaction gas into a reaction chamber according to a preset flow rate, adjusting the temperature in the reaction chamber to a preset temperature, and adjusting the pressure in the reaction chamber to a preset pressure;

the reaction gas reacts on the surface of the drift region to form a body region film;

and stopping the reaction after the body area film grows to a preset value.

3. The method for manufacturing a trench MOSFET according to claim 2, wherein stopping the reaction after the body film grows to a predetermined value specifically comprises: when the body region film grows to 0.1-2um, the reaction gas stops filling the reaction chamber.

4. The method for fabricating a trench MOSFET with reduced on-resistance based on P-type epitaxy of claim 2, wherein the adjusting the temperature in the reaction chamber to a predetermined temperature specifically comprises: the temperature in the reaction chamber was adjusted to 950-1150 ℃.

5. The method for manufacturing a P-type epitaxial reduced on-resistance trench MOSFET according to claim 2, wherein the reactive gas comprises: h ₂ 、N ₂ 、CH ₄ 、O ₂ And SiH ₄ 。

6. The method for fabricating a trench MOSFET with reduced on-resistance based on P-type epitaxy of claim 2, wherein the adjusting the pressure in the reaction chamber to a predetermined pressure specifically comprises: the pressure in the reaction chamber was adjusted to 101.325KPa.

7. The method for manufacturing a P-type epitaxial reduced on-resistance trench MOSFET according to claim 1, wherein the thickness of the body region is 0.1-2um.

8. The method for manufacturing a trench MOSFET with reduced on-resistance based on P-type epitaxy as claimed in claim 1, wherein the doping concentration of the body region is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 。

9. The method for fabricating a P-type epitaxial reduced on-resistance trench MOSFET of claim 1, further comprising, prior to forming a body region over a drift region using an epitaxial process: a drift region is epitaxially formed over the substrate.

10. A P-type epitaxial reduced on-resistance trench MOSFET comprising: a substrate, a drift region, a body region, a source, a drain and a gate;

the drain is deposited under the substrate;

the substrate is positioned below the drift region;

the drift region is located below the body region;

the body region is located below the source region;

the source electrode is deposited above the source electrode region;

the gate is deposited in the trench.