CN116487418A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The method for preparing the semiconductor structure includes the following steps. A substrate is provided, and grooves are formed in the substrate. A protective layer is formed which conformally covers the bottom of the trench. An inhibiting layer is formed, and the inhibiting layer covers the sidewall of the trench and is in contact with the protection layer. Remove the protective layer. A first gate oxide layer is formed at the bottom of the trench by a thermal oxidation process, and the inhibiting layer is thermally oxidized simultaneously to form a second gate oxide layer; the thickness of the first gate oxide layer is greater than that of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together form a gate oxide layer. The preparation method of the above semiconductor structure increases the thickness of the gate oxide layer at the bottom of the trench, so the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench is improved, thereby reducing the gate-drain capacitance at the bottom of the trench and improving the high-frequency performance of the corresponding semiconductor device.

Description

Semiconductor structure and its preparation method

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background technique

In the manufacturing process of a trench metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET for short), a gate oxide layer and a gate are formed inside the trench to control the MOSFET on and off. Therefore, the preparation of the gate oxide layer and the gate is a very important process.

However, due to stress at the bottom of the trench, the gate oxide on the sidewalls of the trench in MOSFETs is thicker than the gate oxide on the bottom of the trench. In this way, the gate oxide layer at the bottom of the trench has insufficient withstand voltage and is easily broken down. Moreover, the gate oxide layer that is too thin at the bottom of the trench will easily lead to excessive gate-to-drain capacitance there, which limits the use of corresponding semiconductor devices in high-frequency applications.

Therefore, how to improve the withstand voltage capability of the gate oxide layer is an urgent problem to be solved.

Contents of the invention

Based on this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, so as to effectively improve the withstand voltage capability of the gate oxide layer.

Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, including the following steps:

providing a substrate, forming a trench in the substrate;

Form a protective layer that conforms to the bottom of the trench;

forming an inhibiting layer, the inhibiting layer covers the sidewall of the trench and is in contact with the protection layer;

remove the protective layer;

forming a first gate oxide layer at the bottom of the trench;

A second gate oxide layer covering sidewalls of the trench is formed based on the suppression layer.

In the embodiment of the present disclosure, the protective layer conformally covering the bottom of the trench is first formed, and then the suppression layer is formed to cover the sidewall of the trench, and the suppression layer is in contact with the protection layer. The unexpected effect is that, after removing the protection layer, a suppression layer covering only the sidewall of the trench can be obtained. In this way, by controlling the formation thickness of the suppression layer, the thickness of the second gate oxide layer formed based on the suppression layer and covering the sidewall of the trench subsequently can be controlled. In this way, the thickness difference between the first gate oxide layer at the bottom of the trench and the second gate oxide layer at the sidewall of the trench can be simply adjusted. For example, the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewall of the trench. Based on this, the thickness of the gate oxide layer at the bottom of the trench can be simply increased through the method for preparing the semiconductor structure, so the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench is improved, thereby reducing the gate-drain capacitance at the bottom of the trench and improving the high-frequency performance of the corresponding semiconductor device.

Optionally, the step of forming a protective layer includes:

An initial protective layer is formed, and the initial protective layer conforms to the inner wall of the trench;

forming a mask layer, and the mask layer fills the bottom of the trench to define a formation area of the protective layer;

patterning the initial protection layer based on the mask layer to form a protection layer;

Remove the masking layer.

In the embodiment of the present disclosure, the protective layer conformally covers the bottom of the trench and is patterned based on the initial protective layer and mask layer, so that the formation area of the protective layer can be accurately defined, thereby accurately defining the formation area of the suppression layer on the sidewall of the trench. In this way, by controlling the formation area of the suppression layer, the formation area of the second gate oxide layer and the first gate oxide layer can be effectively controlled, thereby accurately controlling the thickness of the first gate oxide layer at the bottom of the trench and the thickness of the second gate oxide layer at the sidewall of the trench. Moreover, the protective layer is obtained based on the patterning of the mask layer, which also facilitates the simplification of its preparation process to improve production efficiency.

Optionally, the material of the mask layer includes photoresist.

Optionally, the second gate oxide layer is formed by an oxidation inhibiting layer.

Optionally, the first gate oxide layer is formed by a thermal oxidation process; the second gate oxide layer is formed by simultaneously forming the first gate oxide layer through an oxidation suppression layer.

In the embodiment of the present disclosure, when the thermal oxidation process is used to oxidize the structure after removing the protective layer, since the sidewall of the trench is covered with the suppression layer, the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewall of the trench. In this way, the thickness of the gate oxide layer at the bottom of the trench is increased, further improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

Optionally, the oxidation rate for forming the first gate oxide layer is greater than the oxidation rate for forming the second gate oxide layer. In this way, the same thermal oxidation process can be used to ensure that the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewall of the trench, thereby improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

Optionally, the value range of the ratio of the oxidation rate for forming the first gate oxide layer to the oxidation rate for forming the second gate oxide layer includes: 19-21. In this way, by reasonably selecting the ratio of the oxidation rate between the first gate oxide layer and the second gate oxide layer, the ratio of the thicknesses of the first gate oxide layer at the bottom of the trench to the second gate oxide layer at the sidewall of the trench can be reasonably controlled, so as to ensure that the thicknesses of the first gate oxide layer and the second gate oxide layer meet the performance requirements of the semiconductor structure.

Optionally, after forming the second gate oxide layer, the manufacturing method of the semiconductor structure further includes: using a thermal oxidation process to oxidize surfaces of the substrate close to the first gate oxide layer and the second gate oxide layer to form a third gate oxide layer. Wherein, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer jointly constitute the gate oxide layer.

In the embodiment of the present disclosure, forming the third gate oxide layer on the surface of the substrate close to the first gate oxide layer and the second gate oxide layer can further increase the thickness of the gate oxide layer at the bottom of the trench, thereby further improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

Optionally, the material of the substrate includes silicon or highly doped silicon; the material of the suppression layer includes silicon carbide or low doped silicon.

In the embodiment of the present disclosure, the material of the substrate is silicon or highly doped silicon, and the material of the suppression layer is silicon carbide or low doping silicon, which can ensure that the oxidation rate of the substrate is higher than that of the suppression layer, so as to ensure that the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewall of the trench.

Optionally, the suppression layer is formed using a selective epitaxial growth process.

Based on the same inventive concept, the present disclosure also provides a semiconductor structure obtained by using the preparation methods in some of the above embodiments. The semiconductor structure includes: a substrate, a first gate oxide layer and a second gate oxide layer. The substrate has grooves in it. The first gate oxide layer is filled at the bottom of the trench. The second gate oxide layer covers the sidewall of the trench and is connected to the first gate oxide layer. Wherein, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer. The first gate oxide layer and the second gate oxide layer together constitute a gate oxide layer.

In the embodiment of the present disclosure, the semiconductor structure adopts the above structure, and the technical effect achieved by the semiconductor structure is the same as that achieved by the method for preparing the semiconductor structure in the foregoing embodiments, and will not be described in detail here.

Optionally, the semiconductor structure further includes: a third gate oxide layer. The third gate oxide layer is located between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer. Wherein, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer jointly constitute the gate oxide layer.

In the embodiment of the present disclosure, the third gate oxide layer located between the substrate and the first gate oxide layer and between the substrate and the second gate oxide layer further increases the thickness of the gate oxide layer at the bottom of the trench, thereby further improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

As mentioned above, in the semiconductor structure and its preparation method provided by the embodiments of the present disclosure, by first forming a protective layer conformally covering the bottom of the trench, and then forming a suppressing layer covering the sidewall of the trench and making the suppressing layer contact with the protective layer, unexpected effects can be obtained after removing the protective layer and forming a gate oxide layer: simply and effectively increasing the thickness of the gate oxide layer at the bottom of the trench to improve the insufficient withstand voltage of the gate oxide layer at the bottom of the trench, thereby reducing the gate-drain capacitance at the bottom of the trench and improving the high-frequency performance of the corresponding semiconductor device; and, the protective layer is based on Obtaining the patterned mask layer is also conducive to simplifying the manufacturing process of the semiconductor structure to improve production efficiency.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work.

FIG. 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

2 is a schematic cross-sectional view of a structure obtained in step S10 in a method for preparing a semiconductor structure provided by an embodiment;

FIG. 3 is a flow chart of forming a protective layer in a method for preparing a semiconductor structure provided in an embodiment;

4 is a schematic cross-sectional view of a structure obtained in step S21 in a method for preparing a semiconductor structure provided by an embodiment;

5 is a schematic cross-sectional view of a structure obtained in step S22 in a method for preparing a semiconductor structure provided by an embodiment;

6 is a schematic cross-sectional view of a structure obtained in step S23 in a method for preparing a semiconductor structure provided by an embodiment;

7 is a schematic cross-sectional view of a structure obtained in step S24 in a method for preparing a semiconductor structure provided by an embodiment;

8 is a schematic cross-sectional view of a structure obtained in step S30 in a method for preparing a semiconductor structure provided by an embodiment;

9 is a schematic cross-sectional view of a structure obtained in step S40 in a method for preparing a semiconductor structure provided by an embodiment;

FIG. 10 is a schematic cross-sectional view of a structure obtained in step S50 in a method for preparing a semiconductor structure provided by an embodiment; and FIG. 10 is also a schematic cross-sectional view of a semiconductor structure provided by an embodiment;

FIG. 11 is a schematic cross-sectional view of another structure obtained in step S50 in the manufacturing method of a semiconductor structure provided by an embodiment; and FIG. 11 is also a schematic cross-sectional view of another semiconductor structure provided by an embodiment.

Explanation of reference signs:

1-substrate; 11-groove;

20-protection layer; 200-initial protection layer;

30 - mask layer;

40 - suppression layer;

50-gate oxide layer; 51-first gate oxide layer; 52-second gate oxide layer; 53-third gate oxide layer;

60 - Gate.

Detailed ways

In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the description of the present disclosure are for the purpose of describing specific embodiments only, and are not intended to limit the present disclosure.

It will be appreciated that spatially relative terms such as "under," "beneath," "beneath," "beneath," "on," "above," etc., may be used herein to describe one element or feature's relationship to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. In addition, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

When used herein, the singular forms "a", "an" and "the/the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "consists of" and/or "comprising" are used in this specification, the presence of said features, integers, steps, operations, elements and/or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups can be determined. Also, when used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (Physical Vapor Deposition, referred to as PVD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the invention.

In the manufacturing process of a trench metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET for short), a gate oxide layer and a gate are formed inside the trench to control the MOSFET on and off. Therefore, the preparation of the gate oxide layer and the gate is a very important process.

However, due to stress at the bottom of the trench, the gate oxide on the sidewalls of the trench in MOSFETs is thicker than the gate oxide on the bottom of the trench. In this way, the gate oxide layer at the bottom of the trench has insufficient withstand voltage and is easily broken down. Moreover, the gate oxide layer that is too thin at the bottom of the trench will easily lead to excessive gate-to-drain capacitance there, which limits the use of corresponding semiconductor devices in high-frequency applications.

Therefore, how to improve the withstand voltage capability of the gate oxide layer is an urgent problem to be solved.

In view of the deficiencies of the above-mentioned related technologies, the purpose of the embodiments of the present disclosure is to provide a semiconductor structure and a manufacturing method thereof, so as to effectively improve the withstand voltage capability of the gate oxide layer.

Please refer to FIG. 1 , in some embodiments, some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, and the method includes the following steps.

S10: providing a substrate, and forming a trench in the substrate.

S20: forming a protective layer, and the protective layer conformally covers the bottom of the trench.

S30: forming a suppression layer, the suppression layer covers the sidewall of the trench and is in contact with the protection layer.

S40: removing the protective layer.

S50: forming a first gate oxide layer at the bottom of the trench;

S60: forming a second gate oxide layer covering the sidewall of the trench based on the suppression layer.

In the embodiment of the present disclosure, the protective layer conformally covering the bottom of the trench is first formed, and then the suppression layer is formed to cover the sidewall of the trench, and the suppression layer is in contact with the protection layer. The unexpected effect is that, after removing the protection layer, a suppression layer covering only the sidewall of the trench can be obtained. In this way, by controlling the formation thickness of the suppression layer, the thickness of the second gate oxide layer formed based on the suppression layer and covering the sidewall of the trench subsequently can be controlled. In this way, the thickness difference between the first gate oxide layer at the bottom of the trench and the second gate oxide layer at the sidewall of the trench can be simply adjusted. For example, the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewall of the trench. Based on this, the thickness of the gate oxide layer at the bottom of the trench can be simply increased through the method for preparing the semiconductor structure, so the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench is improved, thereby reducing the gate-drain capacitance at the bottom of the trench and improving the high-frequency performance of the corresponding semiconductor device.

The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 2 to FIG. 11 .

In step S10 , referring to S10 in FIG. 1 and FIG. 2 , a substrate 1 is provided, and trenches 11 are formed in the substrate 1 .

In some examples, the substrate 1 may include, but is not limited to, a silicon substrate. Moreover, according to the distribution of the shape of the trench 11 in the substrate 1, the trench 11 can be divided into the bottom of the trench 11 and the sidewall of the trench 11; that is, a virtual boundary can be regarded as a virtual boundary between the bottom of the trench 11 and the sidewall of the trench 11, so as to define corresponding formation positions of the first gate oxide layer and the second gate oxide layer.

In some examples, the surface at the bottom of the groove 11 is a curved surface.

Optionally, a dry etching process may be used to form the trench 11 in the substrate 1 .

In step S20 , referring to S20 in FIG. 1 and FIGS. 3 to 6 , a protective layer 20 is formed, and the protective layer 20 conformally covers the bottom of the trench 11 .

Here, the protective layer 20 conformally covers the bottom of the groove 11, which means that the protective layer 20 has a thin layer structure, and the surface of the protective layer 20 is simulated to the surface at the bottom of the groove 11, so that the surface shape of the protective layer 20 is similar to the surface shape of the bottom of the groove 11.

In some embodiments, please refer to FIG. 3 , forming the protection layer 20 includes the following steps.

S21: forming an initial protection layer, and the initial protection layer conformally covers the inner wall of the trench.

S22: forming a mask layer, the mask layer fills the bottom of the trench to define a formation area of the protective layer.

S23: Patterning the initial protective layer based on the mask layer to form a protective layer.

S24: removing the mask layer.

In the embodiment of the present disclosure, the protective layer 20 conformally covers the bottom of the trench 11 and is patterned based on the initial protective layer and mask layer, so that the formation area of the protective layer 20 can be accurately defined, thereby accurately defining the formation area of the suppression layer on the sidewall of the trench 11. In this way, by controlling the formation area of the suppression layer, the formation area of the second gate oxide layer and the first gate oxide layer can be effectively controlled, and then the thickness of the first gate oxide layer at the bottom of the trench 11 and the thickness of the second gate oxide layer on the sidewall of the trench 11 can be precisely controlled. Moreover, the protection layer 20 is obtained by patterning the mask layer, which is also beneficial to simplify its preparation process and improve production efficiency.

In step S21 , referring to FIG. 4 , an initial protection layer 200 is formed, and the initial protection layer 200 conformally covers the inner wall of the trench 11 .

In some embodiments, the initial protective layer 200 also extends to cover the upper surface of the substrate 1 .

Optionally, the thickness range of the initial protection layer 200 includes: 200 angstroms to 1000 angstroms. For example, the thickness of the initial protective layer 200 can be 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms or 1000 angstroms, etc.

Optionally, the material of the initial protection layer 200 may include but not limited to silicon oxide.

Optionally, the initial protective layer 200 is formed by a thermal oxidation process.

In step S22 , referring to FIG. 5 , a mask layer 30 is formed, and the mask layer 30 fills the bottom of the trench 11 to define a formation area of the protective layer 20 .

In some embodiments, forming the mask layer 30 includes: forming an initial mask layer (not shown in FIG. 5 ), the initial mask layer at least fills up the trench 11 ; and removing part of the initial mask layer 300 to form the mask layer 30 .

Optionally, an etch-back process may be used to remove part of the initial mask layer 300 .

Optionally, the material of the mask layer 30 includes but not limited to photoresist.

In step S23 , referring to FIG. 6 , the initial protective layer 200 is patterned based on the mask layer 30 to form the protective layer 20 .

In some embodiments, based on the mask layer 30 , an etching process may be used to remove the sidewalls of the trench 11 and the initial protective layer 200 on the upper surface of the substrate 1 to form the protective layer 20 .

In step S24 , referring to FIG. 7 , the mask layer 30 is removed.

Optionally, an etch-back process may be used to remove the mask layer 30 .

In step S30 , referring to S30 in FIG. 1 and FIG. 8 , an inhibiting layer 40 is formed, and the inhibiting layer 40 covers the sidewall of the trench 11 and is in contact with the passivation layer 20 .

Optionally, the material of the substrate 1 includes silicon or highly doped silicon, and the material of the suppression layer 40 includes silicon carbide or low doped silicon. It should be noted that when the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is low doped silicon, the oxidation rate of the suppression layer 40 is about 10%-20% slower than that of the substrate 1 . When the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is silicon carbide, the oxidation rate of the suppression layer 40 is only 5%-10% of that of the substrate 1 .

In the embodiment of the present disclosure, the material of the substrate 1 is silicon or highly doped silicon, and the material of the suppression layer 40 is silicon carbide or low doping silicon, which can ensure that the oxidation rate of the substrate 1 is higher than the oxidation rate of the suppression layer 40, so as to ensure that the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than the thickness of the second gate oxide layer 52 formed on the sidewall of the trench 11.

In some embodiments, the suppression layer 40 also extends over the upper surface of the substrate 1 .

Optionally, the suppression layer 40 is formed by a selective epitaxial growth process.

In some embodiments, the film thickness of the suppression layer 40 depends on the height difference ΔH between the bottom of the trench 11 and the sidewall of the trench 11 . Wherein, ΔH is equal to the difference between the height H1 of the sidewall of the trench 11 and the height H2 of the bottom of the trench 11 .

For example, the ratio of the oxidation rate of the suppression layer 40 to the oxidation rate of the bottom substrate 1 of the trench 11 is 1:20, and without considering the influence of the film thickness of the suppression layer 40 on the oxidation rate, the thickness of the suppression layer 40 is about 1/19 of the aforementioned height difference ΔH.

It should be noted that after the subsequent suppression layer 40 is completely oxidized, the substrate 1 at the sidewall of the trench 11 and the substrate 1 at the bottom of the trench 11 can be further oxidized to form a third gate oxide layer. At this time, since the second gate oxide layer formed based on the suppression layer 40 at the sidewall of the trench 11 is thinner and the first gate oxide layer formed at the bottom of the trench 11 is thicker, when the thermal oxidation process is continued, the oxidation rate of the substrate 1 at the sidewall of the trench 11 will be greater than the oxidation rate of the substrate 1 at the bottom of the trench 11, so that the thickness difference between the oxide layer at the sidewall of the trench 11 and the oxide layer at the bottom of the trench 11 is reduced. Here, the oxide layer at the sidewall of the trench 11 includes the second gate oxide layer and the third gate oxide layer at the sidewall of the trench 11 ; the oxide layer at the bottom of the trench 11 includes the first gate oxide layer and the third gate oxide layer at the bottom of the trench 11 .

Based on this, in some embodiments, the thickness of the suppression layer 40 can be reasonably increased, for example, the thickness of the suppression layer 40 is greater than 1/19 of the aforementioned height difference ΔH.

In step S40 , referring to S40 in FIG. 1 and FIG. 9 , the protection layer 20 is removed.

Optionally, the protection layer 20 can be removed by using a wet etching process.

Exemplarily, the wet etching solution may include, but not limited to, a buffered oxide etch solution (Buffered Oxide Etch, BOE for short) and a hydrofluoric acid etchant (the ratio of hydrofluoric acid to water may be 100:1, for example).

In step S50 , referring to S50 in FIG. 1 and FIG. 10 , a first gate oxide layer 51 is formed at the bottom of the trench 11 .

In step S60 , referring to S60 in FIG. 1 and FIG. 10 , a second gate oxide layer 52 covering sidewalls of the trench 11 is formed based on the suppression layer 40 .

In some embodiments, the second gate oxide layer 52 is formed through the oxidation inhibiting layer 40 .

In some embodiments, the first gate oxide layer 51 is formed by a thermal oxidation process; the second gate oxide layer 52 is formed by simultaneously forming the first gate oxide layer 51 with the oxidation inhibiting layer 40 .

In the embodiment of the present disclosure, when the thermal oxidation process is used to oxidize the structure after removing the protective layer 30, since the sidewall of the trench 11 is covered with the suppression layer 40, the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than the thickness of the second gate oxide layer 52 formed on the sidewall of the trench 11. In this way, the thickness of the gate oxide layer at the bottom of the trench 11 is increased, further improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

In some embodiments, the suppression layer 40 also extends to cover the upper surface of the substrate 1 , and accordingly, the second gate oxide layer 52 formed based on the suppression layer 40 also extends to cover the upper surface of the substrate 1 .

In some embodiments, the oxidation rate for forming the first gate oxide layer 51 is greater than the oxidation rate for forming the second gate oxide layer 52 . In this way, the same thermal oxidation process can be used to ensure that the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than the thickness of the second gate oxide layer 52 formed on the sidewall of the trench 11, thereby improving the problem of insufficient withstand voltage of the gate oxide layer 50 at the bottom of the trench 11.

In some examples, the value range of the ratio of the oxidation rate for forming the first gate oxide layer 51 to the oxidation rate for forming the second gate oxide layer 52 includes: 19-21.

It should be noted that the oxidation rate of the formation of the first gate oxide layer is the oxidation rate of the bottom substrate 1 of the trench 11 , and the oxidation rate of the formation of the second gate oxide layer is the oxidation rate of the suppression layer 40 .

In the embodiment of the present disclosure, by reasonably selecting the ratio of the oxidation rate between the first gate oxide layer 51 and the second gate oxide layer 52, the ratio of the thicknesses of the first gate oxide layer 51 at the bottom of the trench 11 and the thickness of the second gate oxide layer 52 on the sidewall of the trench 11 can be reasonably controlled, so as to ensure that the thicknesses of the first gate oxide layer 51 and the second gate oxide layer 52 meet the performance requirements of the semiconductor structure.

In some embodiments, referring to FIG. 11 , after forming the second gate oxide layer 52 , the preparation method further includes: using a thermal oxidation process, oxidizing the surfaces of the substrate 10 close to the first gate oxide layer 51 and the second gate oxide layer 52 to form a third gate oxide layer 53 . Wherein, the first gate oxide layer 51 , the second gate oxide layer 52 and the third gate oxide layer 53 together constitute the gate oxide layer 50 .

Here, after the suppression layer 40 is completely oxidized to form the second gate oxide layer 52 , the substrate 1 at the sidewall of the trench 11 and the substrate 1 at the bottom of the trench 11 may be further oxidized to form the third gate oxide layer 53 . That is to say, the aforementioned thermal oxidation process for forming the third gate oxide layer 53 and the thermal oxidation process for forming the second gate oxide layer 52 and the first gate oxide layer 51 may be the same thermal oxidation process.

In the embodiment of the present disclosure, forming the third gate oxide layer 53 on the surface of the substrate 1 close to the first gate oxide layer 51 and the second gate oxide layer 52 can further increase the thickness of the gate oxide layer 50 at the bottom of the trench 11, thereby further improving the problem of insufficient withstand voltage of the gate oxide layer 50 at the bottom of the trench 11.

Optionally, the material of the gate oxide layer 50 (including the first gate oxide layer 51 , the second gate oxide layer 52 or the third gate oxide layer 53 ) may include but not limited to silicon oxide.

In some embodiments, referring to FIGS. 10 and 11 , after forming the gate oxide layer 50 , the fabrication method further includes: forming a gate 60 at least filling the trench 11 on the surface of the gate oxide layer 50 away from the substrate 10 .

Exemplarily, the gate 60 is formed of a conductive material with excellent electrical properties, such as doped polysilicon, metal copper, or metal tungsten.

Based on the same inventive concept, please refer to FIG. 10 and FIG. 11 , the present disclosure also provides a semiconductor structure obtained by using the preparation methods in some of the above-mentioned embodiments. The semiconductor structure includes: a substrate 1 , a first gate oxide layer 51 and a second gate oxide layer 52 . The substrate 1 has a trench 11 in it. The first gate oxide layer 51 is filled at the bottom of the trench 11 . The second gate oxide layer 52 covers the sidewall of the trench 11 and is connected to the first gate oxide layer 51 . Wherein, the thickness of the first gate oxide layer 51 is greater than the thickness of the second gate oxide layer 52 . The first gate oxide layer 51 and the second gate oxide layer 52 together constitute the gate oxide layer 50 .

In the embodiment of the present disclosure, the semiconductor structure adopts the above structure, and the technical effect achieved by the semiconductor structure is the same as that achieved by the method for preparing the semiconductor structure in the foregoing embodiments, and will not be described in detail here.

Optionally, the material of the substrate 1 includes silicon or highly doped silicon. The second gate oxide layer 52 is obtained based on oxidation of the suppression layer 40 . The material of the suppression layer 40 includes silicon carbide or low doped silicon. It should be noted that when the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is low doped silicon, the oxidation rate of the suppression layer 40 is about 10%-20% slower than that of the substrate 1 . When the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is silicon carbide, the oxidation rate of the suppression layer 40 is only 5%-10% of that of the substrate 1 .

In some embodiments, the thickness of the second gate oxide layer 52 (that is, the film thickness of the suppression layer 40 ) depends on the height difference ΔH between the bottom of the trench 11 and the sidewall of the trench 11 . Wherein, ΔH is equal to the difference between the height H1 of the sidewall of the trench 11 and the height H2 of the bottom of the trench 11 . For example, if the ratio of the oxidation rate of the suppression layer 40 to the oxidation rate of the bottom substrate 1 of the trench 11 is 1:20, then the thickness of the second gate oxide layer 52 (that is, the film thickness of the suppression layer 40 ) can be 1/19 of the aforementioned height difference ΔH without considering the influence of the film thickness on the oxidation rate.

In some examples, the surface at the bottom of the groove 11 is a curved surface.

In some embodiments, referring to FIG. 11 , the semiconductor structure further includes: a third gate oxide layer 53 . The third gate oxide layer 53 is located between the substrate 1 and the first gate oxide layer 51 , and between the substrate 1 and the second gate oxide layer 52 . Wherein, the first gate oxide layer 51 , the second gate oxide layer 52 and the third gate oxide layer 53 together constitute a gate oxide layer.

In the embodiment of the present disclosure, the third gate oxide layer 53 located between the substrate 1 and the first gate oxide layer 51 and between the substrate 1 and the second gate oxide layer 52 further increases the thickness of the gate oxide layer 50 at the bottom of the trench 11, thereby further improving the problem of insufficient withstand voltage of the gate oxide layer 50 at the bottom of the trench 11.

Optionally, the material of the gate oxide layer 50 (including the first gate oxide layer 51 , the second gate oxide layer 52 or the third gate oxide layer 53 ) may include but not limited to silicon oxide.

In some embodiments, referring to FIGS. 10 and 11 , the semiconductor structure further includes: a gate 60 disposed on the surface of the gate oxide layer 50 away from the substrate 10 and at least filling the trench 11 .

Exemplarily, the gate 60 is formed of a conductive material with excellent electrical properties, such as doped polysilicon, metal copper, or metal tungsten.

To sum up, in the semiconductor structure and its manufacturing method provided by the embodiments of the present disclosure, by first forming the protection layer 20 conformally covering the bottom of the trench 11 , and then forming the suppression layer 40 covering the sidewall of the trench 11 and making the suppression layer 40 in contact with the protection layer 20 , an unexpected effect can be obtained after removing the protection layer 20 and forming the gate oxide layer 50 . Therefore, the gate-to-drain capacitance at the bottom of the trench 11 is reduced, and the high-frequency performance of the corresponding semiconductor device is improved; moreover, the protective layer 20 is obtained by patterning based on the mask layer 30, which also facilitates the simplification of the manufacturing process of the semiconductor structure to improve production efficiency.

In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features of the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present disclosure, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the scope of protection of the disclosed patent should be based on the appended claims.

Claims (12)

1. A method for preparing a semiconductor structure, comprising: providing a substrate in which a trench is formed; forming a protective layer conformally covering the bottom of the trench; forming an inhibiting layer, the inhibiting layer covers the sidewall of the trench and is in contact with the protection layer; removing said protective layer; forming a first gate oxide layer at the bottom of the trench; A second gate oxide layer covering sidewalls of the trench is formed based on the suppression layer. 2. The method for preparing a semiconductor structure according to claim 1, wherein the step of forming the protective layer comprises: forming an initial protective layer, the initial protective layer conformally covers the inner wall of the trench; forming a mask layer filling the bottom of the trench to define a formation area of the protective layer; patterning the initial protection layer based on the mask layer to form a protection layer; removing the mask layer. 3 . The method for fabricating a semiconductor structure according to claim 2 , wherein the material of the mask layer comprises photoresist. 4 . 4. The method for fabricating a semiconductor structure according to claim 1, wherein the second gate oxide layer is formed by oxidizing the suppression layer. 5. the preparation method of semiconductor structure according to claim 1 or 4, is characterized in that, The first gate oxide layer is formed by a thermal oxidation process; The second gate oxide layer is formed by simultaneously oxidizing the suppression layer while forming the first gate oxide layer. 6 . The method for fabricating a semiconductor structure according to claim 5 , wherein an oxidation rate for forming the first gate oxide layer is greater than an oxidation rate for forming the second gate oxide layer. 7 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the value range of the ratio of the oxidation rate for forming the first gate oxide layer to the oxidation rate for forming the second gate oxide layer includes: 19-21. 8. The method for preparing a semiconductor structure according to claim 1, wherein after forming the second gate oxide layer, the method further comprises: using a thermal oxidation process to oxidize the surfaces of the substrate close to the first gate oxide layer and the second gate oxide layer to form a third gate oxide layer; Wherein, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together constitute a gate oxide layer. 9 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the material of the substrate comprises silicon or highly doped silicon; the material of the suppression layer comprises silicon carbide or low doped silicon. 10 . The method for manufacturing a semiconductor structure according to claim 9 , wherein the suppression layer is formed by a selective epitaxial growth process. 11 . 11. A semiconductor structure, characterized in that it is prepared by the preparation method according to any one of claims 1 to 10; the semiconductor structure comprises: a substrate having a trench therein; a first gate oxide layer, filled at the bottom of the trench; a second gate oxide layer covering the sidewall of the trench and connected to the first gate oxide layer; Wherein, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together form a gate oxide layer. 12. The semiconductor structure according to claim 11, further comprising: a third gate oxide layer located between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer; Wherein, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together constitute a gate oxide layer.