CN206697482U - A kind of trench metal-oxide semiconductor - Google Patents
A kind of trench metal-oxide semiconductor Download PDFInfo
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- CN206697482U CN206697482U CN201720377915.3U CN201720377915U CN206697482U CN 206697482 U CN206697482 U CN 206697482U CN 201720377915 U CN201720377915 U CN 201720377915U CN 206697482 U CN206697482 U CN 206697482U
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Abstract
The utility model discloses a kind of trench metal-oxide semiconductor, including：Gate trench, form sediment on the bottom of the gate trench and side wall and be provided with gate oxide layers, and the thickness of the gate oxide layers of gate trench cell wall lower half and bottom is identical and be thicker than the gate oxide layers at the top of gate trench.The utility model has the advantages that：The formation of groove is only etched by a step and completed, only etch an epitaxial layer, by adjusting energy of light source during photoetching, the different oxide layer of thickness is generated in groove using the method for photoresist half-exposure, simplify the method that groove is formed using composite barrier in traditional preparation methods and then by twice etching, processing step is simplified, improves preparation efficiency.
Description
Technical field
A kind of semiconductor is the utility model is related to, more precisely a kind of trench metal-oxide semiconductor.
Background technology
With power MOS (Metal Oxide Semiconductor) device technique and the continuous maturation of design, the competition of domestic and international power MOS (Metal Oxide Semiconductor) device also increasingly swashs
Strong, cost, the performance for improving device and the reliability for reducing device are also more and more urgent.Do not influenceing the premise of device performance
Under, it is an important means for reducing device cost to reduce the photoetching number in device fabrication；And do not lifted device into
On the premise of product, the performance of device is lifted, is the important means of a lifting product competitiveness again.
Utility model content
The purpose of this utility model is to provide a kind of trench metal-oxide semiconductor, its can not lifted device into
On the premise of product, the performance of device is lifted.
The utility model uses following technical scheme：
A kind of trench metal-oxide semiconductor, including：
Gate trench, form sediment on the bottom of the gate trench and side wall and be provided with gate oxide layers, and under gate trench cell wall
The thickness of the gate oxide layers of half portion and bottom is identical and is thicker than the gate oxide layers at the top of gate trench.
Also include polysilicon layer, and gate trench is formed sediment and set completely by polysilicon layer.
For the gate trench in N-type epitaxial layer, the side of N-type epitaxial layer, which is formed sediment, is provided with N-type substrate.
Also include：Source electrode groove, source electrode groove is in N-type epitaxial layer；Form sediment and be provided with the bottom of source electrode groove and side wall
Gate oxide layers, source electrode groove is formed sediment by polysilicon to be set completely, and the N-type epitaxial layer between source electrode groove and adjacent gate trenches
Top form sediment and be provided with gate oxide layers with the bottom condition of equivalent thickness of source electrode groove.
Inject to form Channeling implantation layer, raceway groove by impurity between the top source electrode groove and gate trench of N-type epitaxial layer
The source region implanted layer formed by source region injection and impurity activation is provided with inside implanted layer.
Gate trench both sides are provided with contact hole, and contact hole, the bottom of contact hole are provided with the polysilicon layer of source electrode trench interiors
Portion is located at Channeling implantation layer and passes through source region implanted layer, the first metal of deposit in contact hole, and is formed sediment above the first metal and set second
Metal, formed sediment between second metal layer and gate oxide layers and be provided with dielectric layer.
A kind of preparation method for preparing trench metal-oxide semiconductor, comprises the following steps：
One layer of thicker oxide layer is grown on groove, forms grid oxygen, the gate oxide forms sediment located at the bottom land and cell wall of groove；
Photoresist is deposited, it is full by being filled in groove；
Photoresist carries out half-exposure, by adjusting exposure energy, retains the photoresist of groove inner bottom part；
Oxide layer is etched, and the oxide layer in groove above photoresist is removed, and the oxide layer of channel bottom retains；
Except photoresist, and oxide layer is grown, interior one layer of thinner gate oxide of regrowth above groove and between groove.
It is further comprising the steps of：
Depositing polysilicon, polysilicon is set to being formed sediment on the outside of trench interiors and gate oxide, and trench interiors are formed sediment and set completely, and it is right
Polysilicon carries out heavy doping, reduces resistivity；
Unnecessary polysilicon is etched away, makes polysilicon surface equal with area surface, but the polysilicon in groove retains, shape
Into MOSFET grid.
It is further comprising the steps of：
The photoetching of Channeling implantation area, injection, and annealed, channel region Impurity Distribution is obtained, forms injection channel region；
Source region photoetching, injection are carried out, and is annealed, activator impurity, forms injection source region；
Dielectric layer deposited, dielectric layer, which forms sediment, is located at the outside of gate oxide；
Dielectric layer is removed, carries out contact hole photoetching, and carries out contact hole injection, deposit layer of metal filling source contact openings
With gate contact hole, and excess surface metal is removed, form source electrode and grid.
It is further comprising the steps of：
Deposit second layer metal simultaneously carries out photoetching, etching, forms MOSFET extraction electrodes；
Passivation layer is deposited, photoetching, etching is carried out, the passivation layer on second layer metal surface is removed, packaging and routing is reserved and connects
Tactile fairlead.
The utility model has the advantages that：The structure of bottom thickness grid oxygen provides higher breakdown voltage for device, on groove
The thin grid oxygen of half part ensure that the relatively low cut-in voltage of device., can when being adjusted to reach identical breakdown voltage with traditional structure
Using the smaller epitaxial layer of resistivity, so to effectively reduce the conducting resistance of device again, reach lifting device performance
Purpose.
Brief description of the drawings
The utility model is described in detail with reference to embodiment and accompanying drawing, wherein：
Fig. 1 is structural representation of the present utility model.
Fig. 2 to Figure 18 is the structural representation of the intermediate of preparation method of the present utility model.
Embodiment
Specific embodiment of the present utility model is expanded on further below in conjunction with the accompanying drawings：
As shown in figure 1, a kind of trench metal-oxide semiconductor, including：Gate trench, the bottom of the gate trench
And formed sediment in side wall and be provided with gate oxide layers, and the gate oxide layers 30 of gate trench cell wall lower half and bottom thickness it is identical and
The gate oxide layers 50 being thicker than at the top of gate trench, form sediment between gate trench the gate oxide being provided with the top of the groove same thickness
Layer 50.
Compared with the structure of conventional MOSFET device, the structure of bottom thickness grid oxygen provides structure of the present utility model for device
Higher breakdown voltage, the thin grid oxygen of groove top half ensure that the relatively low cut-in voltage of device.When being adjusted to and conventional junction
When structure reaches identical breakdown voltage, the smaller epitaxial layer of resistivity can be used, so effectively reduces the conducting of device again
Resistance, the purpose of lifting device performance is reached.
The utility model also includes polysilicon layer 60, and gate trench is formed sediment and set completely by polysilicon layer.
For gate trench located in N-type epitaxial layer 20, the side of N-type epitaxial layer, which is formed sediment, is provided with N-type substrate 10.
The utility model also includes source electrode groove, is formed sediment on the bottom of source electrode groove and side wall and is provided with gate oxide layers 30, source
Pole groove formed sediment by polysilicon sets it is full, and the top of the N-type epitaxial layer between source electrode groove and adjacent gate trenches form sediment be provided with
The gate oxide layers of the bottom condition of equivalent thickness of source electrode groove.The source electrode groove is in N-type epitaxial layer.N-type epitaxial layer
Inject to form Channeling implantation layer 70 by impurity between top source electrode groove and gate trench.It is provided with and passes through inside Channeling implantation layer
The source region implanted layer that source region is injected and impurity activation is formed.Gate trench both sides are provided with contact hole, the polycrystalline of source electrode trench interiors
Contact hole is provided with silicon layer, the bottom of contact hole located at Channeling implantation layer and passes through source region implanted layer, deposit first in contact hole
Metal, and formed sediment above the first metal and set the second metal.Formed sediment between second metal layer and gate oxide layers and be provided with dielectric layer.
The utility model bottom thickness grid oxygen, the groove structure of the thin grid oxygen of upper part reduce only by once etching completion
Process complexity, improves preparation efficiency.
The formation of first groove is only etched by a step and completed, and only etches an epitaxial layer, by adjusting light source during photoetching
Energy, the different oxide layer of thickness is generated in groove using the method for photoresist half-exposure, is simplified in traditional preparation methods
The method that groove is formed using composite barrier and then by twice etching, is simplified processing step, improves preparation efficiency.
For the thickness of thin grid oxygen typically in 150A~600A or so, this is mainly the demand according to different product to cut-in voltage
Gate oxide thickness to be adjusted, the thin grid oxygen in top is exactly to control low cut-in voltage.Bottom thickness gate oxide thickness scope one
As in 600A~3000A, for groove MOSFET in the case of with a extension, breakdown voltage is to be in the increase of gate oxide thickness
Downward trend after now first rising, the regulation breakdown reverse voltage of the thick grid oxygen effect of bottom.By adjusting bottom gate oxide thickness
To improve breakdown voltage, then the lower extension of resistivity can be used to coordinate the bottom grid oxygen after regulation, with it is general
In the case that MOSFET reaches identical voltage, because using the extension of lower electrical resistivity of epitaxy, conducting resistance can be effectively reduced.
A kind of preparation method of trench metal-oxide semiconductor, comprises the following steps：
One layer of thicker oxide layer is grown on groove, forms grid oxygen, the gate oxide forms sediment located at the bottom land and cell wall of groove；
Photoresist is deposited, it is full by being filled in groove；
Photoresist carries out half-exposure, by adjusting exposure energy, retains the photoresist of groove inner bottom part；
Oxide layer is etched, and the oxide layer in groove above photoresist is removed, and the oxide layer of channel bottom retains；
Except photoresist, and oxide layer is grown, interior one layer of thinner gate oxide of regrowth above groove and between groove.
Gate trench of the present utility model can be prepared in preparation method of the present utility model, realize channel bottom thickness grid
Oxygen, the structure of the thin grid oxygen in surface.
In preparation method of the present utility model, groove is located in N-type epitaxial layer, and oxide layer is grown on groove, growth
One layer of thicker oxide layer, forms grid oxygen, and the gate oxide forms sediment on bottom land and cell wall and epitaxial layer located at groove.
Photoresist is deposited, it is full by being filled in groove；Active area photoetching, half-exposure is carried out to photoresist, exposed by adjusting
Energy, make photoresist Partial exposure in groove；Oxide layer is etched, and upper part and surfaces of active regions oxide layer are gone in groove
Remove, the oxide layer that glue protection part is photo-etched outside channel bottom and active area retains；It is except photoresist, remaining photoresist is complete
All remove；Grow oxide layer, one layer of thinner gate oxide of regrowth in etched portions groove.
The utility model deposits photoresist, by adjustment control exposure energy, made in groove after first layer grid oxygen is grown
Photoresist Partial exposure, i.e. groove upper part photoresist are exposed, and channel bottom photoresist is not exposed, etch upper part oxygen
Change layer, remove photoresist, finally grow one layer of thin grid oxygen to realize channel bottom thickness grid oxygen, the structure of the thin grid oxygen in surface.
The utility model is further comprising the steps of：
Depositing polysilicon, polysilicon is set to being formed sediment on the outside of trench interiors and gate oxide, and trench interiors are formed sediment and set completely, and it is right
Polysilicon carries out heavy doping, reduces resistivity；
Unnecessary polysilicon is etched away, makes polysilicon surface equal with area surface, but the polysilicon in groove retains, shape
Into MOSFET grid；
The photoetching of Channeling implantation area, injection, and annealed, channel region Impurity Distribution is obtained, forms injection channel region；
Source region photoetching, injection are carried out, and is annealed, activator impurity, forms injection source region；
Dielectric layer deposited, dielectric layer, which forms sediment, is located at the outside of gate oxide；
Dielectric layer is removed, carries out contact hole photoetching, and carries out contact hole injection, deposit layer of metal filling source contact openings
With gate contact hole, and excess surface metal is removed, form source electrode and grid；
Deposit second layer metal simultaneously carries out photoetching, etching, forms MOSFET extraction electrodes；
Passivation layer is deposited, photoetching, etching is carried out, the passivation layer on second layer metal surface is removed, packaging and routing is reserved and connects
Tactile fairlead.
In the utility model preparation method, etching groove only can just be completed by a step, be completed without multiple etching, letter
Change processing step, improve preparation efficiency.
Grown as shown in Fig. 2 carrying out epitaxial layer 20 on substrate 10；It is suitable outer according to the selection of MOSFET property requirements
Prolong disk, the disk is made up of the substrate of low-resistivity and the epitaxial layer of specific electric resistance.
Deposit masking layer and carry out trench lithography, masking layer etching；One layer of masking layer 21, the masking layer are grown on epitaxial layer
21 effect is to provide masking for etching groove below, and the composition for sheltering layer material can be silica, silicon nitride or two
Person is combined, and grows a photoresist 22 in the outside of masking layer 21, and the photoetching of groove 23 is carried out to photoresist 22 and masking layer 21, and right
Masking layer 21 performs etching, and etches etching groove window 23, as shown in Figure 3.
Photoresist 22 is removed, groove 24 is carried out and etches；Groove 24 is formed under the masking action of masking layer 21, such as Fig. 4 institutes
Show.
Masking layer is removed, carries out sacrifice oxidation, and removes oxide layer, as shown in Figure 5.
Grow oxide layer, grow one layer of thicker oxide layer, formed grid oxygen, the gate oxide form sediment located at groove bottom land and
On cell wall and epitaxial layer, as shown in Figure 6.
Photoresist is deposited, full by being filled in groove, the photoresist 40 is deposited on the outside for prolonging layer and trench interiors, such as Fig. 7
It is shown.
Active area photoetching, half-exposure is carried out to photoresist, by adjusting exposure energy, expose photoresist part in groove
Light, i.e. groove upper part photoresist are exposed, and channel bottom photoresist is not exposed, as shown in Figure 8.
Oxide layer is etched, and upper part and surfaces of active regions oxide layer are removed in groove, channel bottom and active
The oxide layer that glue protection part is photo-etched outside area retains, as shown in Figure 9.
Except photoresist, remaining photoresist is all removed, as shown in Figure 10.
Growth oxide layer, the thinner gate oxide 50 of one layer of regrowth in etched portions groove, as shown in figure 11.
Depositing polysilicon 60, and heavy doping is carried out to polysilicon, resistivity is reduced, on the outside of trench interiors and gate oxide
Shallow lake sets polysilicon, and trench interiors are formed sediment and set completely, as shown in figure 12.
Unnecessary polysilicon is etched away, makes polysilicon surface equal with area surface, i.e., the polysilicon of area surface is carved
Eating away, but the polysilicon in groove retains, and forms MOSFET grid, as shown in figure 13.
Channeling implantation area's photoetching, injection are carried out, removes photoresist, and is annealed, obtains desired channel region impurity point
Cloth, injection channel region 70 is formed, as shown in figure 14.
Source region photoetching, injection are carried out, removes photoresist, and is annealed, activator impurity, injection source region 80 is formed, such as schemes
Shown in 15.
Dielectric layer deposited 90, usual material are phosphorosilicate glass, and dielectric layer, which forms sediment, is located at the outside of gate oxide 100, such as Figure 16
It is shown.
Dielectric layer is removed, carries out contact hole photoetching, and carries out contact hole injection, deposit layer of metal filling source contact openings
With gate contact hole, and excess surface metal is removed, usual metal material is tungsten, source electrode 90 and grid 100 is formed, such as Figure 17 institutes
Show.
Second layer metal 110,120 is deposited again, and carries out photoetching, etching, forms MOSFET extraction electrodes, second layer metal
It is made up of more metal layers, is common process, as shown in figure 18, and second metal layer is formed sediment and is located at the outside of dielectric layer, and complete second
Metal level contacts with the first metal layer, and the second metal 110 contacts with source electrode 90, and the second metal 120 contacts with grid 100.
Passivation layer 130,140 is deposited, passivation material is made up of silica, silicon nitride or its composite, to chip list
Face forms protection, carries out photoetching, etching, the passivation layer on second layer metal surface is removed, reserve the extraction of packaging and routing contact
Hole, form structure as shown in Figure 1.
The preparation method that the groove of the structure of thickness grid oxygen in bottom of the prior art is traditional is realized by twice etching,
Surface typically uses the compound mask version of the composition of oxide skin(coating)-Nitride-Oxide, etches top half ditch first
Groove, grow one layer of thin grid oxygen.One layer of nitration case, etching bottom nitration case and oxide layer, Ran Houjin are deposited in groove again
Second of etching of row, etches second groove, grows bottom thickness grid oxygen part.Remaining nitride in first groove is removed again
Layer, polysilicon is filled to complete this structure.Such preparation flow is more complicated, reduces device preparation efficiency.
Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model
All any modification, equivalent and improvement made within the spirit and principle of utility model etc., should be included in the utility model
Protection domain within.
Claims (9)
- A kind of 1. trench metal-oxide semiconductor, it is characterised in that including：Gate trench, form sediment on the bottom of the gate trench and side wall and be provided with gate oxide layers, and gate trench cell wall lower half And the thickness of the gate oxide layers of bottom is identical and be thicker than the gate oxide layers at the top of gate trench.
- 2. trench metal-oxide semiconductor according to claim 1, it is characterised in that also including polysilicon layer, and Polysilicon layer, which forms sediment gate trench, to be set completely.
- 3. trench metal-oxide semiconductor according to claim 1 or 2, it is characterised in that the gate trench is set In in N-type epitaxial layer, the side shallow lake of N-type epitaxial layer is provided with N-type substrate.
- 4. trench metal-oxide semiconductor according to claim 3, it is characterised in that also include：Source electrode groove, source Pole groove is in N-type epitaxial layer；Formed sediment on the bottom of source electrode groove and side wall and be provided with gate oxide layers.
- 5. trench metal-oxide semiconductor according to claim 4, it is characterised in that source electrode groove passes through polysilicon Shallow lake sets full.
- 6. trench metal-oxide semiconductor according to claim 5, it is characterised in that source electrode groove and neighboring gates Form sediment the gate oxide layers being provided with the bottom condition of equivalent thickness of source electrode groove for the top of N-type epitaxial layer between groove.
- 7. trench metal-oxide semiconductor according to claim 5, it is characterised in that the top source of N-type epitaxial layer Inject to form Channeling implantation layer by impurity between pole groove and gate trench, be provided with inside Channeling implantation layer and injected by source region And the source region implanted layer that impurity activation is formed.
- 8. trench metal-oxide semiconductor according to claim 7, it is characterised in that gate trench both sides are provided with and connect Contact hole, the polysilicon layer of source electrode trench interiors is interior to be provided with contact hole, and the bottom of contact hole located at Channeling implantation layer and passes through source region Implanted layer.
- 9. trench metal-oxide semiconductor according to claim 8, it is characterised in that the first gold medal of deposit in contact hole Category, and formed sediment above the first metal and set the second metal, being formed sediment between second metal layer and gate oxide layers is provided with dielectric layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876449A (en) * | 2017-04-12 | 2017-06-20 | 上海格瑞宝电子有限公司 | A kind of trench metal-oxide semiconductor and preparation method thereof |
| CN110223959A (en) * | 2019-07-02 | 2019-09-10 | 上海格瑞宝电子有限公司 | The Metal Oxide Semiconductor Field Effect Transistor and preparation method thereof of depth groove |
-
2017
- 2017-04-12 CN CN201720377915.3U patent/CN206697482U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876449A (en) * | 2017-04-12 | 2017-06-20 | 上海格瑞宝电子有限公司 | A kind of trench metal-oxide semiconductor and preparation method thereof |
| CN110223959A (en) * | 2019-07-02 | 2019-09-10 | 上海格瑞宝电子有限公司 | The Metal Oxide Semiconductor Field Effect Transistor and preparation method thereof of depth groove |
| CN110223959B (en) * | 2019-07-02 | 2024-01-23 | 上海格瑞宝电子有限公司 | Metal oxide semiconductor field effect transistor with deep and shallow grooves and preparation method thereof |
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