CN110071043A - A kind of preparation method of power semiconductor - Google Patents

Abstract

The invention relates to a preparation method of a power semiconductor device. The second conductive type body region of the terminal region cooperates with the substrate terminal trench to form a required terminal region structure, and a mask plate is not required to obtain the second conductive type body region. Compared with the existing process, the trench type power semiconductor device can use less mask when preparing the front structure, which effectively reduces the preparation cost of the power semiconductor device. Since the substrate barrier layer and the cell insulating oxide layer have different etching selectivity ratios, when the substrate barrier layer is removed, over-etching of the cell insulating oxide layer is avoided, thereby ensuring the reliability of the obtained power semiconductor device. The presence of the second conductive type base region of the substrate in the active region ensures the breakdown characteristics of the terminal region of the prepared power semiconductor device and the conduction characteristics of the active region. The entire process is compatible with existing processes and is safe and reliable.

Description

A kind of preparation method of power semiconductor device

technical field

The invention relates to a preparation method, in particular to a preparation method of a power semiconductor device, and belongs to the technical field of the preparation technology of power semiconductor devices.

Background technique

At present, power semiconductor devices are developing rapidly. On the one hand, the technology of IGBT and VDMOS is constantly innovating to achieve excellent performance; on the other hand, low cost has also become the pursuit goal of power semiconductor development. In the processing cost of power semiconductors, the cost of the mask and the corresponding photolithography process are often the main factors, so reducing the number of masks becomes the key to reducing the cost of the device. In most cases, there is often a trade-off between high-performance devices and low cost, unless new devices, process methods, etc. appear.

As shown in FIG. 1 to FIG. 11 , the manufacturing process steps of the front surface structure of the existing trench type power semiconductor device are shown. Specifically,

As shown in FIG. 1 , an N-type semiconductor substrate 1 is provided, and a first photoresist layer 2 of the substrate is coated on the front surface of the semiconductor substrate 1 , and the first photoresist layer 2 of the substrate is subjected to Photolithography is performed to obtain the first photoresist layer window 4 of the substrate passing through the first photoresist layer 2 of the substrate.

As shown in FIG. 2 , the front surface of the semiconductor substrate 1 is implanted by using the first photoresist layer 2 of the substrate and the window 4 of the first photoresist layer of the substrate to obtain a terminal ring 5 located in the terminal area. The window 4 of the first photoresist layer 2 of the substrate corresponds to the window 4 of the first photoresist layer of the substrate.

As shown in FIG. 3 , the first photoresist layer 2 of the substrate is removed, and a field oxide layer 7 and a second photoresist layer 8 of the substrate covering the field oxide layer 7 are arranged on the front surface of the semiconductor substrate 1 , The second photoresist layer 8 of the substrate is photoetched by using the second mask plate 6 of the substrate, and the field oxide layer 7 corresponding to the active region is etched by the second photoresist layer 8 of the substrate after photoetching, so as to A field oxide layer 7 on the termination region can be obtained;

As shown in FIG. 4 , the second photoresist layer 8 of the substrate is removed, and the third photoresist layer 9 of the substrate is coated on the active area of the semiconductor substrate 1 and the field oxide layer 7, and the third mask of the substrate is used. 10. Perform photolithography on the third photoresist layer 9 of the substrate to obtain the third photoresist layer window 12 of the substrate passing through the third photoresist layer 9 of the substrate; use the third photoresist layer 9 of the substrate and the third photoresist layer of the substrate The resist layer window 12 is used to etch the semiconductor substrate 1 in the active region to obtain the active region trench 11 in the active region.

As shown in FIG. 5 , the third photoresist layer 9 of the substrate is removed, an insulating gate oxide layer 13 is grown in the active region trench 11 , and an insulating gate oxide layer 13 is grown in the active region trench 11 The trench conductive polysilicon 14 is filled and the excess polysilicon is etched away.

As shown in FIG. 6 , P-type ions are implanted and propelled above the semiconductor substrate 1 to obtain a substrate P-type base region 15 located in the active region. At the same time, the field oxide layer 7 on the semiconductor substrate 1 can be used to The P-type ions are blocked from being implanted into the termination region, and the P-type base region 15 of the substrate is located above the bottom of the trench 11 in the active region.

As shown in FIG. 7 , N-type ions are implanted and propelled above the semiconductor substrate 1 to obtain a substrate N+ active layer 16 located in the active region, and the substrate N+ active layer 16 is located on the substrate P-type Above the base region 15, the N-type ion implantation into the termination region can be blocked by the field oxide layer 7.

As shown in FIG. 8 , a dielectric layer is deposited on the front surface of the above-mentioned semiconductor substrate 1, and the dielectric layer covers the substrate N+ active layer 16 and the field oxide layer 7 to obtain a substrate dielectric layer 17. The substrate dielectric layer 17 covers the notch of the trench 11 in the active region; coat the fourth substrate photoresist layer 18 on the substrate dielectric layer 17, and use the substrate fourth mask 19 to perform photolithography on the substrate fourth photoresist layer 18 to A window 20 of the fourth photoresist layer of the substrate passing through the fourth photoresist layer 18 of the substrate is obtained, and the window 20 of the fourth photoresist layer of the substrate is located above the active region.

As shown in FIG. 9 , the substrate dielectric layer 17 and the substrate N+ active layer 16 are etched by using the substrate fourth photoresist layer 18 and the substrate fourth photoresist layer window 20 to obtain the substrate fourth photoresist The substrate contact holes 24 corresponding to the layer windows 20 pass through the substrate dielectric layer 17 , and the substrate N+ source regions 23 are obtained on both sides of the active region trench 11 .

As shown in FIG. 10 , the fourth photoresist layer 18 of the substrate is removed, and metal deposition is performed on the front surface of the semiconductor substrate 1 to obtain a front metal layer, which covers the substrate dielectric layer 17 and is filled in inside the substrate contact hole 24 .

The fifth photoresist layer 26 of the substrate is coated on the front metal layer, and the fifth photoresist layer 26 of the substrate is photoetched by using the fifth mask 27 of the substrate, so as to obtain a substrate penetrating the fifth photoresist layer 26 of the substrate The fifth photoresist layer window 28, the fifth photoresist layer window 28 of the substrate is located above the termination area. The front metal layer of the substrate is etched by using the fifth photoresist layer 26 of the substrate and the window 28 of the fifth photoresist layer of the substrate to obtain the metal separation hole 22 of the substrate, and the front metal layer is separated by the metal separation hole 22 to form the substrate terminal The front metal 25 and the front metal 21 of the substrate cell.

As shown in FIG. 11 , a passivation layer is deposited above the front surface of the semiconductor substrate 1 to obtain a front surface passivation layer 29 of the substrate, and the front surface passivation layer 29 covers the front metal layer 25 and the cell of the substrate terminal. On the front metal layer 21 , and the substrate front passivation layer 29 is filled in the substrate metal separation hole 22 .

The sixth photoresist layer 30 of the substrate is coated on the front passivation layer 29 of the substrate, and the sixth photoresist layer 30 of the substrate is photoetched by using the sixth mask plate 31 of the substrate, and the sixth photoresist layer 30 of the substrate after photoetching is used. The resist layer 30 etches the front surface passivation layer 29 of the substrate to obtain a substrate source pad hole 32 penetrating the front surface passivation layer 29 of the substrate. exposed.

After removing the sixth photoresist layer 30 of the substrate, the processing steps of the source pad can be performed; in addition, a backside process needs to be performed on the backside of the semiconductor substrate 1, and the required MOSFET device or IGBT device can be obtained according to the difference of the backside process. , the backside process can adopt the existing common process steps, which are well known to those skilled in the art, and will not be repeated here.

To sum up, for a MOSFET device or an IGBT device, at least six masks need to be provided during the front-side process to use the corresponding mask to perform the corresponding photolithography process steps, so that the prepared MOSFET device or IGBT device can be prepared. higher cost.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a preparation method of a power semiconductor device, which is compatible with the existing technology, reduces the preparation cost of the power semiconductor device, and is safe and reliable.

According to the technical solution provided by the present invention, a preparation method of a power semiconductor device, the preparation method comprises the following steps:

Step 1. Provide a semiconductor substrate with a first conductivity type, and perform trench etching on the semiconductor substrate to obtain a desired substrate trench, where the substrate trench includes a liner located in the active region. a bottom cell trench and a substrate termination trench located in the termination region;

Step 2, performing an oxide layer growth process in the above-mentioned substrate trench to obtain a cell insulating oxide layer covering the inner wall of the substrate cell trench and a terminal insulating oxide layer covering the inner wall of the substrate terminal trench; The substrate cell trench of the cell insulating oxide layer is filled with conductive polysilicon of the substrate cell, and at the same time, the substrate terminal conductive polysilicon is filled in the substrate terminal trench where the terminal insulating oxide layer is grown;

Step 3. Perform implantation and advancement of impurity ions of the second conductivity type on the front surface of the semiconductor substrate to obtain a second conductivity type body region traversing the upper part of the semiconductor substrate, and the second conductivity type body region is located in the substrate. Above the bottom of the bottom groove;

Step 4, depositing a barrier material layer on the front side of the above-mentioned semiconductor substrate, and coating photoresist on the barrier material layer, and using the second mask of the substrate to perform photolithography on the photoresist on the barrier material layer , in order to obtain the second photoresist layer of the substrate located above the terminal area of the semiconductor substrate, and use the second photoresist layer of the substrate to etch the barrier material layer to obtain the second photoresist layer located directly below the substrate The substrate barrier layer;

Step 5. Using the second photoresist layer of the substrate and the barrier layer of the substrate to shield the terminal area of the semiconductor substrate, implant the second conductivity type impurity ions into the active area of the semiconductor substrate, and remove the substrate after the implantation is completed. For the second photoresist layer, after high temperature annealing, a doped region of the second conductivity type of the substrate can be obtained in the active region of the semiconductor substrate;

Step 6, using the substrate barrier layer to implant the first conductivity type impurity ions into the active region of the semiconductor substrate, after high temperature annealing, the first conductivity type source dopant of the substrate can be obtained in the active region of the semiconductor substrate The impurity region and the second conductive type base region of the substrate, the first conductive type source doping region of the substrate is located above the second conductive type base region of the substrate, the first conductive type source doping region of the substrate, the first conductive type source doping region of the substrate The two-conductivity-type base region is in contact with the outer wall of the corresponding substrate cell trench;

In step 7, a dielectric layer is deposited on the semiconductor substrate to obtain a substrate dielectric layer covering the front surface of the semiconductor substrate, and the third photoresist layer of the substrate is obtained by coating the substrate dielectric layer. The mask plate performs photolithography on the third photoresist layer of the substrate to obtain a window of the third photoresist layer of the substrate passing through the third photoresist layer of the substrate, and the window of the third photoresist layer of the substrate is located in the semiconductor above the active region of the substrate;

Step 8, using the third photoresist layer of the substrate and the window of the third photoresist layer of the substrate to etch the substrate dielectric layer, so as to obtain the penetrating substrate dielectric layer and the first conductive type source doped region of the substrate. A dielectric contact hole, the first conductive type source doped region of the substrate can form a required first conductive type source region of the substrate through the dielectric contact hole;

Step 9, removing the third photoresist layer of the substrate, and depositing a metal layer on the substrate dielectric layer to obtain a substrate front metal layer, the substrate front metal layer covering the substrate dielectric layer and Filled in the dielectric contact hole, the front metal layer of the substrate filled in the dielectric contact hole is in ohmic contact with the source region of the first conductivity type of the substrate and the base region of the second conductivity type of the substrate;

Step 10: Coat the fourth photoresist layer of the substrate on the metal layer on the front side of the substrate, and use the fourth mask of the substrate to perform photolithography on the fourth photoresist layer of the substrate, so as to obtain the fourth photoresist penetrating the substrate. The fourth photoresist layer window of the substrate of the resist layer is used to etch the metal layer on the front side of the substrate by using the fourth photoresist layer of the substrate and the window of the fourth photoresist layer of the substrate, so as to obtain a metal layer through the front side of the substrate The substrate metal separation hole of the layer, and the substrate metal separation hole can be used to separate the substrate front metal layer to obtain the substrate cell front metal layer and the substrate terminal front metal layer, and the substrate cell front metal layer and the lining the bottom first conductive type source region and the substrate second conductive type base region are in ohmic contact;

Step 11, removing the fourth photoresist layer of the substrate and depositing a passivation layer, so as to obtain a front-side passivation layer covering the front-side metal layer of the substrate cell and the front-side metal layer of the substrate terminal, and all The front passivation layer of the substrate is also filled in the metal separation hole of the substrate;

Step 12: Coat the fifth photoresist layer of the substrate on the front passivation layer of the substrate, use the fifth mask layer of the substrate to perform photolithography on the fifth photoresist layer of the substrate, and use the photoetched photoresist layer. The fifth photoresist layer of the substrate etches the front passivation layer of the substrate to obtain a substrate source pad hole penetrating the front passivation layer of the substrate. The front metal layer of the substrate cell corresponding to the substrate source pad hole is exposed;

Step 13, removing the above-mentioned fifth photoresist layer of the substrate, and performing a required backside process on the backside of the semiconductor substrate.

In step 1, the first photoresist layer of the substrate is coated on the front side of the semiconductor substrate, and the first photoresist layer of the substrate is photoetched by using the first mask of the substrate, so as to obtain the first photoresist layer through the substrate. The first photoresist layer window of the substrate of the photoresist layer, after the front surface of the semiconductor substrate is etched by using the first photoresist layer of the substrate and the window of the first photoresist layer of the substrate, the required lining can be obtained. Bottom groove.

The substrate barrier layer includes a polysilicon layer, a silicon dioxide layer or a silicon nitride layer.

The material of the semiconductor substrate includes silicon.

In step 2, the cell insulating oxide layer and the terminal insulating oxide layer are the same process step layer, and the cell insulating oxide layer and the terminal insulating oxide layer are silicon dioxide layers.

The doping concentration of the second conductive type base region of the substrate is greater than the doping concentration of the second conductive type body region.

When the substrate dielectric layer is a silicon dioxide layer and the substrate barrier layer is a polysilicon layer, the substrate barrier layer needs to be removed from the semiconductor substrate before the dielectric layer is deposited.

In both the "first conductivity type" and the "second conductivity type", for N-type power semiconductor devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power semiconductor devices, the first conductivity type refers to N-type. A conductivity type and a second conductivity type refer to types that are just opposite to N-type power semiconductor devices.

The advantages of the present invention: a substrate terminal trench is arranged in the terminal area of the semiconductor substrate, a terminal insulating oxide layer and a substrate terminal conductive polysilicon are arranged in the substrate terminal trench, and the second conductivity type is performed on the front side of the semiconductor substrate. Impurity ion implantation can obtain the second conductivity type body region, and the second conductivity type body region of the terminal region cooperates with the substrate terminal trench to form the required terminal region structure, and the mask plate is not required to obtain the second conductivity type body region Compared with the existing process, the trench type power semiconductor device can use less mask when preparing the front structure, which effectively reduces the preparation cost of the power semiconductor device.

The terminal area of the semiconductor substrate is shielded by the substrate barrier layer and the second photoresist layer of the substrate, the second conductivity type impurity ions are implanted into the active area of the semiconductor substrate, and the second photoresist layer of the substrate is removed and After the activation, the doping region of the second conductivity type of the substrate can be obtained, the doping concentration and depth of the doping region of the second conductivity type of the substrate can meet the required requirements, and the required blocking voltage requirements can be achieved, which is consistent with the current requirements. Compared with other processes, there is no need to use a mask, which can further reduce the cost. In the subsequent process, the second conductive type base region of the substrate can be obtained by using the second conductive type doped region of the substrate and the second conductive type body region in the active region, and the substrate barrier layer is used to terminate the semiconductor substrate. After shielding the region, the first conductive type source doped region of the substrate can be obtained in the active region of the semiconductor substrate, and the first conductive type source region of the substrate can be obtained from the first conductive type source doped region of the substrate. Since the substrate barrier layer and the cell insulating oxide layer have different etching selectivity ratios, when the substrate barrier layer is removed, over-etching of the cell insulating oxide layer is avoided, thereby ensuring the reliability of the obtained power semiconductor device.

The second conductive type base region of the substrate exists in the active region, which can realize the adjustment of the doping concentration of the second conductive type in the active region, and ensure the breakdown characteristics of the terminal region of the prepared power semiconductor device and the active region. The conduction characteristics of the whole process are compatible with the existing process, which is safe and reliable.

Description of drawings

1 to 11 are cross-sectional views of the specific manufacturing process steps of the conventional power semiconductor device, wherein

FIG. 1 is a cross-sectional view after obtaining a first photoresist layer window of a substrate.

FIG. 2 is a cross-sectional view after obtaining the terminal ring.

FIG. 3 is a schematic diagram after etching the field oxide layer of the active region.

FIG. 4 is a cross-sectional view after obtaining trenches in the active region.

FIG. 5 is a cross-sectional view after obtaining trench conductive polysilicon.

FIG. 6 is a cross-sectional view after obtaining the P-type base region of the substrate.

FIG. 7 is a cross-sectional view after obtaining the N+ active layer of the substrate.

FIG. 8 is a cross-sectional view after obtaining a fourth photoresist layer window of the substrate.

FIG. 9 is a cross-sectional view after obtaining a substrate contact hole.

FIG. 10 is a cross-sectional view after obtaining the metal separation holes of the substrate.

FIG. 11 is a cross-sectional view after obtaining a substrate source pad hole.

12 to 21 are cross-sectional views of the specific implementation process steps of the present invention, wherein

FIG. 12 is a cross-sectional view of the substrate trench obtained by the present invention.

FIG. 13 is a cross-sectional view of the substrate cell conductive polysilicon and the substrate terminal conductive polysilicon obtained by the present invention.

FIG. 14 is a cross-sectional view after the P-type base region is obtained in the present invention.

FIG. 15 is a cross-sectional view of the present invention after obtaining the second photoresist layer of the substrate.

16 is a cross-sectional view of the present invention after obtaining a P-type doped region of the substrate.

FIG. 17 is a cross-sectional view of the substrate N+ source doped region obtained by the present invention.

FIG. 18 is a cross-sectional view of the present invention after obtaining the window of the third photoresist layer of the substrate.

19 is a cross-sectional view of the present invention after obtaining a dielectric contact hole.

FIG. 20 is a cross-sectional view of the substrate metal separation hole obtained in the present invention.

21 is a cross-sectional view of the present invention after obtaining the substrate source pad hole.

Description of reference numerals: 1-semiconductor substrate, 2-substrate first photoresist layer, 3-substrate first mask, 4-substrate first photoresist layer window, 5-terminal ring, 6-substrate second mask Template, 7-field oxide layer, 8-substrate second photoresist layer, 9-substrate third photoresist layer, 10-substrate third mask, 11-active area trench, 12-substrate third photoresist Resist layer window, 13-insulation gate oxide layer, 14-trench conductive polysilicon, 15-substrate P-type base region, 16-substrate N+ active layer, 17-substrate dielectric layer, 18-substrate fourth photoresist layer , 19-substrate fourth mask, 20-substrate fourth photoresist layer window, 21-substrate cell front metal, 22-substrate metal separation hole, 23-substrate N+ source region, 24-substrate contact hole, 25- Front side metal of substrate terminal, 26-substrate fifth photoresist layer, 27-substrate fifth mask, 28-substrate fifth photoresist layer window, 29-substrate front passivation layer, 30-substrate sixth photoresist layer, 31-substrate sixth mask, 32-substrate source pad hole, 33-substrate first photoresist layer, 34-substrate first mask, 35-substrate terminal trench, 36-liner Bottom cell trench, 37-terminal insulating oxide layer, 38-substrate terminal conductive polysilicon, 39-P-type body region, 40-substrate barrier layer, 41-substrate second photoresist layer, 42-substrate The second mask, 43-substrate N+ source doping region, 44-substrate dielectric layer, 45-substrate third photoresist layer, 46-substrate third mask, 47-substrate third lithography Adhesive layer window, 48-dielectric contact hole, 49-substrate N+ source region, 50-substrate fourth photoresist layer, 51-substrate terminal front metal layer, 52-substrate fourth mask, 53-liner Bottom cell front metal layer, 54-substrate metal separation hole, 55-substrate fifth photoresist layer, 56-substrate fifth mask, 57-substrate source pad hole, 58-semiconductor substrate , 59-substrate cell conductive polysilicon, 60-cell insulating oxide layer, 61-substrate front passivation layer, 62-substrate P-type base doped region and 63-substrate P-type base region.

Detailed ways

The present invention will be further described below with reference to the specific drawings and embodiments.

As shown in FIGS. 12 to 21 : in order to prepare a low-cost trench-type power semiconductor device, an N-type power semiconductor device is used to illustrate the specific preparation process steps of the present invention. Specifically, the preparation method includes the following steps :

Step 1. Provide an N-type semiconductor substrate 58, and perform trench etching on the semiconductor substrate 58 to obtain a desired substrate trench, and the substrate trench includes the substrate located in the active region cell trenches 36 and substrate termination trenches 35 in the termination region;

Specifically, the material of the semiconductor substrate 58 includes silicon. Of course, the semiconductor substrate 58 can also use other common semiconductor materials, and the specific type can be selected according to needs, which is well known to those skilled in the art, and will not be repeated here. During specific implementation, the first substrate photoresist layer 33 is coated on the front side of the semiconductor substrate 58, and the substrate first photoresist layer 33 is photoetched by using the substrate first mask 34, so as to obtain through The substrate first photoresist layer window of the substrate first photoresist layer 33 is used to etch the front surface of the semiconductor substrate by using the substrate first photoresist layer 33 and the substrate first photoresist layer window, The desired substrate trench can be obtained, as shown in FIG. 12 .

In the embodiment of the present invention, the substrate cell trench 36 is located in the active area of the semiconductor substrate 58 , the substrate terminal trench 35 is located in the terminal area of the semiconductor substrate 58 , and the active area is generally located in the semiconductor substrate 58 . The central area and the terminal area are located in the outer ring of the active area, and the relative positional relationship between the active area and the terminal area is set by those skilled in the art as needed, which is well known to those skilled in the art, and will not be repeated here. . The substrate cell trenches 36 and the substrate terminal trenches 35 have the same depth. The depths of the substrate cell trenches 36 and the substrate terminal trenches 35 are both smaller than the thickness of the semiconductor substrate 58 . The substrate cell trenches have the same depth. 36. The substrate termination trench 35 extends vertically downward from the front surface of the semiconductor substrate 58.

Step 2, performing an oxide layer growth process in the above-mentioned substrate trench to obtain a cell insulating oxide layer 60 covering the inner wall of the substrate cell trench 36 and a terminal insulating oxide layer 37 covering the inner wall of the substrate terminal trench 35; The substrate cell conductive polysilicon 59 is filled in the substrate cell trench 36 on which the cell insulating oxide layer 60 is grown, and the substrate terminal conductive polysilicon 59 is filled in the substrate terminal trench 35 where the terminal insulating oxide layer 37 is grown. polysilicon 38;

Specifically, the cell insulating oxide layer 60 and the terminal insulating oxide layer 37 are prepared by a thermal oxidation process. The cell insulating oxide layer 60 covers the sidewalls and bottom walls of the cell trench 36 in the substrate, and the terminal insulating oxide layer 37 covers the substrate. The sidewalls and bottom walls of the bottom terminal trench 35 , the cell insulating oxide layer 60 and the terminal insulating oxide layer 37 are generally silicon dioxide layers. The substrate cell conductive polysilicon 59 is filled in the substrate cell trench 36, and the substrate cell conductive polysilicon 59 is insulated from the semiconductor substrate 58 by the cell insulating oxide layer 60, and the substrate terminal conductive polysilicon 38 is insulated by the terminal The oxide layer 37 is insulated from the semiconductor substrate 58 as shown in FIG. 12 . In specific implementation, before the thermal oxidation process is performed, the substrate first photoresist layer 33 on the front surface of the semiconductor substrate 58 needs to be removed, and the specific process of removing the substrate first photoresist layer 33 is for those skilled in the art known. In addition, the cell insulating oxide layer 60 and the terminal insulating oxide layer 37 can be prepared by the thermal oxidation process commonly used in the technical field, and the process of filling the substrate cell conductive polysilicon 59 in the substrate cell trench 36 is as follows. It is well known to those skilled in the art and will not be repeated here.

Step 3. Perform the implantation and advancement of P-type impurity ions on the front surface of the semiconductor substrate 58 to obtain a P-type body region 39 that traverses the upper part of the semiconductor substrate 58, and the P-type body region 39 is located in the substrate trench above the bottom of the groove;

Specifically, the implantation and advancement of P-type impurity ions can be performed by using the existing common process conditions. Generally, an activation step is required after ion implantation. During activation, the temperature of high-temperature annealing is generally above 800°C, and the specific temperature The conditions can be selected according to needs, which are well known to those skilled in the art, and will not be repeated here. In addition, the type of the P-type impurity ions can be selected as required, and details are not repeated here. The obtained P-type body region 39 covers the upper part of the semiconductor substrate 58 , that is, the P-type body region 39 traverses the upper part of the semiconductor substrate 58 , and the P-type body region 39 is located in the corresponding active region of the semiconductor substrate 58 and in the terminal area. The upper surface of the P-type body region 39 corresponds to the front surface of the semiconductor substrate 58 , and the P-type body region 39 is located above the bottom of the trench in the substrate, as shown in FIG. 14 .

Step 4, depositing a barrier material layer on the front surface of the above-mentioned semiconductor substrate 58, and coating photoresist on the barrier material layer, and using the second reticle 42 of the substrate to carry out the photoresist on the barrier material layer. Photolithography is used to obtain the second photoresist layer 41 of the substrate located above the terminal area of the semiconductor substrate 58, and the barrier material layer is etched by using the second photoresist layer 41 of the substrate to obtain the second photoresist layer 41 located on the substrate. The substrate barrier layer 40 directly under the resist layer 41;

Specifically, the blocking material layer includes a polysilicon layer, a silicon dioxide layer or a silicon nitride layer. When a material other than a silicon dioxide layer is used for the blocking material layer, the blocking material layer and the cell insulating oxide layer 60 have different etching options. That is, when the barrier material layer is a polysilicon layer or a silicon nitride layer, the barrier material layer and the cell insulating oxide layer 60 have different etching selectivity ratios, and when the barrier material layer is a silicon dioxide layer, the barrier material layer It has the same etching selectivity ratio as the cell insulating oxide layer 60 .

A barrier material layer can be deposited on the front surface of the semiconductor substrate 58 by using technical means commonly used in the technical field. After the barrier material layer is obtained, a photoresist layer is coated on the barrier material layer, and a second mask of the substrate is used. After the photoresist layer is etched by the stencil 42, the second photoresist layer 41 of the substrate can be obtained, wherein the second photoresist layer 41 of the substrate is located above the terminal area of the semiconductor substrate 58, that is, the second photoresist layer of the substrate is located above the terminal area of the semiconductor substrate 58. The resist layer 41 does not cover the active region of the semiconductor substrate 58 . After etching the barrier material through the second photoresist layer 41 of the substrate, the barrier substrate 40 can be obtained, that is, the barrier substrate 40 is located directly under the second photoresist layer 41 of the substrate, and the barrier layer 40 is located directly under the second photoresist layer 41 of the substrate. 40 also does not cover and shade the active region of the semiconductor substrate 58 , as shown in FIG. 15 .

Step 5. Use the second photoresist layer 41 of the substrate and the substrate barrier layer 40 to shield the terminal area of the semiconductor substrate 58, and implant the P-type impurity ions into the active area of the semiconductor substrate 58, and remove after the implantation is completed. For the second photoresist layer 40 of the substrate, after high temperature annealing, the substrate P-type doped region 62 can be obtained in the active region of the semiconductor substrate 58;

Specifically, since the second photoresist layer 41 of the substrate and the substrate barrier layer 40 can shield the terminal region of the semiconductor substrate 58, P-type impurity ion implantation can be performed on the active region of the semiconductor substrate 58. Specifically, The process of implanting the P-type impurity ions and the types of the P-type impurity ions are well known to those skilled in the art, and will not be repeated here. After the implantation, the second photoresist layer 40 of the substrate needs to be removed by the technical means commonly used in the technical field. After the removal, and the high temperature annealing process step is performed, the substrate P-type doped region 62 can be obtained, and the high temperature annealing process can be performed. The temperature is generally above 800 ℃, and the specific temperature can be selected according to the needs. In the embodiment of the present invention, the doping concentration of the P-type doping region 62 of the substrate is greater than the doping concentration of the P-type body region 39, so that the doping concentration and depth of the P-type doping region 62 of the substrate can meet the requirements. As a result, high blocking voltage can be achieved, and compared with the traditional process, there is no additional mask added in this step, as shown in Figure 16.

Step 6. Use the substrate barrier layer 40 to implant N-type impurity ions into the active region of the semiconductor substrate 58. After high temperature annealing, the substrate N+ source doped region can be obtained in the active region of the semiconductor substrate 58. 43 and the substrate P-type base region 63, the substrate N+ source doped region 43 is located above the substrate P-type base region 62, the substrate N+ source doped region 43, the substrate P-type base region 62 and the corresponding substrate The outer wall of the bottom cell trench 36 is in contact;

Specifically, when the terminal region of the semiconductor substrate 58 is shielded by the substrate barrier layer 40, N-type impurity ion implantation can be performed on the active region of the semiconductor substrate 58, and the specific process of performing the N-type impurity ion implantation is the technology It is well known to those skilled in the art and will not be repeated here. The temperature of the high-temperature annealing is generally 800° C., after the high-temperature annealing, the N+ source doped region 43 of the substrate can be activated. In addition, after the substrate N+ source doping region 43 is obtained, the substrate P-type base region 63 can be obtained by using the substrate P-type doping region 62 and the P-type body region 39 in the active region. The type base region 62 is located below the substrate N+ source doped region 43 .

It can be seen from the above description that after the substrate N+ source doping region 43 is obtained, the substrate P-type base region 63 can be obtained from the substrate P-type doping region 62 and the P-type body region 39 in the active region, so that the substrate P-type base region 63 can be obtained. The doping concentration and depth of the P-type base region 63 meet the required requirements to achieve high blocking voltage. The specific principle of achieving high blocking voltage is well known to those skilled in the art, and will not be repeated here. The substrate N+ source doped region 43 and the substrate P-type base region 62 are in contact with the outer walls of the corresponding substrate cell trenches 36 , as shown in FIG. 17 .

In the embodiment of the present invention, it can be seen from the above description that when the substrate barrier layer 40 is made of polysilicon or silicon nitride, the material with a different etching selection ratio than the cell insulating oxide layer 60 is used. Therefore, when the barrier material layer is etched to form the substrate When the blocking layer 40 is used, the over-etching of the insulating oxide layer 60 of the cell can be prevented, the process control is relatively easy, and the reliability of the obtained power semiconductor device is ensured. However, when the substrate barrier layer 40 adopts a silicon dioxide layer, the over-etching of the cell insulating oxide layer 60 can also be prevented by precisely controlling the etching process, but the process is relatively difficult, and the specific etching process is selected as It is well known to those skilled in the art and will not be repeated here.

Step 7, and perform dielectric layer deposition on the semiconductor substrate 58 to obtain the substrate dielectric layer 44 covering the front surface of the semiconductor substrate 58, and coat the substrate dielectric layer 44 to obtain the substrate third photoresist layer 45 , the third photoresist layer 45 of the substrate is subjected to photolithography using the third reticle 46 of the substrate to obtain a window 47 of the third photoresist layer of the substrate penetrating the third photoresist layer 45 of the substrate. The bottom third photoresist layer window 47 is located above the active region of the semiconductor substrate 58;

Specifically, the substrate barrier layer 40 can be removed from the semiconductor substrate 58 by using technical means commonly used in the technical field. The specific process of removing the substrate barrier layer 40 is well known to those skilled in the art and will not be repeated here. After the substrate barrier layer 40 is removed, a dielectric layer is deposited on the semiconductor substrate 58 to obtain a substrate dielectric layer 44 covering the front surface of the semiconductor substrate 58 , and the substrate dielectric layer 44 may be a silicon dioxide layer. After the substrate dielectric layer 44 is obtained, the substrate third photoresist layer 45 is obtained by coating the substrate dielectric layer 44, and the substrate third photoresist layer 45 is photolithographically performed by using the substrate third mask 46 , the window 47 of the third photoresist layer of the substrate is obtained, the window 47 of the third photoresist layer of the substrate passes through the third photoresist layer 45 of the substrate, and the window 47 of the third photoresist layer of the substrate is located in the active directly above the area, as shown in Figure 18.

As can be seen from the above description, the substrate dielectric layer 44 is generally a silicon dioxide layer, and when the substrate barrier layer 40 is a polysilicon layer, the substrate barrier layer 40 needs to be removed from the semiconductor substrate 58 before the dielectric layer is deposited. remove. When the substrate barrier layer 40 is a silicon dioxide layer or silicon nitride, the substrate barrier layer 40 does not need to be removed from the semiconductor substrate 58 when the dielectric layer is deposited.

Step 8: Etching the substrate dielectric layer 44 by using the third substrate photoresist layer 45 and the substrate third photoresist layer window 47 to obtain the through-substrate dielectric layer 44 and the substrate N+ source doping region The dielectric contact hole 48 of 43, the substrate N+ source doped region 43 can form the required substrate N+ source region 49 through the dielectric contact hole 48;

Specifically, the substrate dielectric layer 44 is etched by using the third substrate photoresist layer 45 and the substrate third photoresist layer window 47 to obtain a medium corresponding to the substrate third photoresist layer window 47 The contact hole 48 , the dielectric contact hole 48 penetrates through the substrate dielectric layer 44 and the substrate N+ source doped region 43 . On the cross section of the power semiconductor device, after the dielectric contact hole 48 penetrates the substrate N+ source doped region 43, the substrate N+ source region 49 located on both sides of the substrate cell trench 36 is obtained, and the substrate N+ source region 49 is obtained. Contacts are made with the outer sidewalls of the corresponding adjacent substrate cell trenches 36 as shown in FIG. 19 .

Step 9. Remove the third photoresist layer 45 of the above-mentioned substrate, and deposit a metal layer on the above-mentioned substrate dielectric layer 44 to obtain a front-side metal layer of the substrate, and the front-side metal layer of the substrate covers the substrate dielectric layer 44 and filled in the dielectric contact hole 48, the substrate front metal layer filled in the dielectric contact hole 48 is in ohmic contact with the substrate N+ source region 49 and the substrate P-type base region 63;

Specifically, the third photoresist layer 45 of the substrate is removed by using technical means commonly used in the technical field, and then the metal layer is deposited by using technical means commonly used in the technical field. The metal layer can be made of commonly used materials. A selection is required and will not be repeated here. The substrate front metal layer is covered on the substrate dielectric layer 44 and filled in the dielectric contact holes 48. After the substrate front metal layer is filled in the dielectric contact holes 48, the substrate front metal layer can interact with the substrate N+ source region 49, The substrate P-type base region 62 is in ohmic contact.

Step 10: Coat the fourth substrate photoresist layer 50 on the above-mentioned substrate front metal layer, and use the substrate fourth mask 52 to perform photolithography on the substrate fourth photoresist layer 50 to obtain a through substrate The fourth photoresist layer window of the substrate of the fourth photoresist layer 50 is used to etch the front metal layer of the substrate by using the fourth photoresist layer 50 of the substrate and the window of the fourth photoresist layer of the substrate to obtain The substrate metal separation hole 54 penetrates through the substrate front metal layer, and the substrate front metal layer can be separated by the substrate metal separation hole 54 to obtain the substrate cell front metal layer 53 and the substrate terminal front metal layer 51. The front metal layer 53 of the substrate cell is in ohmic contact with the substrate N+ source region 49 and the substrate P-type base region 63;

Specifically, the fourth substrate photoresist layer 50 is obtained by coating the metal layer on the front side of the substrate, and the fourth substrate photoresist layer 50 is photoetched by using the fourth substrate mask 52 to obtain the substrate fourth photoresist layer 50. Four photoresist layer windows, the fourth photoresist layer window of the substrate is located above the termination area. When the metal on the front side of the substrate is etched by using the fourth photoresist layer 50 of the substrate and the window of the fourth photoresist layer of the substrate, the substrate metal separation hole 54 above the terminal area can be obtained, and the substrate metal separation hole can be obtained. 54 penetrates through the front metal layer of the substrate, so that the front metal layer of the substrate can be separated to obtain the front metal layer 53 of the substrate cell and the front metal layer 51 of the substrate terminal. The front metal layer 53 of the substrate cell is separated and isolated, the front metal layer 51 of the substrate terminal is located in the terminal area, and the front metal layer 53 of the substrate cell is in ohmic contact with the substrate N+ source region 49 and the substrate P-type base region 62, such as shown in Figure 20.

Step 11, removing the above-mentioned fourth photoresist layer 50 of the substrate and depositing a passivation layer to obtain a front-side passivation layer covering the front-side metal layer 53 of the substrate cell and the front-side metal layer 51 of the substrate terminal 61, and the substrate front passivation layer 61 is also filled in the substrate metal separation hole 54;

Specifically, the fourth photoresist layer 50 of the substrate is removed by using technical means commonly used in the technical field, and a passivation layer is deposited by using technical means commonly used in the technical field. The material of the passivation layer can be silicon nitride, The substrate front passivation layer 61 covers the substrate cell front metal layer 53 and the substrate terminal front metal layer 51 . At the same time, the substrate front passivation layer 61 is also filled in the substrate metal separation holes 54 .

Step 12: Coating the fifth substrate photoresist layer 55 on the above-mentioned substrate front passivation layer 61, using the substrate fifth mask layer 56 to perform photolithography on the substrate fifth photoresist layer 55, and using The fifth photoresist layer 55 of the substrate after photoetching etches the front surface passivation layer 61 of the substrate to obtain the substrate source pad hole 57 penetrating the front surface passivation layer 61 of the substrate. The pad hole 57 can expose the front metal layer 53 of the substrate cell corresponding to the substrate source pad hole 57;

Specifically, the fifth photoresist layer 55 of the substrate is obtained by coating the front surface passivation layer 61 of the substrate, and the fifth photoresist layer 55 of the substrate is photoetched by using the fifth mask 56 of the substrate, and then the substrate is subjected to photolithography. The bottom front passivation layer 61 is etched to obtain the substrate source pad hole 57, the substrate source pad hole 57 passes through the substrate front passivation layer 61, and the substrate source pad hole 57 is located in the active region Above, through the substrate source pad hole 57, the front metal layer 53 of the substrate cell corresponding to the substrate source pad hole 57 can be exposed, as shown in FIG. The source electrode of the semiconductor device is formed after the layer 53 is drawn out, and the specific process of forming the source electrode is well known to those skilled in the art.

Step 13 , removing the above-mentioned fifth photoresist layer 55 of the substrate, and performing a required backside process on the backside of the semiconductor substrate 58 .

Specifically, the fifth photoresist layer 55 of the substrate is removed by technical means commonly used in the art to complete the required front-side process, and then the required back-side process is performed on the backside of the semiconductor substrate 58 as required. Different power semiconductor devices can be obtained, such as obtaining a MOSFET device or an IGBT device, and the specific backside process and backside structure are well known to those skilled in the art, and will not be repeated here.

It can be seen from the above description that the substrate terminal trench 35 is arranged in the terminal region of the semiconductor substrate 58, and the terminal insulating oxide layer 37 and the substrate terminal conductive polysilicon 38 are arranged in the substrate terminal trench 35. P-type impurity ion implantation is performed on the front side to obtain a P-type body region 39, and the P-type body region 39 of the terminal region cooperates with the substrate terminal trench 35 to form the required terminal region structure, and it is not necessary to obtain the P-type body region 39. Compared with the existing technology, the reticle can make the trench type power semiconductor device use one less reticle when preparing the front structure, which effectively reduces the manufacturing cost of the power semiconductor device.

The terminal region of the semiconductor substrate 58 is shielded by the substrate barrier layer 40 and the second photoresist layer 41 of the substrate, P-type impurity ions are implanted into the active region of the semiconductor substrate 58, and the second photoresist of the substrate is removed. After layer 41 is activated, the substrate P-type doping region 62 can be obtained, so that the doping concentration and depth of the substrate P-type doping region 62 can meet the required requirements, and the required blocking voltage requirements can be achieved. Compared with the existing process, there is no need to use a mask, which can further reduce the cost. In the subsequent process, the substrate P-type base region 63 can be obtained by using the substrate P-type doping region 62 and the P-type body region 39 in the active region, and the substrate barrier layer 40 can be used to form the termination region of the semiconductor substrate 58 After shielding, the substrate N+ source doped region 43 can be obtained in the active region of the semiconductor substrate 58 , and the substrate N+ source doped region 49 can be obtained from the substrate N+ source doped region 43 . Since the substrate barrier layer 40 and the cell insulating oxide layer 60 may have different etching selection ratios, when the substrate barrier layer 40 is removed, over-etching of the cell insulating oxide layer 60 is avoided, so as to ensure reliable power semiconductor devices. sex.

By using the substrate P-type base region 63 in the active region, the doping concentration of the P-type in the active region can be adjusted, which ensures the breakdown characteristics of the terminal region of the prepared power semiconductor device and the conduction of the active region. The whole process is compatible with the existing process, safe and reliable.

In the embodiment of the present invention, the P-type doping concentration in the active region should be higher to prevent the base region from breaking through under high voltage. When the P-type doping concentration in the active region is low, the high voltage The P-type base region 42 will be completely depleted, and the electric field will extend to the front metal layer 53 or the N+ source region 47 of the substrate cell filled in the dielectric contact hole 48 , so that punch-through occurs. When the substrate P-type base region 42 is prepared in the active region, the withstand voltage requirement of the active region can be met, that is, the breakdown characteristics of the terminal region of the prepared power semiconductor device and the conduction characteristics of the active region can be ensured . The specific conditions of the P-type doping concentration in the active region, that is, the process and method of adjusting the P-type doping concentration in the active region are well known to those skilled in the art, and will not be repeated here.

Claims (7)

1. a kind of preparation method of power semiconductor, characterized in that the preparation method includes the following steps:

Step 1 provides the semiconductor substrate with the first conduction type, and carries out etching groove to the semiconductor substrate, with Required substrate trenches are obtained, the substrate trenches include the lining positioned at the substrate cellular groove of active area and positioned at termination environment Bottom terminal trenches；

Step 2 carries out oxide layer growth technique in above-mentioned substrate trenches, to obtain the cellular of covering substrate cellular trench wall Insulating oxide and the terminating insulation oxide layer for covering substrate terminal trench wall；There is the lining of cellular insulating oxide in growth Substrate cellular conductive polycrystalline silicon is filled in the cellular groove of bottom, meanwhile, there is the substrate terminal groove of terminating insulation oxide layer in growth Interior filling substrate terminal conductive polycrystalline silicon；

Step 3, the injection and propulsion that the second conductive type impurity ion is carried out on the front of above-mentioned semiconductor substrate, to obtain The second conductivity type body region of semiconductor substrate internal upper part is crossed, second conductivity type body region is located at substrate trenches slot bottom Top；

Step 4, the deposition preventing material layer on the front of above-mentioned semiconductor substrate, and photoetching is coated on the barrier material layer Glue carries out photoetching to the photoresist on barrier material layer using the second mask of substrate, to obtain being located at semiconductor substrate terminal The second photoresist layer of substrate above area, performs etching barrier material layer using the second photoresist layer of substrate, to be located at Substrate barrier layer immediately below the second photoresist layer of substrate；

Step 5 blocks semiconductor substrate terminal area using the second photoresist layer of substrate and substrate barrier floor, to semiconductor The active area of substrate carries out the injection of the second conductive type impurity ion, and the second photoresist layer of substrate is removed after the completion of injection, high After temperature annealing, substrate the second conduction type doped region can be obtained in the active area of semiconductor substrate；

Step 6, the note for carrying out the first conductive type impurity ion to the active area of above-mentioned semiconductor substrate using substrate barrier layer Enter, after high annealing, substrate the first conduction type source dopant region and substrate can be obtained in the active area of semiconductor substrate Two conduction type base regions, substrate the first conduction type source dopant region are located at the top of the second conduction type base region of substrate, lining Bottom the first conduction type source dopant region, the second conduction type base region of substrate are contacted with the outer wall of respective substrate cellular groove；

Step 7 carries out dielectric layer deposition on a semiconductor substrate, to obtain the covering positive substrate dielectric layer of semiconductor substrate, On substrate dielectric layer coating obtain substrate third photoresist layer, using substrate third mask to substrate third photoresist layer into Row photoetching, to obtain the substrate third photoresist layer window of Through-substrate third photoresist layer, the substrate third photoresist layer Window is located at the top of semiconductor substrate active area；

Step 8 performs etching substrate dielectric layer using substrate third photoresist layer and substrate third photoresist layer window, with Obtain the media contact hole of Through-substrate dielectric layer and the first conduction type of substrate source dopant region, the first conduction type of substrate source Doped region can form required substrate the first conduction type source region by media contact hole；

Step 9, the above-mentioned substrate third photoresist layer of removal, and the deposited metal on above-mentioned substrate dielectric layer, to obtain substrate Front metal layer, the substrate face metal layer are covered on substrate dielectric layer and are filled in media contact hole, are filled in Jie Substrate face metal layer in matter contact hole and substrate the first conduction type source region and the second conduction type base region of substrate and Ohmic contact；

Step 10, the 4th photoresist layer of coated substrate on above-mentioned substrate face metal layer, using the 4th mask of substrate to lining The 4th photoresist layer of bottom carries out photoetching, to obtain the 4th photoresist layer window of substrate of the 4th photoresist layer of Through-substrate, utilizes The 4th photoresist layer of substrate and the 4th photoresist layer window of substrate perform etching substrate face metal layer, to obtain perforation lining The substrate metal of bottom front metal layer separates hole, and can separate substrate face metal layer using substrate metal separation hole and be served as a contrast Bottom cellular front metal layer and substrate terminal front metal layer, the substrate cellular front metal layer and the first conductive-type of substrate Type source region and substrate the second conduction type base region Ohmic contact；

Step 11, above-mentioned the 4th photoresist layer of substrate of removal simultaneously carry out passivation layer deposit, to obtain being covered in substrate cellular front Substrate face passivation layer on metal layer, substrate terminal front metal layer, and the substrate face passivation layer is also filled up in substrate In metal separation hole；

Step 12, the 5th photoresist layer of coated substrate on above-mentioned substrate face passivation layer, using the 5th mask layer of substrate to lining The 5th photoresist layer of bottom carries out photoetching, and is carved using the 5th photoresist layer of substrate after photoetching to substrate face passivation layer Erosion, to obtain the substrate source pad hole of Through-substrate front passivation layer, can be made and the lining by substrate source pad hole The just corresponding substrate cellular front metal layer in bottom source pad hole exposes；

Step 13, above-mentioned the 5th photoresist layer of substrate of removal, and required back process is carried out at the back side of semiconductor substrate.

2. the preparation method of power semiconductor according to claim 1, it is characterized in that: partly being led in step 1 described The first photoresist layer of front surface coated substrate of body substrate carries out light to the first photoresist layer of substrate using the first mask of substrate Carve, to obtain substrate the first photoresist layer window of the first photoresist layer of Through-substrate, using the first photoresist layer of substrate and After substrate the first photoresist layer window is to the front etching of semiconductor substrate, required substrate trenches can be obtained.

3. the preparation method of power semiconductor according to claim 1, it is characterized in that: the substrate barrier layer includes Polysilicon layer, silicon dioxide layer or silicon nitride layer.

4. the preparation method of power semiconductor according to claim 1, it is characterized in that: the material of the semiconductor substrate Material includes silicon.

5. the preparation method of power semiconductor according to claim 1, it is characterized in that: in step 2, cellular insulation oxygen Change layer and terminating insulation oxide layer is same processing step layer, cellular insulating oxide, terminating insulation oxide layer are titanium dioxide Silicon layer.

6. the preparation method of power semiconductor according to claim 1, it is characterized in that: the second conductive-type of the substrate The doping concentration of type base area is greater than the doping concentration of the second conductivity type body region.

7. the preparation method of power semiconductor according to claim 3, it is characterized in that: the substrate dielectric layer is two Silicon oxide layer when substrate barrier layer is polysilicon layer, before carrying out dielectric layer deposition, needs to serve as a contrast substrate barrier layer from semiconductor It is removed on bottom.