CN213601874U - MOSFET device - Google Patents
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- CN213601874U CN213601874U CN202022524966.9U CN202022524966U CN213601874U CN 213601874 U CN213601874 U CN 213601874U CN 202022524966 U CN202022524966 U CN 202022524966U CN 213601874 U CN213601874 U CN 213601874U
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 123
- 210000000746 body region Anatomy 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 66
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 44
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 238000000034 method Methods 0.000 abstract description 27
- 238000010586 diagram Methods 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000002360 preparation method Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The utility model discloses a MOSFET device relates to semiconductor power device field. The method is used for solving the problems of poor reliability and weak peripheral withstand voltage of the conventional MOSFET peripheral withstand voltage. The method comprises the following steps: the semiconductor device comprises an active region groove, a peripheral groove, a first conduction type drift layer, a first conduction type body region and a second conduction type source region; the active region groove and the peripheral groove are arranged on the first conductive type drift layer; the second conduction type source region is arranged between the active region grooves and the peripheral grooves, and the bottom of the second conduction type source region is contacted with the upper surface of the first conduction type body region; the thickness of the SAC oxide layer in the peripheral groove is larger than that of the grid oxide layer.
Description
Technical Field
The utility model relates to a semiconductor power device technical field, more specifically relate to a MOSFET device.
Background
In order to form a source electrode on a first conductive type drift layer with lower doping on the surface of a silicon wafer, a traditional injection voltage division ring terminal design method is used for a traditional power device MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, Chinese is a Metal-Oxide-Semiconductor Field Effect Transistor), namely, a terminal region utilizes a PN junction for voltage resistance, a thick dielectric layer is not arranged in the terminal region, and therefore a source electrode photomask is required to shield the terminal region to prevent the source electrode from being injected into the terminal region and damaging a PN junction voltage resistance structure.
In the prior art, the cost is increased by about 15% when each layer of photomask is added, so that the mask plate needs to be prepared during source injection during the preparation of the conventional MOSFET device, and the problems of high manufacturing cost and complex process exist.
Disclosure of Invention
The embodiment of the utility model provides a MOSFET device for when solving current MOSFET device preparation, need prepare the mask plate when injecting into because of the source electrode, there is manufacturing cost height, and the complicated problem of technology.
The embodiment of the utility model provides a MOSFET device, active area slot, peripheral slot, first conductivity type drift layer, first conductivity type body region and second conductivity type source region;
the active region groove and the peripheral groove are arranged on the first conductive type drift layer;
the second conduction type source region is arranged between the active region grooves and the peripheral grooves, and the bottom of the second conduction type source region is contacted with the upper surface of the first conduction type body region;
and the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer.
Preferably, a polysilicon layer is also included;
the active region groove with all set up in the peripheral ditch inslot the polycrystalline silicon layer is located in the active region ditch inslot the upper surface of polycrystalline silicon layer has the same height with the upper surface that is located the grid oxide layer of active region ditch inslot both sides, is located in the peripheral ditch inslot the upper surface of polycrystalline silicon layer has the same height with the upper surface that is located the grid oxide layer of peripheral ditch inslot both sides.
Preferably, the semiconductor device further comprises a cut-off ring region groove, a source region metal layer, a peripheral cut-off region metal layer and a gate region metal layer;
the stop ring region groove is adjacent to the peripheral groove;
the source region metal layer is respectively contacted with the first conductive type body regions positioned between the active region grooves and the peripheral grooves through contact hole metal layers;
the gate region metal layer is in contact with the polycrystalline silicon layer through the contact hole metal layer;
and the peripheral cut-off region metal layer is respectively contacted with the first conductive type body region positioned on one side of the cut-off ring region groove and the polycrystalline silicon layer positioned in the peripheral groove through the contact hole metal layer.
Preferably, the width of the peripheral trench is greater than the width of the active region trench;
the depth of the peripheral groove is greater than that of the active region groove;
the spacing between the peripheral trenches is equal to the spacing between the active region trenches.
Preferably, the width of the peripheral trench is 1.5 times the width of the active region trench;
the depth of the peripheral groove is 0.2 microns more than the depth of the active region groove;
the peripheral groove comprises a grid groove and a peripheral voltage-resisting area groove.
An embodiment of the utility model provides a MOSFET device, include: the semiconductor device comprises an active region groove, a peripheral groove, a first conduction type drift layer, a first conduction type body region and a second conduction type source region; the active region groove and the peripheral groove are arranged on the first conductive type drift layer; the second conduction type source region is arranged between the active region grooves and the peripheral grooves, and the bottom of the second conduction type source region is contacted with the upper surface of the first conduction type body region; and the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer. The MOSFET device terminal voltage dividing ring is different from the traditional injection voltage dividing ring, the groove is used for dividing voltage, the influence of a thermal process on the terminal injection ring can be avoided, and the manufacturing process is easier to control; the thickness of the SAC oxide layer on the peripheral groove is larger than that of the gate oxide layer on the active region groove, so that the problem that a device breaks down at the bottom of the groove can be effectively solved, and the voltage withstanding property of the device is improved; the SAC oxide layer and the gate oxide layer reserved in the terminal area have enough thickness, so that the SAC oxide layer and the gate oxide layer can be used as a photoetching mask plate between peripheral grooves during secondary ion implantation, and only a second conduction type source area is formed between active areas. Meanwhile, the MOSFET device solves the problems of high manufacturing cost and complex process due to the fact that a mask plate needs to be prepared when a source electrode is injected in the prior art, and solves the problems of poor reliability and weak peripheral voltage resistance of the MOSFET.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic view of a process for manufacturing a MOSFET device according to an embodiment of the present invention;
fig. 3A is a schematic diagram of a first conductive type drift layer according to an embodiment of the present invention;
fig. 3B is a schematic diagram illustrating the preparation of an active region trench, a peripheral trench and a stop ring region trench according to an embodiment of the present invention;
fig. 3C is a schematic diagram illustrating the preparation of a SAC oxide layer according to an embodiment of the present invention;
fig. 3D is a schematic diagram of a SAC oxide layer with the active region and the stop ring removed according to an embodiment of the present invention;
fig. 3E is a schematic diagram illustrating the preparation of a gate oxide layer on the first conductivity type drift layer, in the active region trench and in the peripheral trench according to an embodiment of the present invention;
fig. 3F is a schematic diagram illustrating a polysilicon layer according to an embodiment of the present invention;
fig. 3G is a schematic diagram illustrating the preparation of the polysilicon annealed oxide layer according to an embodiment of the present invention;
fig. 3H is a schematic diagram illustrating the preparation of a first conductive type body region according to an embodiment of the present invention;
fig. 3I is a schematic diagram illustrating a second conductive type source region according to an embodiment of the present invention;
fig. 3J is a schematic view of a silica layer according to an embodiment of the present invention;
fig. 3K is a schematic view illustrating a contact hole metal layer according to an embodiment of the present invention;
fig. 3L is a schematic view of a metal layer according to an embodiment of the present invention.
The semiconductor device comprises a first conductive type substrate layer-1, a first conductive type drift layer-2, an active region groove-3, a gate groove-4, a peripheral pressure-resistant region groove-5, a stop ring region groove-6, an SAC oxide layer-7, a gate oxide layer-8, a polycrystalline silicon layer-9, a polycrystalline silicon annealing oxide layer-10, a first conductive type body region-11, a second conductive type source region-12, a silicon dioxide layer-13, contact holes-14, a contact hole metal layer-15, a source region metal layer-17, a gate region metal layer-18, a peripheral stop region metal layer-19, a drain region metal layer-20 and a peripheral groove-45.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Fig. 1 schematically shows a structure of a MOSFET device according to an embodiment of the present invention, as shown in fig. 1, the MOSFET device mainly includes an active region trench 3, a peripheral trench 45, a first conductivity type drift layer 2, a first conductivity type body region 11, and a second conductivity type source region 12.
As shown in fig. 1, the active region trench 3, the peripheral trench 45, and the off-ring region trench 6 are all disposed on the first conductivity type drift layer 2, wherein the active region trench 3 and the off-ring region trench 6 are disposed on both sides of the peripheral trench 45, respectively. In the embodiment of the present invention, in order to optimize the electric field distribution of the active region and the peripheral interface region, preferably, on the one hand, the depth of the peripheral groove 45 is greater than the depth of the active region groove 3; on the other hand, the width of the peripheral trench 45 is also larger than the width of the active region trench 3.
Further, in order to prevent the device from being broken down at the bottom of the trench, i.e., to improve the withstand voltage characteristics of the device, it is preferable that the thickness of the SAC (SAC Sacrificial) oxide layer 7 in the peripheral trench 45 is greater than the thickness of the gate oxide layer 8 in the active region trench 3.
In practical application, the peripheral trench 45 includes a gate trench 4 and a peripheral voltage-withstanding region trench 5, where the gate trench 4 is located between the active region trench 3 and the peripheral voltage-withstanding region trench 5, and correspondingly, the peripheral voltage-withstanding region trench 5 is located between the gate trench 4 and the stop ring region trench 6. It should be noted that the peripheral trench 45 includes a plurality of gate trenches 4 and peripheral voltage-withstanding region trenches 5, and the plurality of peripheral trenches 45 are equally spaced from each other. In order to improve the electric field distribution in the peripheral region so that the withstand voltage of the periphery of the device is higher than that of the active region, it is preferable that the pitches between the plurality of peripheral trenches 45 and the active region trench 3 are also equal. Further, the gate trench 4 and the peripheral voltage-withstanding region trench 5 have the same width, and the gate trench 4 and the peripheral voltage-withstanding region trench 5 also have the same trench depth.
As shown in fig. 1, a polysilicon layer 9 is deposited in each of the active region trench 3, the gate trench 4, the peripheral voltage withstanding region trench 5 and the stop ring region trench 6, and since a gate oxide layer 8 is grown in the active region trench 3 by a thermal oxidation process, and a SAC oxide layer 7 and a gate oxide layer 8 are deposited in the gate trench 4, the stop ring region trench 6 and the peripheral voltage withstanding region trench 5, and the thickness of the SAC oxide layer 7 is greater than that of the gate oxide layer 8, the polysilicon layers 9 deposited on the active region trench 3, the gate trench 4, the peripheral voltage withstanding region trench 5 and the stop ring region trench 6 have different heights, specifically, as shown in fig. 1, the upper surface of the polysilicon layer 9 in the active region trench 3 has the same height as the upper surfaces of the gate oxide layers 8 on both sides of the active region trench, and the upper surfaces of the gate oxide layers 9 in the gate trench 4, the stop ring region trench 6, The upper surface of the polysilicon layer 9 in the stop ring region trench 6 and in the peripheral voltage-withstanding region trench 5 has the same height as the upper surface of the gate oxide layer 8 on the SAC oxide layer 7. Namely, the upper surfaces of the gate oxide layers 8 at the two sides of the active region trench and the upper surface of the polysilicon layer 9 positioned in the active region trench 3 are positioned on the same horizontal line, and the upper surfaces of the gate oxide layers 8 positioned on the SAC oxide layer 7 at the two sides of the gate trench 4, the stop ring region trench 6 and the peripheral voltage-withstanding region trench 5 and the upper surfaces of the polysilicon layer 9 positioned in the gate trench 4, the stop ring region trench 6 and the peripheral voltage-withstanding region trench 5 are positioned on the same horizontal line.
Since the active region trenches 3 include a plurality of trenches, a first conductive type body region 11 is included between each active region trench 3, further, a first conductive type body region 11 is also included on one side of the stop ring region trench 6, further, a region of the active region trench 3 adjacent to the gate trench 4 also includes the first conductive type body region 11, the first conductive type body region 11 is not disposed between the stop ring region trench 6 and the peripheral voltage-withstanding region trench 5, and only the first conductive type body region 11 is included on the other side of the stop ring region trench 6.
Further, a second conductivity type source region 12 is further included in the first conductivity type body region 11, and specifically, the second conductivity type source region 12 is disposed on the first conductivity type body region 11 located between the active region trenches 3; a second conductive type source region 12 is also arranged on the first conductive type body region 11 located in the region where the source region trench 3 is adjacent to the gate trench 4; a second conductive-type source region 12 is also provided on the first conductive-type body region 11 on the side of the stop ring region trench 6.
As shown in fig. 1, contact holes 14 are formed in the first conductive type body region 11 and the second conductive type source region 12 between the active region trenches 3, after metal is provided in the contact holes 14, the contact holes 14 form contact hole metal layers 15, the contact hole metal layers 15 are formed in the first conductive type body region 11 between the active region trenches 3 and the gate trenches 4, and the two contact hole metal layers 15 are in contact with the active region metal layers; contact hole metal layers 15 are arranged on the first conductive type body region 11 and the second conductive type source region 12 which are positioned on one side of the cut-off ring region groove 6, contact hole metal layers 15 are arranged on the polycrystalline silicon layer 9 in the cut-off ring region groove 6, and the two contact hole metal layers 15 are in contact with the peripheral cut-off region metal layer 19; be provided with contact hole metal layer 15 on the polycrystalline silicon layer 9 that is located gate trench 4, this contact hole metal layer 15 contacts with gate region metal layer 18, it should be said that, in the embodiment of the utility model, in order to guarantee that gate region dynamic characteristic is superior to other MOSFET devices, be similar to the charge balance principle of separation gate MOSFET device. Preferably, the contact hole metal layer 15 contacting the gate metal layer is surrounded by a trench on both sides, i.e., the polysilicon layer 9 contacting the contact hole metal layer 15 further has a plurality of polysilicon layers 9 on both sides thereof, and the polysilicon layers 9 each represent the polysilicon layer 9 disposed in the trench.
In the embodiment of the present invention, in order to optimize the electric field distribution of the peripheral boundary region outside the active region, preferably, the width of the gate trench 4 and the peripheral voltage-resistant region trench 5 is 1.5 times the width of the active region trench 3, and the depth of the gate trench 4 and the peripheral voltage-resistant region trench 5 is 0.2 μm more than the depth of the active region trench 3.
In the embodiment of the present invention, the first conductive type is N-type, and the second conductive type is P-type; or the first conductive type is P type, and the second conductive type is N type.
In order to more clearly introduce the MOSFET device provided by the embodiments of the present invention, a method for manufacturing the MOSFET device is described below.
Fig. 2 is a schematic view of a process for manufacturing a MOSFET device according to an embodiment of the present invention; fig. 3A is a schematic diagram of a first conductive type drift layer according to an embodiment of the present invention; fig. 3B is a schematic diagram illustrating the preparation of an active region trench, a peripheral trench and a stop ring region trench according to an embodiment of the present invention; fig. 3C is a schematic diagram illustrating the preparation of a SAC oxide layer according to an embodiment of the present invention; fig. 3D is a schematic diagram of a SAC oxide layer with the active region and the stop ring removed according to an embodiment of the present invention; fig. 3E is a schematic diagram illustrating the preparation of a gate oxide layer on the first conductivity type drift layer, in the active region trench and in the peripheral trench according to an embodiment of the present invention; fig. 3F is a schematic diagram illustrating a polysilicon layer according to an embodiment of the present invention; fig. 3G is a schematic diagram illustrating the preparation of the polysilicon annealed oxide layer according to an embodiment of the present invention; fig. 3H is a schematic diagram illustrating the preparation of a first conductive type body region according to an embodiment of the present invention; fig. 3I is a schematic diagram illustrating a second conductive type source region according to an embodiment of the present invention; fig. 3J is a schematic view of a silica layer according to an embodiment of the present invention; fig. 3K is a schematic view illustrating a contact hole metal layer according to an embodiment of the present invention; fig. 3L is a schematic view of a metal layer according to an embodiment of the present invention.
The following describes in detail a method for manufacturing a MOSFET device with reference to a schematic flow diagram of the manufacturing method provided in fig. 2 and with reference to schematic manufacturing diagrams provided in fig. 3A to 3L, and specifically, as shown in fig. 2, the method mainly includes the following steps:
103, forming a polycrystalline silicon layer and a polycrystalline silicon annealing oxidation layer on the grid oxidation layer through precipitation, etching and thermal oxidation processes;
and 105, forming a contact hole metal layer on the first conductive type body region and the polycrystalline silicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact holes.
Specifically, as shown in fig. 3A, an N-type heavily doped semiconductor first conductivity type substrate layer 1 is provided, and then an N-type lightly doped first conductivity type drift layer 2 is grown on the N-type heavily doped semiconductor first conductivity type substrate layer 1.
In step 101, as shown in fig. 3B, an active region trench 3, a peripheral trench 45, and a stop ring region trench 6 are sequentially formed in the first conductivity type drift layer 2 by etching. Note that the peripheral trench 45 includes the gate trench 4 and the peripheral voltage-withstanding region trench 5.
In the embodiment of the present invention, in order to optimize the electric field distribution of the active region and the peripheral interface region, preferably, on the one hand, the depth of the peripheral groove 45 is greater than the depth of the active region groove 3; on the other hand, the width of the peripheral trench 45 is also larger than the width of the active region trench 3. Further, in order to improve the electric field distribution in the peripheral region so that the withstand voltage in the periphery of the device is higher than the withstand voltage capability of the active region, it is preferable that the pitches between the plurality of peripheral trenches 45 and the active region trench 3 are also equal.
In step 102, as shown in fig. 3C, a sacrificial oxide layer is grown on the upper surface of the first conductive type drift layer 2 and inside the active region trench 3, the gate trench 4, the peripheral withstand voltage region trench 5, and the stop ring region trench 6 by a thermal oxidation process, and then an oxide layer is deposited by a chemical vapor deposition process, so as to form the SAC oxide layer 7.
Further, as shown in fig. 3D, photolithography is performed using a SAC photomask to remove the SAC oxide layer 7 in the active region trench 3 and on the upper surface of the first conductive type drift layer 2 on both sides of the active region trench 3, and to remove the SAC oxide layer 7 on the upper surface of the first conductive type drift layer 2 on one side of the stop ring region trench 6. Note that the first conductivity type drift layer 2 on the inner side of the stop ring region trench 6 indicates the side not adjacent to the peripheral voltage-withstanding region trench 5.
Further, as shown in fig. 3E, a gate oxide layer 8 is grown on the upper surface of the first conductivity type drift layer 2, in the active region trench 3, in the gate trench 4, in the peripheral withstand voltage region trench 5, and in the stop ring region trench 6 by a thermal oxidation process. In the embodiment of the present invention, in order to prevent the device from being broken down at the bottom of the trench, i.e., to improve the voltage withstanding characteristics of the device, it is preferable that the thickness of the SAC oxide layer 7 in the gate trench 4 and the peripheral voltage withstanding region trench 5 is greater than the thickness of the gate oxide layer 8 in the active region trench 3.
In step 103, as shown in fig. 3F, an N-type heavily doped polysilicon layer 9 is deposited on the upper surface of the gate oxide layer 8 by a deposition process, that is, while the polysilicon layers 9 are formed in the active region trench 3, the gate trench 4, the peripheral voltage withstanding region trench 5, and the stop ring region trench 6, a heavily doped polysilicon layer 9 is also deposited on the gate oxide layer 8 on both sides of the active region trench 3, the gate trench 4, the peripheral voltage withstanding region trench 5, and both sides of the stop ring region trench 6. Further, a heavily doped polysilicon layer 9 deposited on the gate oxide layer 8 at two sides of the active region trench 3, two sides of the gate trench 4, two sides of the peripheral voltage-withstanding region trench 5 and two sides of the stop ring region trench 6 is etched away by a back etching process.
As shown in fig. 3G, annealing is performed by a thermal oxidation process to activate the doped elements inside the polysilicon layer 9, and a polysilicon annealed oxide layer 10 is grown on the upper surface of the gate oxide layer 8.
In step 104, as shown in fig. 3H, a first conductivity type body region 11 is formed in the first conductivity type drift layer 2 by a first implantation, where the first conductivity type body region 11 is located between the active region trenches 3, between the active region trenches 3 and the gate trenches 4, and on one side of the stop ring region trench 6. That is, when the first ion implantation is performed, the SAC oxide layer 7 and the gate oxide layer 8 are used as masks between the peripheral trenches 45, thereby blocking the first ion implantation between the peripheral trenches 45.
Note that, at the time of the first implantation, the upper surface of the SAC oxide layer 7 is blocked by photolithography, and the upper surface of the active region gate oxide layer 8 is exposed, so that the first conductivity type body region 11 is formed between the active region trenches 3, between the active region trench 3 and the gate trench 4, and on one side of the stop ring region trench 6 by this implantation.
As shown in fig. 3I, a second conductive type source region 12 is formed in the first conductive type body region 11 between the active region trenches 3 by a second implantation, the second conductive type source region 12 is formed in the first conductive type body region 11 between the active region trenches 3 and the gate trenches 4, and the second conductive type source region 12 is formed in the first conductive type body region 11 at one side of the off ring region trench 6. It should be noted that, in the embodiment of the present invention, SAC oxide layer 7 and gate oxide layer 8 on peripheral trench 45 can be used as the photoresist mask of second conductivity type source region 12, and therefore, when performing the second ion implantation, the photoresist mask is not prepared on peripheral trench 45, and further, because the photoresist mask is not prepared on peripheral trench 45, first conductivity type region 11 between source region trench 3 and gate trench 4 also forms second conductivity type source region 12.
In step 105, as shown in fig. 3J, an isolation silicon dioxide layer 13 is deposited on the surface of the polysilicon annealed oxide layer 10 by a deposition process. Further, as shown in fig. 3K, a contact hole 14 is formed on the silicon dioxide layer 13 by an etching method, and then a metal is filled into the contact hole 14 by a filling method to form a contact hole metal layer 15. Specifically, contact-hole metal layers 15 are formed on the first-conductivity-type body regions 11 and the second-conductivity-type source regions 12 located between the active-region trenches 3, and contact-hole metal layers 15 are formed on the first-conductivity-type body regions 11 located between the active-region trenches 3 and the gate trenches 4; a contact hole metal layer 15 is formed on the first conductive type body region 11 and the second conductive type source region 12 which are positioned on one side of the cut-off ring region groove 6, and a contact hole metal layer 15 is formed on the polycrystalline silicon layer 9 in the cut-off ring region groove 6; a contact hole metal layer 15 is formed on the polysilicon layer 9 within the gate trench 4.
Sputtering a metal layer on the surface of the silicon dioxide layer 13 by a sputtering process, defining a source region metal layer 17, a gate region metal layer 18 and a peripheral cut region metal layer 19 by photoetching and etching processes, thinning the wafer by a grinding process, and forming a drain region metal layer 20 by a metal evaporation process. As shown in fig. 3L, the contact hole metal layer 15 on the first conductivity type body region 11 and the second conductivity type source region 12 between the active region trenches 3 and the contact hole metal layer 15 on the first conductivity type body region 11 between the active region trenches 3 and the gate trenches 4 are both in contact with the active region metal layer; the contact hole metal layers 15 of the first conductive type body region 11 and the second conductive type source region 12 positioned on one side of the stop ring region groove 6 and the contact hole metal layers 15 of the polycrystalline silicon layer 9 positioned in the stop ring region groove 6 are both in contact with the peripheral stop region metal layer 19; the contact hole metal layer 15 of the polysilicon layer 9 located in the gate trench 4 is in contact with the gate region metal layer 18. The drain region metal layer 20 is in contact with the lower surface of the first conductivity type substrate layer 1.
To sum up, the embodiment of the present invention provides a MOSFET device, including: the semiconductor device comprises an active region groove, a peripheral groove, a first conduction type drift layer, a first conduction type body region and a second conduction type source region; the active region groove and the peripheral groove are arranged on the first conductive type drift layer; the second conduction type source region is arranged between the active region grooves and the peripheral grooves, and the bottom of the second conduction type source region is contacted with the upper surface of the first conduction type body region; and the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer. The MOSFET device terminal voltage dividing ring is different from the traditional injection voltage dividing ring, the groove is used for dividing voltage, the influence of a thermal process on the terminal injection ring can be avoided, and the manufacturing process is easier to control; the thickness of the SAC oxide layer on the peripheral groove is larger than that of the gate oxide layer on the active region groove, so that the problem that a device breaks down at the bottom of the groove can be effectively solved, and the voltage withstanding property of the device is improved; the SAC oxide layer and the gate oxide layer reserved in the terminal area have enough thickness, so that the SAC oxide layer and the gate oxide layer can be used as a photoetching mask plate between peripheral grooves during secondary ion implantation, and only a second conduction type source area is formed between active areas. Meanwhile, the MOSFET device solves the problems of high manufacturing cost and complex process due to the fact that a mask plate needs to be prepared when a source electrode is injected in the prior art, and solves the problems of poor reliability and weak peripheral voltage resistance of the MOSFET.
While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A MOSFET device, comprising: the semiconductor device comprises an active region groove, a peripheral groove, a first conduction type drift layer, a first conduction type body region and a second conduction type source region;
the active region groove and the peripheral groove are arranged on the first conductive type drift layer;
the second conduction type source region is arranged between the active region grooves and the peripheral grooves, and the bottom of the second conduction type source region is contacted with the upper surface of the first conduction type body region;
and the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer.
2. The device of claim 1, further comprising a polysilicon layer;
the active region groove with all set up in the peripheral ditch inslot the polycrystalline silicon layer is located in the active region ditch inslot the upper surface of polycrystalline silicon layer has the same height with the upper surface that is located the grid oxide layer of active region ditch inslot both sides, is located in the peripheral ditch inslot the upper surface of polycrystalline silicon layer has the same height with the upper surface that is located the grid oxide layer of peripheral ditch inslot both sides.
3. The device of claim 2, further comprising a stop-ring region trench, a source region metal layer, a peripheral stop region metal layer, and a gate region metal layer;
the stop ring region groove is adjacent to the peripheral groove;
the source region metal layer is respectively contacted with the first conductive type body regions positioned between the active region grooves and the peripheral grooves through contact hole metal layers;
the gate region metal layer is in contact with the polycrystalline silicon layer through the contact hole metal layer;
and the peripheral cut-off region metal layer is respectively contacted with the first conductive type body region positioned on one side of the cut-off ring region groove and the polycrystalline silicon layer positioned in the peripheral groove through the contact hole metal layer.
4. The device of claim 3, wherein a width of the peripheral trench is greater than a width of the active region trench;
the depth of the peripheral groove is greater than that of the active region groove;
the spacing between the peripheral trenches is equal to the spacing between the active region trenches.
5. The device of claim 4,
the width of the peripheral groove is 1.5 times that of the active region groove;
the depth of the peripheral groove is 0.2 microns more than the depth of the active region groove;
the peripheral groove comprises a grid groove and a peripheral voltage-resisting area groove.
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| CN112234103A (en) * | 2020-11-04 | 2021-01-15 | 华羿微电子股份有限公司 | A kind of MOSFET device and preparation method |
| CN112234103B (en) * | 2020-11-04 | 2024-12-10 | 华羿微电子股份有限公司 | MOSFET device and preparation method thereof |
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