CN110957370B - Method for manufacturing lateral double-diffused transistor - Google Patents

Abstract

Disclosed is a method for manufacturing a lateral double diffused transistor, comprising: depositing a pad oxide layer and a first hard mask on the surface of a substrate, wherein the substrate is formed with a P-type well region and an N-type well region separated from each other; an opening of a hard mask to form an N-type drift region in the substrate, the N-type drift region being separated from the P-type well region and adjoining the N-type well region; on the surface of the first hard mask and the pad oxide layer depositing a second hard mask; and forming a field oxide layer over the N-type drift region through the opening of the second hard mask. In the manufacturing method, an opening is formed by etching a first hard mask, a drift region is formed through the opening, the mask is saved, and a second hard mask is deposited over the first hard mask, so that the nitride layer above the drift region has The thickness of the nitride layer is smaller than that of other regions, and the length of the bird's beak is increased, so as to reduce the electric field of the silicon substrate under the bird's beak region, and effectively improve the breakdown voltage of the transistor while saving the process cost.

Description

Manufacturing method of lateral double diffused transistor

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a method for manufacturing a lateral double diffusion transistor.

Background technique

Lateral Double-Diffused MOSFET (LDMOS) transistor, as a kind of power field effect transistor, has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance, etc. Because of its excellent characteristics, it has been widely used, and people's performance requirements for LDMOS are getting higher and higher.

In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible on the premise that the source-drain breakdown voltage BV-dss is high, but the optimization requirements of the source-drain breakdown voltage and the on-resistance are indeed contradictory. of. Generally speaking, the method of reducing the on-resistance of LDMOS is to continuously increase the concentration of the drift region, and at the same time, through various RESURF (Reduced SURface Field) theories, so that it can be completely depleted, so as to obtain low on-resistance. , and maintain a high breakdown voltage.

FIG. 1 shows a schematic cross-sectional structure diagram of a lateral double-diffused transistor in the prior art. As shown in FIG. 1, in the conventional NLDMOS process, a P-well region 102, an N-well region 103 and a drift region 104 are formed in the substrate 101, and the field plate 151 is placed on the field oxide layer 131 of the drift region. The preparation process of the field oxide layer makes a short bird's beak region formed between the gate oxide (gate oxide layer 141) and the field oxide layer 131. When the concentration of the drift region 104 is high, according to Gauss's law, it is very easy to oxidize in the vicinity of the field oxide layer. An extremely strong electric field is generated in the silicon under the gate oxide layer 141 of the layer 131 (at the asterisk in the figure), thereby causing a breakdown, so that the breakdown voltage of the NLDMOS is low.

In the existing manufacturing process, the electric field at the asterisk shown in FIG. 1 is reduced by reducing the concentration of the drift region or the overlapping size of the drift region and the gate oxide layer, thereby increasing the breakdown voltage, but this will cause The on-resistance of the LDMOS is increased, or the cost of process fabrication is increased.

SUMMARY OF THE INVENTION

In view of the above problems, the purpose of the present invention is to provide an optimized method for manufacturing a lateral double diffused transistor, wherein an opening is formed by etching a first hard mask, a drift region is formed through the opening, a mask is saved, and an opening is formed in the first hard mask. A second hard mask is deposited over the die so that the thickness of the nitride layer over the drift region is smaller than that of the other regions, and the length of the bird's beak is increased to reduce the electric field of the silicon substrate under the bird's beak region, at The process cost is saved and the breakdown voltage of the transistor is effectively increased.

According to the present invention, a method for manufacturing a lateral double diffused transistor is provided, comprising:

A pad oxide layer and a first hard mask are sequentially deposited on the surface of the substrate, the substrate is formed with a P-type well region and an N-type well region separated from each other;

forming an N-type drift region in the substrate through the opening of the first hard mask, the N-type drift region being spaced apart from the P-type well region and adjoining the N-type well region;

depositing a second hard mask on the surface of the first hard mask and the pad oxide layer; and

A field oxide layer is formed over the N-type drift region through the opening of the second hard mask.

Optionally, the first hard mask and the second hard mask are respectively formed by the following steps:

forming a nitride layer;

forming a resist mask on the nitride layer; and

The nitride layer is etched through the resist mask to form openings.

Optionally, the resist mask used by the first hard mask when forming openings is an N-type drift region mask, and the resist mask used by the second hard mask when forming openings The mask is an active area mask.

Optionally, forming a field oxide layer over the N-type drift region through the opening of the second hard mask, including the following steps:

etching a portion of the second hard mask over the N-type drift region to expose a portion of the surface of the pad oxide layer; and

A field oxide layer is grown on the exposed areas of the pad oxide layer.

Optionally, after the opening of the second hard mask is formed, the thickness of all the nitride layers above the drift region is smaller than the thickness of all the nitride layers above the P-type well region.

Optionally, the second hard mask that is not etched away above the P-type well region covers the surface of the first hard mask and a part of the surface of the pad oxide layer.

Optionally, the thickness of the second hard mask is smaller than the thickness of the first hard mask.

Optionally, after forming a field oxide layer over the N-type drift region through the opening through the second hard mask, the method further includes the following steps:

etching to remove the second hard mask, the first hard mask and the pad oxide layer;

forming a gate oxide adjacent to the bird's beak region of the field oxide; and

After depositing a field plate layer on the gate oxide layer, a gate electrode is formed by etching, and then source and drain implants are performed.

Optionally, the field plate layer sequentially covers the gate oxide layer and part of the field oxide layer.

Optionally, the field plate layer includes a polysilicon layer.

Optionally, the first hard mask and the second hard mask are grown by chemical vapor deposition.

In the method for manufacturing a lateral double diffused transistor provided by the present invention, an opening is formed by etching a first hard mask, a drift region is formed through the opening, and the opening of the first hard mask is formed when the drift region is fabricated, which saves a mask and simplifies The process steps are saved, and the process cost is saved; and a second hard mask is deposited over the first hard mask, so that the thickness of the nitride layer above the drift region is smaller than that of the other regions, so that the thickness of the drift region is reduced. The increase in the length of the bird's beak is equivalent to introducing a region of gradual thickness transition between the gate oxide layer and the field oxide layer, thereby reducing the electric field of the silicon substrate under the bird's beak region, thereby effectively improving the breakdown voltage of the transistor. The first hard mask is etched by using the drift region mask as the blocking layer, without using a separate mask, which simplifies the process difficulty and saves the process cost.

Preferably, the thickness of the second hard mask is smaller than that of the first hard mask, which further ensures that the thickness of the nitride layer above the drift region is smaller than the thickness of the nitride layer on the P-type well region, so the bird’s beak of the drift region is The increase in length makes a thickness transition region between the field oxide layer and the gate oxide layer, instead of a bird's beak with a transient decrease in thickness, which greatly reduces the electric field of the silicon substrate under the bird's beak region, thereby effectively improving the transistor's hit. Breakthrough voltage and reduce on-resistance.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic cross-sectional structure diagram of a lateral double-diffused transistor in the prior art;

2a-2e illustrate schematic cross-sectional views of various stages of a conventional lateral double-diffused transistor fabrication method;

3 shows a flowchart of a method for manufacturing a lateral double diffused transistor according to an embodiment of the present invention;

4a to 4j illustrate schematic cross-sectional views of various stages of a method of fabricating a lateral double diffused transistor according to an embodiment of the present invention.

Detailed ways

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are designated by the same or similar reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

In describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it can mean directly on the other layer, another region, or directly on the other layer or region Other layers or regions are also included between another layer and another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region.

In order to describe the situation directly above another layer, another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein. In this application, "A is located directly in B" means that A is located in B, and A is directly adjacent to B, rather than A located in a doped region formed in B.

Unless specifically indicated below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors, such as GaAs, InP, GaN, SiC, and group IV semiconductors, such as Si, Ge. The gate conductor and electrode layer can be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN , TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni ₃ Si, Pt, Ru, W, and combinations of the various conductive materials.

In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of fabricating a semiconductor device, including all layers or regions that have already been formed. The term "laterally extending" means extending in a direction substantially perpendicular to the groove depth direction.

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

2a-2e illustrate schematic cross-sectional views of various stages of a conventional lateral double-diffused transistor manufacturing method, and the conventional transistor manufacturing process will be described below with reference to FIGS. 2a-2e.

As shown in FIG. 2a , which is a schematic cross-sectional view of a certain stage of the traditional LDMOS device manufacturing method, first, a P-type well region 202 located on the top of the substrate 201 is formed in an N-type doped semiconductor substrate such as a silicon substrate 201 , an N-type well region 203 , and an N-type drift region 204 located on the side of the P-type well region 202 , and the N-type drift region 204 and the P-type well region 202 are separated from each other. A well mask is required to form the P-type well region 202 and the N-type well region 203, and a drift region mask is also required to form the N-type drift region 204, which is a necessary step in the preparation process, and will not be described in detail here. introduce.

Then, a pad oxide layer 212 is deposited on the surface of the silicon substrate 201 , and a first layer of mask 221 is placed over the pad oxide layer 212 above the drift region 204 , and the pad oxide layer 212 is covered by the mask 221 . Etching is performed to remove the pad oxide layer 212 over the two well regions.

Further, as shown in FIG. 2 b , the mask 221 is removed, and a second layer of pad oxide layer 211 is deposited on the surface of the substrate 201 , the pad oxide layer 211 covers the pad oxide layer 212 , and the pad oxide layer 211 A hard mask 213 is deposited on the surface. The materials of the pad oxide layer 212 and the pad oxide layer 211 are the same, for example, silicon oxide, and the hard mask 213 is, for example, silicon nitride. Then, a second layer of mask, ie, an active region mask 222, is provided over the pad oxide layer 211 over the P-type well region 202 and the N-type well region 203, and the active region mask 222 enables the N-type drift region 204 The upper hard mask 213 is exposed. The hard mask 213 is then etched using the active region mask 222 .

Further, as shown in FIG. 2c, it is a cross-sectional view of the hard mask 213 after being etched. The hard mask 213 located above the P-type well region 202 extends from the P-type well region 202 to the drift region 204, covering part of the lining pad oxide layer 212 , while the hard mask 213 over the N-type well region 203 only covers the pad oxide layer 211 .

Further, as shown in FIG. 2d, the pad oxide layers 211 and 212 above the N-type drift region 204 that are not covered by the hard mask 213 react under certain conditions to form a field oxide layer 231. The ends form the beak area. Due to the existence of the pad oxide layer 212 , the bird's beak region of the field oxide layer 231 close to one end of the P-type well region 202 is adjacent to the pad oxide layer 212 , and then contacts the pad oxide layer 211 . The thickness of the pad oxide layer 212 is greater than that of the pad oxide layer 211 , so that an oxide layer with increasing thickness is gradually formed from the P-type well region 202 to the drift region 204 .

Further, as shown in FIG. 2e, the hard mask 213 and the pad oxide layer 211 are removed by etching, leaving only the field oxide layer 231 and the pad oxide layer 212 adjacent thereto. Then, oxide is deposited over the P-type well region 202 to form a gate oxide layer 241 . Then, a polysilicon layer is deposited over the gate oxide layer 241 to form the field plate 251 and the gate, and finally ion implantation is performed to form source and drain regions in the P-type well region 202 and the N-type well region 203, respectively. Both the source and drain regions are N-type doped regions.

In this transistor, a pad oxide layer 212 is added between the gate oxide layer 241 and the bird's beak of the field oxide layer 231, so that a stepped oxide layer is formed from the P-type well region 202 to the N-type drift region 204, which makes the figure In 2e, the thickness of the oxide layer at the star mark is increased, thereby reducing the electric field there, so the breakdown voltage is greatly improved, but in the manufacturing method of the LDMOS device, after the N-type drift region 204 and the well region are formed, it is also necessary to use To two masks, and to perform two etching processes with the mask as a stop, to deposit a thicker pad oxide layer over the N-type drift region 204, so as to achieve the voltage increase at the star mark, and use the mask multiple times. The mold makes the process cost high, and the preparation is time-consuming, which increases the complexity of the process and is not conducive to mass production. Because the present invention improves the traditional LDMOS device manufacturing method, the LDMOS device structure is fabricated through the process steps of FIGS. 3 and 4a-4j to further improve transistor characteristics, reduce on-voltage drop and increase breakdown voltage.

3 shows a flowchart of a method of manufacturing a lateral double diffused transistor according to an embodiment of the present invention; FIGS. 4a to 4j show schematic cross-sectional views of various stages of a method of manufacturing a lateral double diffused transistor according to an embodiment of the present invention.

The following describes the manufacturing process of the LDMOS device according to the embodiment of the present application with reference to FIGS. 3-4j.

As shown in FIG. 3 , in step S101 , a pad oxide layer and a first hard mask are sequentially deposited on the surface of the substrate, and the substrate is formed with a P-type well region and an N-type well region separated from each other.

As shown in FIG. 4 a , a P-type well region 402 and an N-type well region 403 isolated from the P-type well region 402 are formed inside the semiconductor substrate 401 . This step is accomplished using conventional techniques. Then, a pad oxide layer 411 is deposited on the surface of the substrate 401, the substrate 401 is, for example, a silicon substrate, and the pad oxide layer 411 is, for example, silicon oxide.

Next, as shown in FIG. 4 b , a first hard mask 413 is deposited on the surface of the pad oxide layer 411 , and then a resist mask 421 is arranged on the first hard mask 413 above the P-type well region 402 . The resist mask 421 is used to form the N-type drift region, and is a mask that needs to be used in all conventional process steps.

In step S102, an N-type drift region is formed in the substrate through the opening of the first hard mask, and the N-type drift region is separated from the P-type well region and is adjacent to the N-type well region.

In one embodiment, the first hard mask 413 is nitride, such as silicon nitride, and the first hard mask 413 is formed by the following steps: forming a nitride layer; forming a resist mask on the nitride layer; and etching the nitride layer through the resist mask to form openings.

Specifically, as shown in FIG. 4b , a resist mask 421 is provided above the first hard mask 413 above the P-type well region 402, and the resist mask 421 is used to form an N-type drift region, preferably, The resist mask 421 is a drift region mask.

As shown in FIG. 4 c , the first hard mask 413 is etched by using the resist mask 421 as a blocking layer, and an N-type drift region is implanted to form an N-type drift region 404 on the side of the P-type well region 402 . The first hard mask 413 above the N-type drift region 404 is etched away by using the resist mask 421 as a blocking layer to expose the pad oxide layer 411 , and then ion implantation is performed to form the N-type drift region 404 .

In step S103, a second hard mask is deposited on the surfaces of the first hard mask and the pad oxide layer.

Next, as shown in FIG. 4d , a second nitride layer, that is, a second hard mask 414, is deposited on the surfaces of the remaining first hard mask 413 and the pad oxide layer 411. At this time, the second hard mask 414 covers First hard mask 413 and pad oxide layer 411 .

Preferably, the first hard mask 413 and the second hard mask 414 are both nitride layers, such as silicon nitride. In one embodiment, the first hard mask 413 and the second hard mask 413 are deposited by chemical vapor deposition. Two hard masks 414 .

In this step, the resist mask 421 is used as a blocking layer to etch the first hard mask 413 to define the deposition area of the second hard mask 212 to form the P-type well region 402 to the N-type drift region 404 Distribution of nitride layers of decreasing thickness. Compared with using a separate mask 221 to etch the second pad oxide layer 212 in the traditional process, one mask is saved, the process steps are simplified, and the process cost is saved.

In step S104, a field oxide layer is formed over the N-type drift region through the opening of the second hard mask.

Specifically, as shown in FIG. 4e , a resist mask 422 is provided above the second hard mask 414 , the resist mask 422 is an active region mask, and the resist mask 422 is used for blocking etching The second hard mask 414 is etched to form openings. When the active region mask is positioned over the second hard mask 414, the second hard mask 414 over the N-type drift region 404 is exposed.

In this step, the formation process of the second hard mask 414 is the same as the formation process of the first hard mask 413, including the following steps: forming a nitride layer; forming a resist mask on the nitride layer; The resist mask etches the nitride layer to form openings.

Further, forming a field oxide layer 431 over the N-type drift region 404 through the opening of the second hard mask 414 includes the following steps:

In step 1, a portion of the second hard mask 414 located above the N-type drift region 404 is etched to expose a portion of the surface of the pad oxide layer 411 . As shown in FIG. 4f, the second hard mask 414 is etched, so that the second hard mask 414 above the N-type drift region 404 is etched away, exposing the pad oxide layer 411 below.

In this step, it needs to be ensured that after etching the second hard mask 414 , the thickness of all the nitride layers above the N-type drift region 404 is smaller than the thickness of all the nitride layers above the P-type well region 402 .

In one embodiment, the unetched second hard mask 414 over the P-type well region 402 covers the surface of the first hard mask 413 and part of the surface of the pad oxide layer 411 , so that the P-type well region is The thickness of the nitride layer above the P-type well region 402 is made larger than the thickness of the nitride layer above the N-type drift region 404 .

In another embodiment, the thickness of the second hard mask 414 is smaller than the thickness of the first hard mask 413 , so that even if the second hard mask 414 does not cover the first hard mask 413 , due to the thickness of the second hard mask 414 If the thickness is smaller than that of the first hard mask 413 , the thickness of the nitride layer on the N-type drift region 404 is still smaller than the thickness of the nitride layer on the P-type well region 402 .

In step 2, a field oxide layer is grown on the exposed area of the pad oxide layer 411 . As shown in FIG. 4f, the pad oxide layer 411 not covered by the second hard mask 414 reacts under certain conditions to form a field oxide layer 431, for example, at a high temperature, reacts to generate silicon dioxide.

As shown in FIG. 4g, the field oxide layer 431 forms a bird's beak region at the contact edge of the second hard mask 414 and the pad oxide layer 411, and the thickness of the second hard mask 414 above the N-type drift region 404 is thinner , the thickness of the nitride layer above the N-type drift region 404 is smaller than the thickness of the nitride layer in other regions, so the length of the bird’s beak above the N-type drift region 404 is longer, and the nitride layer in other regions has a normal thickness, so the bird’s beak is long. The length of the mouth is similar to the traditional craft. As a result, the length of the bird's beak region of the field oxide layer 431 is increased, so that a thickness transition region is formed before the pad oxide layer 411 and the field oxide layer 431 to reduce the electric field under the bird's beak region. Due to the existence of the field oxide layer 431, the edge of the second hard mask 414 in contact with the pad oxide layer 411 is lifted up, which is consistent with the shape of the bird's beak region.

Further, in this embodiment, the thickness of the second hard mask 413 above the N-type drift region 404 is smaller than the thickness of the second hard mask 213 above the N-type drift region 204 in the conventional transistor shown in FIG. 2d, Therefore, the length of the bird's beak in the bird's beak region formed in this embodiment is larger than that of the bird's beak formed in the traditional process, so it is equivalent to introducing a thickness transition region, and the bird's beak is no longer a structure that decreases instantaneously. The electric field below the bird's beak region increases the breakdown voltage.

In one embodiment, the manufacturing method of the LDMOS device of the present invention further includes steps S105-S107. The description is expanded below.

In step S105, the second hard mask, the first hard mask and the pad oxide layer are removed by etching.

Next, as shown in FIG. 4h, the second hard mask 414, the first hard mask 413 and the exposed pad oxide layer 411 are removed by etching, and the position of the pad oxide layer 411 above the P-type well region 202 will be subsequently removed. A gate oxide layer is formed. After etching, only the field oxide layer 431 remains.

In step S107, a gate oxide layer adjacent to the bird's beak region of the field oxide layer is formed.

Further, as shown in FIG. 4i, a gate oxide layer 441 is grown. A gate oxide layer 441 is grown on the silicon substrate 401 around the field oxide layer 431 by a certain deposition process. The gate oxide layer 441 covers the channel, that is, covers part of the surface of the well region 402 and part of the N-type drift region 404 . The gate oxide layer 441 is silicon dioxide, for example, as a gate insulating layer of the transistor.

In step S108, a field plate layer is deposited on the gate oxide layer, and then a gate electrode is formed by etching, and then source and drain implants are performed.

As shown in FIG. 4j , a field plate layer 451 is deposited over the gate oxide layer 441 and then etched to remove unnecessary parts, so that the remaining field plate layer 451 covers the gate oxide layer 441 and the field oxide layer 431 in turn. The field plate layer 451 includes, for example, a polysilicon layer, thereby forming a gate electrode. Then, N-type ions are implanted in the P-type well region 402 and the N-type well region 403 to form a source region and a drain region, respectively. Thus, the preparation of the LDMOS as shown in FIG. 4j is completed.

In this transistor, a long bird's beak is formed between the gate oxide layer 441 and the field oxide layer 431, which is equivalent to introducing an oxide layer region with a thickness transition, so that the electric field at the star mark decreases, thereby increasing the breakdown voltage. In the preparation process, the drift region mask is used as the barrier layer to change the thickness of the nitride layer at each position on the substrate 401, which saves a mask and simplifies the process steps, so that the process cost is not increased. This increases the breakdown voltage of the transistor.

In the present invention, NLDMOS (the N-type drift region is an N-type semiconductor) is used as an example for description, but this manufacturing method is also applicable to PLDMOS. It is also applicable to the preparation process of other field oxide layers.

In summary, using the method for manufacturing a lateral double diffused transistor according to the embodiment of the present invention, the opening is formed by etching the first hard mask, the N-type drift region is formed through the opening, and the first hard mask is formed while the N-type drift region is fabricated. The opening of the mold saves the mask, simplifies the process steps, and saves the process cost; and deposits the second hard mask over the first hard mask, so that the thickness of the nitride layer above the N-type drift region is smaller than other regions The thickness of the nitride layer is increased, so that the bird’s beak length of the N-type drift region increases, which is equivalent to introducing a region of gradual thickness transition between the gate oxide layer and the field oxide layer, thereby reducing the silicon substrate under the bird’s beak region. The electric field can effectively increase the breakdown voltage of the transistor. At the same time, because the N-type drift region mask is used as the barrier layer to etch the first hard mask, no separate mask is used, which simplifies the process difficulty and saves the process. cost.

Further, the thickness of the second hard mask is smaller than that of the first hard mask, which further ensures that the thickness of the nitride layer above the N-type drift region is smaller than the thickness of the nitride layer on the P-type well region, so the N-type drift region is The increase of the bird’s beak length in the region makes a thickness transition region formed between the field oxide and the gate oxide, instead of a bird’s beak with a transient decrease in thickness, which greatly reduces the electric field of the silicon substrate under the bird’s beak region, thereby effectively Increase the breakdown voltage of the transistor and reduce the on-resistance.

Embodiments in accordance with the present invention are described above, but these embodiments do not exhaust all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is to be limited only by the claims and their full scope and equivalents.

Claims (10)

1. A method for manufacturing a lateral double-diffused transistor, comprising: A pad oxide layer and a first hard mask are sequentially deposited on the surface of the substrate, the substrate is formed with a P-type well region and an N-type well region separated from each other; forming an N-type drift region in the substrate through the opening of the first hard mask, the N-type drift region being spaced apart from the P-type well region and adjoining the N-type well region; depositing a second hard mask on the surface of the first hard mask and the pad oxide layer; and forming a field oxide layer over the N-type drift region through the opening of the second hard mask, Wherein, the first hard mask and the second hard mask are both nitride layers, and after the opening of the second hard mask is formed, the thickness of all the nitride layers above the drift region is less than the thickness of all the nitride layers. thicknesses of all the nitride layers above the P-type well region to form a distribution of nitride layers with decreasing thicknesses from the P-type well region to the N-type drift region. 2. The method for manufacturing a lateral double diffused transistor according to claim 1, wherein the first hard mask and the second hard mask are formed by the following steps: forming a nitride layer; forming a resist mask on the nitride layer; and The nitride layer is etched through the resist mask to form openings. 3 . The method for manufacturing a lateral double diffused transistor according to claim 2 , wherein the resist mask used by the first hard mask to form the opening is an N-type drift region mask, and the The resist mask used by the second hard mask to form the opening is an active region mask. 4 . The method for manufacturing a lateral double diffused transistor according to claim 1 , wherein forming a field oxide layer over the N-type drift region through the opening of the second hard mask, comprising the following steps: 5 . etching a portion of the second hard mask over the N-type drift region to expose a portion of the surface of the pad oxide layer; and A field oxide layer is grown on the exposed areas of the pad oxide layer. 5 . The method for manufacturing a lateral double diffused transistor according to claim 1 , wherein the first hard mask is covered by the second hard mask that is not etched away above the P-type well region. 6 . surface and part of the surface of the pad oxide layer. 6 . The method for manufacturing a lateral double diffused transistor according to claim 1 , wherein the thickness of the second hard mask is smaller than the thickness of the first hard mask. 7 . 7 . The method for manufacturing a lateral double diffused transistor according to claim 4 , wherein after forming a field oxide layer over the N-type drift region through the opening of the second hard mask, the method further comprises the following steps. 8 . : etching to remove the second hard mask, the first hard mask and the pad oxide layer; forming a gate oxide adjacent to the bird's beak region of the field oxide; and After depositing a field plate layer on the gate oxide layer, a gate electrode is formed by etching, and then source and drain implants are performed. 8 . The method for manufacturing a lateral double diffused transistor according to claim 7 , wherein the field plate layer sequentially covers the gate oxide layer and part of the field oxide layer. 9 . 9 . The method for manufacturing a lateral double diffused transistor according to claim 7 , wherein the field plate layer comprises a polysilicon layer. 10 . 10 . The method for manufacturing a lateral double diffusion transistor according to claim 1 , wherein the first hard mask and the second hard mask are grown by chemical vapor deposition. 11 .

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