CN113745338A - Groove type silicon carbide MOSFET device structure and preparation method thereof - Google Patents
Groove type silicon carbide MOSFET device structure and preparation method thereof Download PDFInfo
- Publication number
- CN113745338A CN113745338A CN202110992436.3A CN202110992436A CN113745338A CN 113745338 A CN113745338 A CN 113745338A CN 202110992436 A CN202110992436 A CN 202110992436A CN 113745338 A CN113745338 A CN 113745338A
- Authority
- CN
- China
- Prior art keywords
- trench
- silicon carbide
- type
- layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 81
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 81
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 83
- 239000002184 metal Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000002513 implantation Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 239000000243 solution Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 7
- 238000002347 injection Methods 0.000 description 11
- 239000007924 injection Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开了一种沟槽型碳化硅MOSFET器件，其结构包括n型碳化硅衬底、位于衬底上方的n型碳化硅外延层、位于外延层顶部的沟槽栅、包裹于沟槽栅下部的氧化层，以及位于氧化层两侧且从上到下依次为n型源区、p型基区、p型沟槽保护区；一电流传输区，形成于氧化层的底部；n型源区及p型基区的上方形成有接触金属；沟槽栅的顶部为层间电介质层；所述层间电介质层的上方依次为金属pad和钝化层；器件的底部形成有漏极金属。本发明还公开了该器件的制备方法。该方法采用倾角注入形成沟槽保护区结构，在对沟槽底部栅氧形成有效保护的同时，最大程度的减少了沟槽保护区对导通电阻的影响，具有更低的电流传输区电阻。
The invention discloses a trench type silicon carbide MOSFET device. Its structure includes an n-type silicon carbide substrate, an n-type silicon carbide epitaxial layer located above the substrate, a trench gate located on the top of the epitaxial layer, and a trench gate wrapped around the trench gate. The lower oxide layer, and the n-type source region, the p-type base region, and the p-type trench protection zone are located on both sides of the oxide layer in order from top to bottom; a current transfer region is formed at the bottom of the oxide layer; the n-type source A contact metal is formed above the region and the p-type base region; the top of the trench gate is an interlayer dielectric layer; the top of the interlayer dielectric layer is a metal pad and a passivation layer in sequence; a drain metal is formed at the bottom of the device. The invention also discloses a preparation method of the device. The method adopts the dip angle implantation to form the trench protection zone structure, which effectively protects the gate oxide at the bottom of the trench, minimizes the influence of the trench protection zone on the on-resistance, and has lower current transmission area resistance.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a groove type silicon carbide MOSFET device structure and a preparation method thereof.
Background
Trench-type silicon carbide MOSFET devices, as recognized next-generation silicon carbide power semiconductor devices, have lower specific on-resistance and on-voltage drop than planar-type devices. The smaller device area also provides a potential cost advantage for trench-type silicon carbide power devices, which are considered to be a comprehensive replacement for planar devices once design, fabrication, and reliability issues are overcome. The trench type silicon carbide power device inherits the core technology of a planar device in the fields of design methods, processes and the like, but has uniqueness. The technical difficulties of a groove etching process, a groove oxidation process, a groove gate oxide protection design method and the like are large.
The most significant problem with silicon carbide trench MOSFETs is the high field strength of the gate oxide in the blocking state. In order to maintain the long-term reliability of the silicon carbide MOSFET device, the highest field intensity of the gate oxide in the blocking state needs to be limited below 3MV/cm, while the field intensity of the gate oxide in the blocking state of the silicon carbide trench MOSFET without a protective structure often reaches above 8MV/cm and is far higher than the requirement of the field intensity working reliability. Silicon carbide trench MOSFET devices therefore require special gate oxide protection structures to avoid blocking state gate oxide breakdown.
Currently, the mainstream silicon carbide trench gate structure includes a double trench structure proposed by lom corporation, an asymmetric trench structure proposed by the british flying corporation, a V-type gate trench structure proposed by sumitomo corporation, a deep P-base trench structure proposed by bosch corporation, and a TED-MOS structure proposed by hitachi corporation. The structures are combined with the structure of the optimized groove through P-type injection, so that the shielding of the gate oxide in a blocking state is realized, and the gate oxide is effectively protected. However, the double-trench structure requires fine line width control and trench depth control; the asymmetric groove structure sacrifices the conduction performance of partial devices; the V-shaped groove structure needs to be prepared on the C surface of the wafer and needs to be developed again with a large number of processes; high-energy ion implantation above MeV is needed in deep P base region implantation, so that defect risks are introduced at the same time of high cost; the TED-MOS structure is too complex and the manufacturing difficulty is very high.
Disclosure of Invention
The invention provides a groove type silicon carbide MOSFET device structure and a preparation method thereof, which have the characteristics of simple preparation method, strong gate oxide protection effect, good conduction performance and the like and are suitable for large-scale production.
In a first aspect, the present invention provides a trench type silicon carbide MOSFET device structure, comprising: an n-type highly doped silicon carbide substrate (1); an n-type lightly doped silicon carbide epitaxial layer (2) is positioned above the silicon carbide substrate (1); a trench gate (7) positioned on top of the silicon carbide epitaxial layer (2); the oxide layer (6) wraps the lower part of the trench gate (7), and the two sides of the oxide layer are sequentially provided with an n-type highly-doped source region (4), a p-type base region (3) and a p-type trench protection region (8) from top to bottom; a current transmission region (5) formed at the bottom of the oxide layer (6) and between the oxide layer (6) and the p-type trench protection region (8); contact grooves are formed on the surfaces and the side walls of the source region (4) and the p-type base region (3), and contact metal (10) is filled in the contact grooves; the top of the trench gate (7) is provided with an interlayer dielectric layer (9); a metal pad (11) and a passivation layer (12) are sequentially arranged above the interlayer dielectric layer (9); the bottom of the device is formed with a drain metal (13).
Further, the thickness of the bottom of the oxide layer (6) is 300nm to 800nm, and the thickness of the side wall is 30nm to 60 nm.
In another aspect of the present invention, the present invention provides a method for manufacturing a trench type silicon carbide MOSFET device, including:
s1, epitaxially growing a silicon carbide epitaxial layer on the silicon carbide substrate;
s2, forming a p-type base region on the top of the silicon carbide epitaxial layer through ion implantation;
s3, arranging a first implantation mask on the top of the silicon carbide epitaxial layer, and forming an n-type source region through ion implantation;
s4, after the first injection mask is removed, arranging a first etching mask above the silicon carbide epitaxial layer, and etching to form a silicon carbide groove;
s5, forming a current transmission layer on the lower portion of the silicon carbide groove by taking the first etching mask as a second injection mask;
s6, after the first etching mask is removed, sequentially filling and forming a silicon dioxide layer and a polysilicon layer in the silicon carbide groove, and carrying out surface planarization;
s7, forming a second etching mask on the flattened device structure, and etching to form a contact groove;
s8, forming a p-type groove protection area by using the contact groove as a third injection mask and adopting inclination angle injection;
s9, removing the second etching mask, and corroding the silicon dioxide structure between the side wall of the silicon carbide groove and the polycrystalline silicon layer by a wet method;
s10, corroding the polycrystalline silicon layer in the structure by using alkaline corrosive liquid, and reserving silicon dioxide at the bottom of the silicon carbide groove for forming an oxide layer;
s11, after high-temperature activation annealing, performing high-temperature gate oxide oxidation, depositing and etching to form a polysilicon gate electrode;
s12, depositing silicon dioxide on the structure, etching to form an interlayer dielectric layer, stripping metal, and performing rapid thermal annealing to form source contact metal;
and S13, evaporating Al on the front surface and etching to form a metal pad structure, covering the passivation layer and etching to form a window, and sputtering drain metal on the back surface and then performing laser annealing to form the drain metal.
Further, the ion implantation for forming the current transfer region is performed with an inclination angle of 30 ° to 45 °.
Further, the ion implantation for forming the trench protection region is performed by using a tilt angle of 15 ° to 30 °.
Further, the depth of the trench gate is 0.8-1.6 μm, the depth of the contact trench under the contact metal is 0.4-0.8 μm, and is shallower than the depth of the trench gate;
further, the alkaline etching solution for etching the polysilicon is a mixed solution of NaOH and NaClO 3.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
compared with the traditional technology, the groove type silicon carbide MOSFET device and the preparation method thereof adopt the dip angle injection to form the groove protection area structure, effectively protect the grid oxide at the bottom of the groove, simultaneously reduce the influence of the groove protection area on the on-resistance to the maximum extent, have lower current transmission area resistance and simultaneously improve the performance of the body diode. In the device preparation process, the method does not need to use overhigh injection energy, has low requirement on injection equipment and has shorter injection time.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings shown below are only some embodiments of the present invention and are not intended to limit the present invention.
Fig. 1 is a schematic diagram of a trench-type silicon carbide MOSFET device in accordance with an embodiment of the present invention;
fig. 2 is a flow chart of a method of fabricating a trench-type silicon carbide MOSFET device in accordance with an embodiment of the present invention;
fig. 3-15 are schematic diagrams of device structures obtained at different steps of a method for fabricating a trench-type silicon carbide MOSFET device according to an embodiment of the present invention.
Description of the main elements
Silicon carbide epitaxial layer 2
P-type base region 3
Trench gate 7
Polysilicon layer 71
P-type trench protection region 8
Interlayer dielectric layer 9
Contact metal 10
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, in one aspect, an embodiment of the present invention provides a trench type silicon carbide MOSFET device structure. The structure comprises an n-type highly-doped silicon carbide substrate (1) and an n-type lightly-doped silicon carbide epitaxial layer (2), wherein the n-type highly-doped silicon carbide epitaxial layer is positioned above the silicon carbide substrate (1); a trench gate (7) positioned on top of the silicon carbide epitaxial layer (2); the oxide layer (6) wraps the lower part of the trench gate (7), and the two sides of the oxide layer are sequentially provided with an n-type highly-doped source region (4), a p-type base region (3) and a p-type trench protection region (8) from top to bottom; a current transmission region (5) formed at the bottom of the oxide layer (6) and between the oxide layer (6) and the p-type trench protection region (8); contact grooves are formed on the surfaces and the side walls of the n-type highly-doped source region (4) and the p-type base region (3), and contact metal (10) is filled in the contact grooves; the top of the trench gate (7) is provided with an interlayer dielectric layer (9); a metal pad (11) and a passivation layer (12) are sequentially arranged above the interlayer dielectric layer (9); the bottom of the device is formed with a drain metal (13).
In the present embodiment, the thickness of the silicon carbide epitaxial layer (2) is 5 μm to 35 μm. The depth of the trench gate (7) is 0.8-1.2 μm. The thickness of the bottom of the oxide layer (6) is 300nm to 800nm, and the thickness of the side wall is 30nm to 60 nm. The depth of the n-type highly doped source region (4) is 0.2 to 0.3 μm. The depth of the p-type base region (3) is 0.5 mu mTo 1 μm. The bottom of the p-type groove protection region (8) is a curved surface, and the total depth is 1-2 mu m. The depth of two sides of the p-type groove protection region (8) is 0.6-1.2 mu m, and the doping concentration is 2E16cm-3To 1E17cm-3。
In the present embodiment, the contact trench depth under the contact metal (10) is 0.4 μm to 0.8 μm and is shallower than the trench gate (7).
Referring to fig. 2, an embodiment of the present invention provides a method for manufacturing a trench-type silicon carbide MOSFET device, and particularly provides a method for manufacturing a trench-type silicon carbide MOSFET device based on the material and process characteristics of silicon carbide, the method including the following steps:
step S1: a silicon carbide epitaxial layer (2) is epitaxially grown on a silicon carbide substrate (1), as shown in fig. 3.
Step S2: and forming a p-type base region (3) on the top of the silicon carbide epitaxial layer (2) through p-type ion implantation, as shown in figure 4.
Step S3: an implantation mask (41) is arranged above the structure of the silicon carbide epitaxial layer (2), and ion implantation is performed through the implantation mask (41) to form a source region (4), as shown in fig. 5. In the present embodiment, the source region (4) is an n-type highly doped source region.
Step S4: after removing the implantation mask (41), arranging an etching mask (51) above the silicon carbide epitaxial layer (2), and etching through the etching mask (51) to form a silicon carbide trench on the top of the silicon carbide epitaxial layer (2), as shown in fig. 6.
Step S5: injecting N ions to form a current transmission layer (5) by using the etching mask (51) as an injection mask and injecting the N ions at the lower part of the silicon carbide groove by using the inclined angle ion injection, thereby obtaining the structure shown in figure 7; in the present embodiment, the ion implantation for forming the current transfer region (5) is performed at an inclination of 30 ° to 45 °.
Step S6: after removing the etching mask (51), sequentially filling and forming a silicon dioxide layer (61) and a polysilicon layer (71) in the silicon carbide trench, and performing surface planarization, as shown in fig. 8.
Step S7: forming an etching mask (81) on the planarized device structure by etching, and forming a contact trench by secondary etching, as shown in fig. 9; in the present embodiment, the depth of the contact trench is 0.4 μm to 0.8 μm and is shallower than the depth of the polysilicon layer (71).
Step S8: forming a p-type groove protection region (8) by using Al ion tilt angle implantation by using the contact groove as an implantation mask, as shown in FIG. 10; in the embodiment, the ion implantation for forming the p-type groove protection region (8) adopts a tilt angle of 15-30 degrees.
Step S9: the etching mask (81) of the above structure is removed, and the silicon dioxide between the side wall of the silicon carbide trench and the polysilicon layer (71) is completely etched by a wet etching process, as shown in fig. 11.
Step S10: adopting alkaline corrosive liquid to corrode the polysilicon layer (71) in the structure, and reserving silicon dioxide at the bottom of the silicon carbide groove, as shown in figure 12; preferably, the alkaline etching solution for etching the polysilicon can be a mixed solution of NaOH and NaClO 3.
Step S11: after high-temperature activation annealing, high-temperature gate oxide oxidation is performed to oxidize the side wall gate of the silicon carbide trench, an oxide layer (6) is formed together with silicon dioxide reserved at the bottom of the silicon carbide trench, and a polysilicon gate electrode, namely a trench gate (7), is formed through deposition and etching processes, as shown in fig. 13.
Step S12: silicon dioxide is deposited on the structure and etched to form an interlayer dielectric layer (9), the metal is stripped and rapid thermal annealing is carried out to form a source contact metal (10), as shown in figure 14.
Step S13: evaporating Al on the front surface and etching to form a metal pad (11), covering the passivation layer (12) and etching to form a window, sputtering drain metal on the back surface and then performing laser annealing to form drain metal (13), and obtaining the final device structure shown in FIG. 15.
The foregoing is a more detailed description of the invention in connection with specific/preferred embodiments and is not intended to limit the practice of the invention to those descriptions. It will be apparent to those skilled in the art that various substitutions and modifications can be made to the described embodiments without departing from the spirit of the invention, and these substitutions and modifications should be considered to fall within the scope of the invention. In the description herein, references to the description of the term "one embodiment," "some embodiments," "preferred embodiments," "an example," "a specific example," or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Claims (7)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110992436.3A CN113745338A (en) | 2021-08-27 | 2021-08-27 | Groove type silicon carbide MOSFET device structure and preparation method thereof |
| CN202210938098.XA CN115394853A (en) | 2021-08-27 | 2022-08-05 | A trench type silicon carbide MOSFET device structure and its preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110992436.3A CN113745338A (en) | 2021-08-27 | 2021-08-27 | Groove type silicon carbide MOSFET device structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113745338A true CN113745338A (en) | 2021-12-03 |
Family
ID=78733304
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110992436.3A Pending CN113745338A (en) | 2021-08-27 | 2021-08-27 | Groove type silicon carbide MOSFET device structure and preparation method thereof |
| CN202210938098.XA Pending CN115394853A (en) | 2021-08-27 | 2022-08-05 | A trench type silicon carbide MOSFET device structure and its preparation method |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210938098.XA Pending CN115394853A (en) | 2021-08-27 | 2022-08-05 | A trench type silicon carbide MOSFET device structure and its preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN113745338A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114496784A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Bottom protection grounding groove type silicon carbide MOSFET and preparation method thereof |
-
2021
- 2021-08-27 CN CN202110992436.3A patent/CN113745338A/en active Pending
-
2022
- 2022-08-05 CN CN202210938098.XA patent/CN115394853A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114496784A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Bottom protection grounding groove type silicon carbide MOSFET and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115394853A (en) | 2022-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102768994B (en) | Integration of schottky diode within power MOSFET | |
| CN107331616B (en) | A trench junction barrier Schottky diode and method of making the same | |
| CN111081759B (en) | Enhanced silicon carbide MOSFET device and manufacturing method thereof | |
| CN103094324B (en) | Trench-type insulated gate bipolar transistor and preparation method thereof | |
| CN105590844B (en) | The manufacturing method of super-junction structure deep trench | |
| JP2009200300A (en) | Semiconductor device, and method of manufacturing the same | |
| JP2008535213A (en) | Method for manufacturing a semiconductor device having a buried doped region | |
| JP2018152522A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| TW201434161A (en) | High-voltage fast recovery trench diode and preparation method thereof | |
| WO2023071284A1 (en) | Trench-gate semiconductor device and manufacturing method therefor | |
| JP2003086800A (en) | Semiconductor device and manufacturing method thereof | |
| CN118553617A (en) | Preparation method of trench gate silicon carbide VDMOS with internal current sharing | |
| CN110223959B (en) | Metal oxide semiconductor field effect transistor with deep and shallow grooves and preparation method thereof | |
| CN111326584B (en) | Silicon carbide MOSFET and preparation method thereof | |
| CN111129108A (en) | Transistor termination structure and method of making the same | |
| CN115241051A (en) | Silicon carbide power device and preparation method thereof | |
| CN118380321B (en) | Silicon carbide MOSFET with shielding area and manufacturing method thereof | |
| CN113745338A (en) | Groove type silicon carbide MOSFET device structure and preparation method thereof | |
| CN113517350A (en) | A low-voltage shielded gate MOSFET device and its manufacturing method | |
| CN116632041B (en) | Shielded gate trench field effect transistor structure and manufacturing method thereof | |
| US20220367710A1 (en) | Sic super junction trench mosfet | |
| CN216250738U (en) | Power semiconductor device and chip | |
| CN218385229U (en) | IGBT device and chip | |
| CN112420845B (en) | Trench power semiconductor device and manufacturing method | |
| CN112768356B (en) | Manufacturing method of trench gate IGBT |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20211203 |
|
| WD01 | Invention patent application deemed withdrawn after publication |