CN107359121B - Preparation method of VDMOS power device and VDMOS power device - Google Patents

Abstract

The present invention provides a preparation method of a VDMOS power device and a VDMOS power device, wherein the preparation method comprises: sequentially growing a gate oxide layer and a polycrystalline gate on a substrate formed with an epitaxial layer, and forming a The polycrystalline gate is oxidized to form an oxide layer; a silicon nitride layer is formed on the oxide layer to form a target substrate structure; on the basis of the target substrate structure, the VDMOS power device is completed. preparation. Through the technical scheme of the present invention, the production process flow of traditional VDMOS power devices can be effectively optimized, the problem of electrical parameters failure of the power devices caused by the narrow process window during the etching process of the Spacer process can be solved, and the high performance of the power devices can be ensured. performance, but also to reduce process costs.

Description

Preparation method of VDMOS power device and VDMOS power device

technical field

The invention relates to the technical field of semiconductors, in particular, to a preparation method of a VDMOS power device and a VDMOS power device.

Background technique

Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) combines the advantages of bipolar transistors and common MOS power devices. Whether switching applications or linear applications, VDMOS power devices are ideal power devices. VDMOS power devices are mainly used in motor speed regulation, inverters, uninterruptible power supplies, electronic switches, hi-fi, automotive electrical appliances and electronic ballasts. VDMOS power devices are divided into enhancement mode VDMOS power devices and depletion mode VDMOS power devices.

With the development of the field of semiconductor design and semiconductor technology, the current VDMOS power devices have developed towards the field of low cost and high performance. main subject. The production cost of the device is usually calculated according to the number of lithography. Therefore, with the development of the process field, it has become the mainstream solution to minimize the number of lithography in the device production process.

The current preparation methods of VDMOS power devices are shown in Figures 1a to 1i, which specifically include the following steps:

(1) As shown in Figure 1a, the gate oxide layer and polycrystalline gate of the power device are grown on the N-type epitaxial layer according to the traditional process, wherein the gate oxide layer is usually grown by thermal oxidation, and the thickness is usually 200 angstroms- 2000 angstroms, the thickness of the polycrystalline gate is usually 3000 angstroms-10000 angstroms, preferably 6000 angstroms.

(2) As shown in FIG. 1b, the polycrystalline gate electrode is oxidized, and the thickness of the obtained oxide layer is 5000 angstroms. During the oxidation process, the polycrystalline gate electrode will be reacted away by about 3000 angstroms.

(3) As shown in FIG. 1c, a photolithography layer is grown on the oxide layer, so as to perform photolithography processing on the oxide layer, the polycrystalline gate and the gate oxide layer according to the photolithography layer.

(4) As shown in FIG. 1d, under the blocking of the photolithography layer, the oxide layer, the polycrystalline gate and the gate oxide layer are etched, and the photolithography layer is removed after the etching is completed.

(5) As shown in FIG. 1e, the body region self-aligned implantation and drive-in of the power device are completed, and the source region self-aligned implantation is completed.

(6) As shown in Figure 1f, do LPTEOS Spacer (LPTEOS is mainly used for Spacer, and the Spacer process is used for self-alignment of source and drain region implantation and reducing the channel effect due to lateral diffusion of source and drain) deposition, using LPCVD ( LowPressure Chemical Vapor Deposition, low pressure chemical vapor deposition) method, deposit a layer of TEOS (tetraethoxysilane) on the surface of the device, usually with a thickness of 3000 angstroms to 4000 angstroms.

(7) As shown in Figure 1g, LPTEOS etching is performed on the TEOS layer, and the whole piece is etched. After etching, the oxide layer, the polycrystalline gate and the TEOS layer on the sidewall of the gate oxide layer will remain.

This step is the most difficult process. To ensure that the TEOS layer on the surface of the source region is etched cleanly, a certain amount of Over Etch must be added. The layer etching rate is inconsistent (the TEOS layer will be faster), so the TEOS layer on the sidewall of the poly gate will be etched away faster, and the worst case will become as shown in Figure 1h, at this time the poly gate will be The electrode has been exposed to the outside, and the subsequent filling of metal will directly lead to a short circuit between the gate and source of the device, and the device will fail.

(8) As shown in Fig. 1i, self-aligned silicon hole etching is performed on the LPTEOS etched device, and metal connection is completed.

Therefore, how to optimize the production process of traditional VDMOS power devices and solve the problem of failure of electrical parameters of power devices due to the narrow process window in the Spacer process etching process can not only ensure the high performance of power devices, but also reduce process costs , has become an urgent problem to be solved.

SUMMARY OF THE INVENTION

Based on the above problems, the present invention proposes a new preparation scheme for VDMOS power devices, which can effectively optimize the production process flow of traditional VDMOS power devices, and solve the problem of power devices caused by the narrow process window during the etching process of the Spacer process. The failure of electrical parameters can not only ensure the high performance of power devices, but also reduce process costs.

In view of this, an aspect of the present invention proposes a method for preparing a VDMOS power device, which includes: sequentially growing a gate oxide layer and a polycrystalline gate on a substrate formed with an epitaxial layer, and aligning the polycrystalline gate Oxidation is performed to form an oxide layer; a silicon nitride layer is formed on the oxide layer to form a target substrate structure; and the preparation of a VDMOS power device is completed on the basis of the target substrate structure.

In this technical solution, after the gate oxide layer, the polycrystalline gate and the oxide layer are sequentially grown on the epitaxial layer according to the traditional production process of VDMOS power devices, a silicon nitride layer is first grown on the surface of the oxide layer to form the target substrate structure to increase the etching height of the subsequent Spacer process, which is equivalent to widening the process window. In this way, the production process flow of traditional VDMOS power devices is effectively optimized, and the power consumption caused by the narrow process window during the Spacer process etching process is solved. The failure of electrical parameters of the device can not only ensure the high performance of the power device, but also reduce the process cost.

In the above technical solution, preferably, completing the preparation of the VDMOS power device on the basis of the target substrate structure specifically includes: growing a photolithography layer on the silicon nitride layer; The etching layer sequentially performs an etching process on the silicon nitride layer, the oxide layer, the polycrystalline gate electrode and the gate oxide layer; after the etching process is completed, the photolithography layer is removed.

In this technical solution, after the silicon nitride layer is formed on the surface of the oxide layer, a photolithography layer is grown thereon to complete the etching of the silicon nitride layer, the oxide layer, the polycrystalline gate and the gate oxide layer. After the etching is completed, the photolithography layer is removed, so as to obtain a better sidewall morphology and ensure the reliability of the preparation of the VDMOS power device.

In any of the above technical solutions, preferably, after removing the photolithography layer, the method further includes: depositing a TEOS layer on the etched target substrate structure.

In this technical solution, after the etching is completed and the photolithography layer is removed, LPTEOS Spacer deposition is performed to deposit a TEOS layer on the surface of the etched target substrate structure to ensure the reliability of preparing VDMOS power devices. sex.

In any of the above technical solutions, preferably, the etched target substrate structure is subjected to deposition processing by means of LPCVD.

In this technical solution, a TEOS layer is deposited on the surface of the etched target substrate structure by using the LPCVD method, so as to ensure the reliability of preparing the VDMOS power device.

In any of the above technical solutions, preferably, the thickness of the TEOS layer is between 3000 angstroms and 4000 angstroms.

In this technical solution, the thickness of the TEOS layer deposited on the surface of the etched target substrate structure is preferably between 3000 angstroms and 4000 angstroms, so as to ensure the reliability of preparing VDMOS power devices.

In any of the above technical solutions, preferably, after the TEOS layer is formed, the method further includes: performing an etching process on the TEOS layer, and only the silicon nitride layer and the oxide layer after the etching process are retained. layer, the polycrystalline gate and the TEOS layer at the sidewalls of the gate oxide layer.

In this technical solution, the Spacer process etching is performed on the TEOS layer formed on the surface of the etched target substrate structure to retain the silicon nitride layer, the oxide layer, the polycrystalline gate and the sidewalls of the gate oxide layer. Here, due to the existence of the silicon nitride layer, the height of the vertical TEOS layer is increased by 3000 angstroms to 4000 angstroms, which is equivalent to an increase in the etching process window, which ensures that the Spacer process can etch enough Over The amount of Etch will relatively slow down the etching rate, so that the polycrystalline gate will not be exposed after the etching is completed, which will lead to the short circuit of the gate and source of the device and the failure of the device after filling the metal, which is greatly optimized. The production process is improved to ensure the high performance of the power device.

In any of the above technical solutions, preferably, after the TEOS layer is etched, the method further includes: sequentially generating a device body region and a source region in the epitaxial layer, so that the source region and the TEOS layer are formed in sequence. contact.

In any of the above technical solutions, preferably, it further includes: after etching the source region, growing a layer of metal on the target substrate structure where the device body region and the source region are formed layer to complete the metal contact to complete the preparation of the VDMOS power device.

In this technical solution, after the TEOS layer is etched, the device body region, source region and metal layer of the VDMOS power device can be sequentially formed according to the traditional process to complete the metal contact and ensure the reliability of the preparation of the VDMOS power device. The preparation of VDMOS power device is completed.

Another aspect of the present invention provides a VDMOS power device, which is prepared by using the preparation method of a VDMOS power device according to any one of the above technical solutions.

In this technical solution, a gate oxide layer, a polycrystalline gate, and an oxide layer are sequentially formed on the epitaxial layer, and then a silicon nitride layer is formed first, so as to increase the etching height of the subsequent Spacer process and widen the process window, thereby effectively The production process flow of traditional VDMOS power devices is optimized, and the problem of electrical parameters failure of power devices caused by the narrow process window in the Spacer process etching process can be solved, which can not only ensure the high performance of power devices, but also reduce process costs.

In the above technical solution, preferably, the thickness of the silicon nitride layer is between 3000 angstroms and 4000 angstroms.

In this technical solution, the thickness of the silicon nitride layer grown on the oxide layer during the preparation of the VDMOS power device is preferably between 3000 angstroms and 4000 angstroms to ensure the reliability of preparing the VDMOS power device.

Through the technical solution of the present invention, the production process flow of traditional VDMOS power devices can be effectively optimized, the problem of electrical parameters failure of power devices caused by the narrow process window during the etching process of the Spacer process can be solved, and the high performance of the power devices can be ensured. performance, and can also reduce process costs.

Description of drawings

FIG. 1a to FIG. 1i show schematic schematic diagrams of the manufacturing method of the VDMOS power device in the related art;

2 shows a schematic flowchart of a method for manufacturing a VDMOS power device according to an embodiment of the present invention;

3 to 7 are schematic diagrams showing the principle of a method for fabricating a VDMOS power device according to an embodiment of the present invention.

Detailed ways

In order to understand the above objects, features and advantages of the present invention more clearly, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments may be combined with each other in the case of no conflict.

Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific details disclosed below. Example limitations.

FIG. 2 shows a schematic flowchart of a method for fabricating a VDMOS power device according to an embodiment of the present invention.

As shown in FIG. 2, a method for preparing a VDMOS power device according to an embodiment of the present invention includes:

Step 202, growing a gate oxide layer and a polycrystalline gate sequentially on the substrate formed with the epitaxial layer, and oxidizing the polycrystalline gate to form an oxide layer;

Step 204, forming a silicon nitride layer on the oxide layer to form a target substrate structure;

In step 206, the preparation of the VDMOS power device is completed on the basis of the target substrate structure.

In this technical solution, after the gate oxide layer, the polycrystalline gate and the oxide layer are sequentially grown on the epitaxial layer according to the traditional production process of VDMOS power devices, a silicon nitride layer is first grown on the surface of the oxide layer to form the target substrate structure to increase the etching height of the subsequent Spacer process, which is equivalent to widening the process window. In this way, the production process flow of traditional VDMOS power devices is effectively optimized, and the power consumption caused by the narrow process window during the Spacer process etching process is solved. The failure of electrical parameters of the device can not only ensure the high performance of the power device, but also reduce the process cost.

In the above technical solution, preferably, the step 206 specifically includes:

Step 2062, growing a photolithography layer on the silicon nitride layer;

Step 2064, performing etching processing on the silicon nitride layer, the oxide layer, the polycrystalline gate and the gate oxide layer in sequence according to the photolithography layer;

Step 2066, removing the photoresist layer after the etching process is completed.

In this technical solution, after the silicon nitride layer is formed on the surface of the oxide layer, a photolithography layer is grown thereon to complete the etching of the silicon nitride layer, the oxide layer, the polycrystalline gate and the gate oxide layer. After the etching is completed, the photolithography layer is removed, so as to obtain a better sidewall morphology and ensure the reliability of the preparation of the VDMOS power device.

In any of the above technical solutions, preferably, after the step 2066, it further includes:

Step 208, depositing a TEOS layer on the etched target substrate structure.

In this technical solution, after the etching is completed and the photolithography layer is removed, LPTEOS Spacer deposition is performed to deposit a TEOS layer on the surface of the etched target substrate structure to ensure the reliability of preparing VDMOS power devices. sex.

In any of the above technical solutions, preferably, in the step 208, the etched target substrate structure is subjected to a deposition process by means of LPCVD.

In this technical solution, a TEOS layer is deposited on the surface of the etched target substrate structure by using the LPCVD method, so as to ensure the reliability of preparing the VDMOS power device.

In any of the above technical solutions, preferably, the thickness of the TEOS layer in the step 208 is between 3000 angstroms and 4000 angstroms.

In this technical solution, the thickness of the TEOS layer deposited on the surface of the etched target substrate structure is preferably between 3000 angstroms and 4000 angstroms, so as to ensure the reliability of preparing VDMOS power devices.

In any of the above technical solutions, preferably, after the step 208, it further includes:

Step 210: Perform etching on the TEOS layer, and only retain the silicon nitride layer, the oxide layer, the polycrystalline gate, and all the sidewalls of the gate oxide layer after the etching process. Describe the TEOS layer.

In this technical solution, the Spacer process etching is performed on the TEOS layer formed on the surface of the etched target substrate structure to retain the silicon nitride layer, the oxide layer, the polycrystalline gate and the sidewalls of the gate oxide layer. Here, due to the existence of the silicon nitride layer, the height of the vertical TEOS layer is increased by 3000 angstroms to 4000 angstroms, which is equivalent to an increase in the etching process window, which ensures that the Spacer process can etch enough Over The amount of Etch will relatively slow down the etching rate, so that the polycrystalline gate will not be exposed after the etching is completed, which will lead to the short circuit of the gate and source of the device and the failure of the device after filling the metal, which is greatly optimized. The production process is improved to ensure the high performance of the power device.

In any of the above technical solutions, preferably, after the step 210, it further includes:

Step 212, generating a device body region and a source region in sequence on the epitaxial layer, so that the source region is in contact with the TEOS layer;

Step 214, after etching the source region, grow a metal layer on the target substrate structure formed with the device body region and the source region to complete metal contact to complete the VDMOS Fabrication of power devices.

In this technical solution, after the TEOS layer is etched, the device body region, source region and metal layer of the VDMOS power device can be sequentially formed according to the traditional process to complete the metal contact and ensure the reliability of the preparation of the VDMOS power device. The preparation of VDMOS power device is completed.

Another aspect of the present invention provides a VDMOS power device, which is prepared by using the preparation method of a VDMOS power device according to any one of the above technical solutions.

In this technical solution, a gate oxide layer, a polycrystalline gate, and an oxide layer are sequentially formed on the epitaxial layer, and then a silicon nitride layer is formed first, so as to increase the etching height of the subsequent Spacer process and widen the process window, thereby effectively The production process flow of traditional VDMOS power devices is optimized, and the problem of electrical parameters failure of power devices caused by the narrow process window in the Spacer process etching process can be solved, which can not only ensure the high performance of power devices, but also reduce process costs.

In the above technical solution, preferably, the thickness of the silicon nitride layer is between 3000 angstroms and 4000 angstroms.

In this technical solution, the thickness of the silicon nitride layer grown on the oxide layer during the preparation of the VDMOS power device is preferably between 3000 angstroms and 4000 angstroms to ensure the reliability of preparing the VDMOS power device.

The following will describe in detail a method for preparing a VDMOS power device according to an embodiment of the present invention with reference to FIGS. 3 to 7 , wherein the correspondence between the reference numerals and the component names in FIGS. 3 to 7 is:

11 epitaxial layer, 12 gate oxide layer, 13 polycrystalline gate, 14 oxide layer, 15 silicon nitride layer, 16 TEOS layer, 17 source region, 18 device body region, 19 metal layer.

As shown in FIG. 3, a gate oxide layer 12 and a polycrystalline gate 13 are formed on the epitaxial layer 11 (such as an N-type epitaxial layer) according to a conventional process, and the polycrystalline gate 13 is oxidized to form an oxide layer 14. A silicon nitride layer 15 is deposited over the oxide layer 14, and the thickness is usually in the range of 3000 angstroms to 4000 angstroms.

As shown in FIG. 4, the silicon nitride layer 15, the oxide layer 14, the polycrystalline gate 13 and the gate oxide layer 14 are etched. Therefore, since a thick silicon nitride layer is added in this step, it is equivalent to changing the Increasing the height of the subsequent spacer to the ground also widens the process window.

As shown in FIG. 5 , LPTEOS spacer deposition is performed by LPCVD, and a TEOS layer 16 is deposited on the surface of the device, and the thickness is usually 3000 angstroms to 4000 angstroms.

As shown in FIG. 6, the TEOS layer 16 (Spacer) is etched. In this step, the height of the vertical TEOS is increased by 3000 angstroms to 4000 angstroms, which is equivalent to increasing the process window so much, that is, there can be enough spacer during etching. Over Etch, there will be no electrical parameter failure problem.

As shown in FIG. 7 , the device can be fabricated according to the traditional process, including the following specific steps: generating a source region, a device body region, and producing a metal layer 18 on the surface to complete the diode fabrication.

In summary, based on the traditional VDMOS power device fabrication process, the process is optimized to solve the problems of narrow process window and device electrical parameters failure caused by the Spacer process etching process, and to ensure low cost.

The technical solutions of the present invention are described in detail above with reference to the accompanying drawings. Through the technical solutions of the present invention, the production process flow of traditional VDMOS power devices can be effectively optimized, and the electrical problems of the power devices caused by the narrow process window during the etching process of the Spacer process can be solved. The problem of the failure of performance parameters can not only ensure the high performance of the power device, but also reduce the process cost.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (7)

1. A preparation method of a VDMOS power device is characterized by comprising the following steps:

growing a gate oxide layer and a polycrystalline grid on a substrate with an epitaxial layer in sequence, and oxidizing the polycrystalline grid to form an oxide layer;

generating a silicon nitride layer on the oxide layer to form a target substrate structure;

finishing the preparation of the VDMOS power device on the basis of the target substrate structure;

the preparation of the VDMOS power device is completed on the basis of the target substrate structure, and specifically includes:

growing a photoetching layer on the silicon nitride layer;

etching the silicon nitride layer, the oxide layer, the polycrystalline grid and the grid oxide layer in sequence according to the photoetching layer;

removing the photoetching layer after the etching treatment is finished;

depositing a TEOS layer on the target substrate structure after etching treatment;

and carrying out deposition treatment on the target substrate structure after etching treatment in an L PCVD mode.

2. The method of claim 1, wherein the TEOS layer is between 3000 and 4000 angstroms thick.

3. The method for manufacturing a VDMOS power device according to claim 1, further comprising, after forming the TEOS layer:

and etching the TEOS layer, and only reserving the etched TEOS layer at the side walls of the silicon nitride layer, the oxide layer, the polycrystalline grid and the gate oxide layer.

4. The method for manufacturing a VDMOS power device according to claim 3, further comprising, after the etching treatment is performed on the TEOS layer:

and sequentially generating a device body region and a source region in the epitaxial layer, so that the source region is in contact with the TEOS layer.

5. The method for preparing the VDMOS power device according to claim 4, further comprising:

and after etching the source region, growing a metal layer on the target substrate structure on which the device body region and the source region are formed, and completing metal contact so as to complete the preparation of the VDMOS power device.

6. A VDMOS power device, characterized in that, it is prepared by the method of any claim 1 to 5.

7. The VDMOS power device of claim 6,

the silicon nitride layer has a thickness of between 3000 angstroms and 4000 angstroms.

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