CN106158961B - Fabrication method of planar VDMOS device - Google Patents

Abstract

The present invention provides a method for manufacturing a planar VDMOS device, comprising: providing a substrate, on which a gate oxide layer, a polysilicon layer and a first silicon nitride layer are formed in sequence; and removing the gate oxide outside the preset first region layer, the polysilicon layer and the first silicon nitride layer, leaving the gate oxide layer, the polysilicon layer and the first silicon nitride layer in the first region; the second silicon nitride layer is formed on the surface of the entire device, through the silicon nitride layer The gate is formed by etching back; the body region and the source region are formed by self-aligned implantation; the body region and the source region outside the gate are removed by etching, and the etching depth is greater than the depth of the body region; A buffer zone below the edge of the zone; a dielectric layer is deposited on the entire surface of the device, the dielectric layer in the preset third region is removed, and a dielectric layer surrounding part of the buffer zone is retained; and a metal layer is deposited. The manufacturing method of the planar VDMOS device provided by the present invention has the advantages of simple manufacturing process and low manufacturing cost.

Description

Fabrication method of planar VDMOS device

technical field

The invention relates to the technical field of semiconductor chip manufacturing technology, in particular to a manufacturing method of a planar VDMOS device.

Background technique

Vertical Double Diffusion Field Effect Transistor (VDMOS) is one of the most commonly used power transistors. As a voltage-controlled device, the channel formation is controlled by a gate voltage signal, thereby controlling the conduction of source and drain currents. VDMOS combines the advantages of bipolar transistors and ordinary MOS devices. Therefore, VDMOS is an ideal power device for both switching applications and linear applications.

In the existing VDMOS manufacturing process, the fabrication of the VDMOS active region generally requires methods such as photolithography, wet etching, dry etching, ion implantation, and ion drive to complete the fabrication. Among them, the photolithography processing of VDMOS takes place in the manufacturing process of the AA region, the polycrystalline layer, the source region, the contact hole and the metal layer, that is, the VDMOS needs to go through five photolithography steps to complete the manufacturing process.

The manufacturing process of the existing VDMOS manufacturing method is complicated, and the manufacturing cost is relatively high.

SUMMARY OF THE INVENTION

The invention provides a manufacturing method of a planar VDMOS device, which is used to solve the problems of complicated manufacturing process and high manufacturing cost in the existing manufacturing method.

The manufacturing method of the planar VDMOS device provided by the present invention includes:

a substrate is provided, and a gate oxide layer, a polysilicon layer and a first silicon nitride layer are sequentially formed on the surface of the substrate;

removing the gate oxide layer, the polysilicon layer and the first silicon nitride layer outside the predetermined first region to retain the gate oxide layer, the polysilicon layer and the first silicon nitride layer in the first region ;

A second silicon nitride layer is formed on the entire surface of the device, the second silicon nitride layer in a predetermined area is removed, and all the gate oxide layer, the polysilicon layer and the sidewalls of the first silicon nitride layer remain. the second silicon nitride layer to form a gate;

forming a body region and a source region of the planar VDMOS device by self-aligned implantation;

By etching, the body region and the source region located in the preset second region are removed, and the body region and the source region located under the gate are retained, and the etching depth is greater than the depth of the body region ;

forming a buffer zone below the edge of the body region;

depositing a dielectric layer on the entire surface of the device, removing the dielectric layer in the preset third region, and retaining the dielectric layer surrounding part of the buffer zone;

A metal layer is deposited, and photolithography and etching of the metal layer are completed to form source metal.

The method for fabricating a planar VDMOS device provided by the present invention is to sequentially form a gate oxide layer, a polysilicon layer and a first silicon nitride layer on the surface of a substrate, and separate the gate oxide layer, polysilicon layer and polysilicon outside the preset first area. layer and the first silicon nitride layer are removed to form a gate; a body region and a source region are formed by self-aligned implantation; and a buffer zone is formed under the edge of the body region by an etching method, and finally a dielectric is deposited The manufacturing of the planar VDMOS device is completed by the method of layering, etching and depositing a metal layer, the manufacturing process is relatively simple, and the cost is low. Moreover, by introducing a buffer under the body region, the voltage resistance of the device is ensured, and the on-resistance of the device is also reduced, thereby reducing the power consumption of the device.

Description of drawings

1 is a schematic flowchart of a method for fabricating a planar VDMOS device provided in Embodiment 1 of the present invention;

2 is a schematic structural diagram of a substrate provided in Embodiment 1 of the present invention;

FIG. 3 is a schematic structural diagram of the first embodiment of the present invention after removing the gate oxide layer, the polysilicon layer and the first silicon nitride layer outside the preset first region;

FIG. 4 is a schematic structural diagram after forming a second silicon nitride layer according to Embodiment 1 of the present invention;

FIG. 5 is a schematic view of the structure after the gate is formed according to the first embodiment of the present invention;

6 is a schematic view of the structure after forming a body region and a source region according to Embodiment 1 of the present invention;

FIG. 7 is a schematic structural diagram of the first embodiment of the present invention after the buffer zone is formed;

FIG. 8 is a schematic structural diagram of the first embodiment of the present invention after the dielectric layer is deposited;

FIG. 9 is a schematic structural diagram of the dielectric layer after etching according to an embodiment of the present invention;

FIG. 10 is a schematic flowchart of a method for fabricating a planar VDMOS device according to Embodiment 2 of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The following embodiments will describe the method of fabricating the active region of the planar VDMOS device.

1 is a schematic flowchart of a method for fabricating a planar VDMOS device according to Embodiment 1 of the present invention. As shown in FIG. 1 , the method for fabricating a planar VDMOS device in this embodiment includes the following steps:

Step 101 , providing a substrate, and a gate oxide layer, a polysilicon layer and a first silicon nitride layer are sequentially formed on the surface of the substrate.

As shown in FIG. 2 , the substrate provided in this embodiment sequentially includes an N-type substrate 1 and an N-type epitaxial layer 2 from bottom to top, and a gate oxide layer 3 and a polysilicon layer are sequentially formed on the surface of the N-type epitaxial layer 2 . layer 4 and first silicon nitride layer 5 .

Step 102: Remove the gate oxide layer, the polysilicon layer and the first silicon nitride layer outside the preset first region, so as to retain the gate oxide layer, the polysilicon layer and the first nitrogen layer in the first region Silicon layer.

Specifically, a first region 6 is preset on the surface of the first silicon nitride layer 5 , a photoresist is formed on the first silicon nitride layer 5 on the first region 6 , and a photoresist is formed on the first region 6 . Under the mask of the photoresist, the gate oxide layer 3, the polysilicon layer 4 and the first silicon nitride layer 5 outside the first region 6 are etched, and the N-type epitaxial layer of the substrate is exposed. After the surface of 2, the etching is stopped, the photoresist is removed, and the structure after etching is shown in FIG. 3 .

Step 103 , forming a second silicon nitride layer on the surface of the entire device, removing the second silicon nitride layer in the preset area, and leaving the gate oxide layer, the polysilicon layer and the sidewalls of the first silicon nitride layer A gate is formed on the second silicon nitride layer.

Specifically, as shown in FIG. 4 , a second silicon nitride layer 7 is formed on the surface of the entire device, and then silicon nitride is etched back to the surface of the N-type epitaxial layer 2 and the The second silicon nitride layer 7 on the surface of the first silicon nitride layer 5 on the first region 6 is etched away, and only the gate oxide layer 3, the polysilicon layer 4 and the first silicon nitride layer 5 remain. The second silicon nitride layer 7 on the sidewall is used to protect the pattern formed in step 102 to form a gate. The structure after forming the gate is shown in FIG. 5 .

Step 104 , forming a body region and a source region of the planar VDMOS device through self-aligned implantation.

Specifically, as shown in FIG. 6 , self-aligned P-type impurity implantation is performed on the region where the body region is to be formed, and the drive-in is completed to form a first P-type implantation layer to form the body region 21 ; the body region 21 is to be formed. Self-aligned N+ type impurity implantation is performed on the source region, and a first N+ type implantation layer is formed by driving in, so as to form the source region 22 , and the body region 21 surrounds the source region 22 .

Step 105: Remove the body region and the source region located in the preset second region by etching, retain the body region and the source region located under the gate, and the etching depth is greater than the body region the depth of the area.

Specifically, as shown in FIG. 6 , under the mask of the first silicon nitride layer 5 and the second silicon nitride layer 7 , trench etching is performed on the body region 21 and the source region 22 in the preset second region 8 Etching, the body region 21 and the source region 22 under the second region 8 are etched away, and only the body region 21 and the source region 22 under the gate remain, and continue to the lower part of the second region 8 Etching until part of the N-type epitaxial layer 2 is etched away, so that the depth of the formed trench is greater than the depth of the body region 21 . The depth of the lower etching is set by those skilled in the art according to requirements, and is not specifically limited here.

Here, the etching depth of the trench is greater than the depth of the body region, which provides a space guarantee for the introduction of the buffer layer.

Step 106 , forming a buffer zone below the edge of the body region.

Specifically, as shown in FIG. 7 , by means of oblique implantation, the device processed in step 105 is subjected to oblique implantation of P-type impurities to form a formation located under the edge of the body region 21 and on the surface of the substrate N-type epitaxial layer 2 Inside the buffer zone 23, the surface of the substrate N-type epitaxial layer 2 is etched, and the buffer zone 23 outside the body region 21 is removed until the surface of the substrate N-type epitaxial layer 2 is exposed. , only the buffer area 23 located below the edge of the body region 21 is retained, and the buffer area 23 finally formed is a columnar structure.

In the prior art, the voltage withstand performance of the planar VDMOS device is mainly achieved by extending the depletion layer of the P-type body region. While ensuring the device voltage resistance, the resistivity of the epitaxial layer cannot be made very low, and the on-resistance of the device is relatively low. high, the power consumption of the device is relatively large. In this embodiment, a buffer layer is introduced under the edge of the body region. When the device is reverse biased, the entire buffer layer is fully depleted to play a role in withstand voltage. Therefore, the resistivity of the epitaxial layer can be Very high, the on-resistance of the device is low, which in turn can reduce the power consumption of the device.

Step 107 , depositing a dielectric layer on the entire surface of the device, removing the dielectric layer in the preset third region, and retaining the dielectric layer surrounding part of the buffer zone.

Specifically, as shown in FIG. 8 , a dielectric layer 9 is first deposited on the surface of the entire device until the dielectric layer 9 fills the trenches, wherein the dielectric layer 9 may be an oxide. After the dielectric layer 9 is generated, the dielectric layer 9 on the surface of the first silicon nitride layer 5 and part of the dielectric layer 9 in the trench are removed by wet etching, wherein the remaining dielectric layer 9 in the trench is removed. The height of part of the dielectric layer 9 is smaller than the height of the buffer layer 23 , and the remaining part of the dielectric layer 9 surrounds part of the buffer layer 23 . The structure formed after etching the dielectric layer 9 is shown in FIG. 9 .

Step 108 , depositing a metal layer, and completing photolithography and etching of the metal layer to form a source metal.

The formation method of the source metal is the same as that in the prior art, and details are not repeated here.

In the method for fabricating a planar VDMOS device provided in this embodiment, a gate oxide layer, a polysilicon layer and a first silicon nitride layer are sequentially formed on the surface of the substrate, and the gate oxide layer, The polysilicon layer and the first silicon nitride layer are removed to form a gate; a body region and a source region are formed by self-aligned implantation; and a buffer zone is formed under the edge of the body region by an etching method, and finally the deposition The fabrication of the planar VDMOS device is completed by means of a dielectric layer, etching, and depositing a metal layer, and the fabrication process is relatively simple and the cost is low. Moreover, by introducing a buffer under the body region, the voltage resistance of the device is ensured, and the on-resistance of the device is also reduced, thereby reducing the power consumption of the device.

FIG. 10 is a schematic flowchart of a method for fabricating a planar VDMOS device according to Embodiment 2 of the present invention. As shown in FIG. 10 , this embodiment further includes step 100 before step 101 above.

In step 100, the gate oxide layer, the polysilicon layer and the first silicon nitride layer are sequentially formed on the surface of the N-type epitaxial layer.

Specifically, on the surface of the N-type epitaxial layer 2 , a gate oxide layer 3 , a polysilicon layer 4 and a first silicon nitride layer 5 are sequentially formed in order from bottom to top. Wherein, the generation method may adopt a generation method such as deposition, which is not specifically limited here.

In this embodiment, the gate oxide layer 3 is sequentially formed on the surface of the N-type epitaxial layer 2, and the polysilicon layer 4 and the first silicon nitride layer 5 provide a structural basis for the subsequent fabrication method of this embodiment.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (6)

1. a method for making a planar VDMOS device, is characterized in that, comprising: a substrate is provided, and a gate oxide layer, a polysilicon layer and a first silicon nitride layer are sequentially formed on the surface of the substrate; removing the gate oxide layer, the polysilicon layer and the first silicon nitride layer outside the predetermined first region to retain the gate oxide layer, the polysilicon layer and the first silicon nitride layer in the first region ; A second silicon nitride layer is formed on the surface of the entire device, and the second silicon nitride layer in the preset area is removed, and only the gate oxide layer, the polysilicon layer and the sidewalls of the first silicon nitride layer remain. the second silicon nitride layer to form a gate; forming a body region and a source region of the planar VDMOS device by self-aligned implantation; By etching, the body region and the source region located in the preset second region are removed, and only the body region and the source region located under the gate are retained, and the etching depth is greater than that of the body region depth; forming a buffer zone below the edge of the body region; depositing a dielectric layer on the entire surface of the device, removing the dielectric layer in the preset third region, and retaining the dielectric layer surrounding part of the buffer zone; depositing a metal layer, and completing photolithography and etching of the metal layer to form source metal; Wherein, forming the buffer zone below the edge of the body region includes: forming a buffer zone below the edge of the body region and within the surface of the substrate by oblique implantation; By etching the surface of the substrate, the buffer zone outside the body region is removed, and only the buffer zone below the edge of the body region remains. 2. The method for fabricating a planar VDMOS device according to claim 1, wherein the removing the gate oxide layer, the polysilicon layer and the first silicon nitride layer outside the preset first region comprises: forming a photoresist on the first silicon nitride layer on the first region; Under the mask of photoresist, the gate oxide layer, the polysilicon layer and the first silicon nitride layer located outside the first region are etched to expose the surface of the substrate; The photoresist is removed. 3. The method for fabricating a planar VDMOS device according to claim 1, wherein said self-aligned implantation forms a body region and a source region of the planar VDMOS device, comprising: performing self-aligned P-type impurity implantation on the region where the body region is to be formed, and completing the drive-in to form a first P-type implantation layer to form the body region; Self-aligned N+ type impurity implantation is performed on the region where the source region is to be formed, and drive-in is completed to form a first N+ type implantation layer, so as to form the source region, and the body region surrounds the source region. 4. The method for fabricating a planar VDMOS device according to claim 1, wherein the removing the dielectric layer in the preset third region comprises: Wet etching is used to remove the dielectric layer in the third region. 5. The method for fabricating a planar VDMOS device according to any one of claims 1-4, characterized in that, before the substrate is provided, further comprising: The gate oxide layer, the polysilicon layer and the first silicon nitride layer are sequentially formed on the surface of the N-type epitaxial layer. 6. The method for fabricating a planar VDMOS device according to any one of claims 1-4, wherein the removing the second silicon nitride layer in the preset area comprises: By etching back, the second silicon nitride layer in the predetermined area is removed.

Images