CN114038751A

CN114038751A - Manufacturing method of shielded gate MOSFET device with upper and lower structures

Info

Publication number: CN114038751A
Application number: CN202111158564.4A
Authority: CN
Inventors: 陈雪萌; 王艳颖; 钱晓霞; 汤艺
Original assignee: Shanghai Daozhi Technology Co ltd
Current assignee: Shanghai Daozhi Technology Co ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2022-02-11
Anticipated expiration: 2041-09-30
Also published as: CN114038751B

Abstract

The invention discloses a method for manufacturing a shielded gate MOSFET with an upper and lower structure. The manufacturing method comprises the steps of: performing trench etching on a selected epitaxial silicon substrate; preparing a field by thermal oxidation or thermal oxidation plus depositing an oxide layer. Oxide layer; etch back to the silicon surface for the first time after filling the gate polysilicon; deposit a silicon nitride hard mask layer, then do active area lithography and etching, leaving an active area on the silicon nitride layer window. After that, the field oxide layer is wet-etched in the active area window, and the second shield gate polysilicon is etched back. Use wet etching to remove the oxide layer on the silicon surface and part of the field oxide layer in the trench, so that the height difference between the shield gate and the field oxide layer in the trench is within 0.2 microns; then oxidize the sidewall of the trench and the shield gate at the same time , the gate oxide layer and the gate oxide layer are formed; the gate polysilicon is filled and etched back to form the control gate.

Description

Manufacturing method of shielded gate MOSFET device with upper and lower structures

Technical Field

The invention relates to the technical field of design and manufacture of a shielded gate MOSFET (SGT-MOSFET) device, in particular to a method for manufacturing a shielded gate MOSFET device with an upper structure and a lower structure.

Background

Compared with the traditional trench MOSFET, the shielded gate MOSFET has the advantages of low on-resistance and low switching loss, so that the application of the shielded gate MOSFET in the middle and low voltage power semiconductor market is gradually increased. The grid electrode of the shielding grid groove type MOSFET structure simultaneously comprises the shielding grid and the control grid, the existence of the shielding grid enables the longitudinal electric field of the device to be distributed like a rectangle when the device is broken down, and compared with the traditional groove type MOSFET, the device can obtain higher breakdown voltage by applying epitaxy with smaller resistivity, so that the device has smaller on-resistance. Shielded gate MOSFET devices are generally classified into an up-down structure and a left-right structure according to the relative positions of the shielded gate and the control gate in the trench. For a shielded gate MOSFET device with an upper structure and a lower structure, two mature manufacturing processes exist at present, and the two processes are mainly different in the process method and the step of manufacturing an Inter Poly Oxide (Inter Poly Oxide) after a shielded gate is formed. One method is to form a shield grid by depositing and etching back polysilicon of the shield grid into a groove, then filling the groove on the shield grid by HDP, etching back to a certain depth to form an inter-grid oxide layer, and then forming a gate oxide layer on the side wall of the groove by thermal oxidation. The other method is that the shielding grid polysilicon is deposited and etched back into the groove to form the shielding grid, then the field oxide layer wet etching is carried out, a grid oxide layer and an inter-grid oxide layer are formed on the side wall of the groove and the top end of the shielding grid through thermal oxidation, and the control grid surrounds the upper part of the shielding grid like a top cap, so that the capacitance area between the shielding grid and the control grid is large, the input capacitance of the device is relatively large, and meanwhile, a sharp corner also exists at the bottom of the control grid, the electric leakage between the shielding grid and the control grid is easy to increase, and the reliability of the device is reduced.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a shielded gate MOSFET device with a top-bottom structure, which can effectively reduce the production cost, form an inter-gate oxide layer with good quality and uniformity, and reduce the capacitance of the device, and has the advantages of simple and easy manufacturing method, safety and reliability.

The invention aims to complete the technical scheme that a manufacturing method of a shielded gate MOSFET device with an upper structure and a lower structure comprises the following steps:

1) depositing an oxide layer on the selected N epitaxial silicon substrate as a hard mask, photoetching and deep trench etching on the N epitaxial silicon substrate by using a first mask plate, and simultaneously forming trenches of a cell region and a terminal region;

2) preparing a field oxide layer with corresponding thickness according to the requirement of the breakdown voltage of a product;

3) depositing polycrystalline silicon, carrying out first polycrystalline silicon back etching to form a shielding grid close to the silicon surface, and then carrying out chemical mechanical polishing to enable the thickness of an oxide layer on the silicon surface to be less than 2000A so as to reduce lateral etching during subsequent wet etching;

4) depositing a silicon nitride layer, wherein the thickness of the silicon nitride layer is 1000-3000A;

5) photoetching the upper part of the groove of the active area by using a second mask, and removing the exposed silicon nitride layer by dry etching;

6) removing the field oxide layer on the side wall of the groove of the active region by wet etching, wherein the depth of the etched oxide layer in the groove is 0.5-1.5 um, and the depth is determined by the designed breakdown voltage of a device and the optimal length of the groove;

7) performing secondary dry etching on the polycrystalline silicon in the groove of the primitive cell region to enable the polycrystalline silicon layer to be 0.1-0.3 microns lower than the field oxide layer;

8) wet etching is carried out to remove the silicon nitride layer, and then wet etching is carried out to remove the oxide layer on the silicon surface, so that the height of the polysilicon shielding gate in the groove, which is higher than or lower than the field oxide layer, is controlled within 0.2 micron;

9) forming a gate oxide layer on the side wall of the trench by using a thermal oxidation method, and simultaneously forming an inter-gate oxide layer on the top of the polysilicon shielding gate;

10) depositing gate polysilicon, and etching the gate polysilicon to the surface of the silicon by utilizing chemical mechanical polishing or wet etching to form a control gate of the device;

11) and carrying out subsequent process treatment to finish the manufacture of the shielded gate MOSFET device.

Further, the subsequent process treatment in the step 11) comprises the following steps:

12) carrying out body region injection and annealing to form a body region with the opposite conductivity type to the substrate and the epitaxial conductivity type;

13) using a third mask to carry out source region photoetching, injecting impurities with the same conductivity type as the substrate and the epitaxy, and annealing to form a heavily doped source region;

14) depositing a dielectric layer, then using a fourth mask to carry out contact hole photoetching, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole;

15) sputtering top metal, and photoetching and etching by using a fifth mask to form the top metal;

16) depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using a sixth mask to finish the manufacturing of the top layer structure;

17) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form the drain electrode of the device.

Further, in step 3), depositing polysilicon, performing first polysilicon back etching to approach the silicon surface, and then performing chemical mechanical polishing to make the thickness of the oxide layer on the silicon surface less than 2000A, so as to reduce lateral etching during subsequent wet etching.

Further, in the step 7), silicon nitride is used as a hard mask in the second dry etching of the polysilicon, and the polysilicon layer is lower than the field oxide layer by 0.1um to 0.3 micron after etching.

Further, in step 8), the silicon nitride layer is removed by wet etching, and then the oxide layer on the silicon surface is removed by wet etching, so that the difference between the height of the polysilicon shield gate in the trench and the height of the field oxide layer is within 0.2 μm.

The invention has the beneficial technical effects that: the method comprises the steps of carrying out first etching back on the shield grid polycrystalline silicon to the silicon surface, depositing a silicon nitride layer to serve as a hard mask, carrying out field oxide layer etching on a groove in a primitive cell region, carrying out second etching back on the shield grid polycrystalline silicon, carrying out field oxide layer wet etching, forming a structure with the height difference between the shield grid polycrystalline silicon and the field oxide layer within 0.2 micrometer in the groove in the primitive cell region, and then generating a gate oxide layer and an inter-grid oxide layer (IPO) through thermal oxidation. Compared with the traditional manufacturing method, the shielding gate device formed by the manufacturing method has smaller overlapping area of the shielding gate and the control gate, so that the capacitance of the device is reduced; in addition, compared with the traditional manufacturing method for forming the inter-gate oxide layer by filling and etching through HDP, the manufacturing method has the advantages that the cost is low, and the problem of forming sharp corners at the lower end of the control gate is solved. Meanwhile, the preparation method provided by the invention is compatible with the existing process steps, so that the production cost is effectively reduced, and the whole manufacturing process is safe and reliable.

Drawings

FIG. 1 is a schematic diagram of deep trench etching;

FIG. 2 is a schematic diagram illustrating the growth of a field oxide layer;

FIG. 3 is a schematic diagram of the shield gate polysilicon filling and etch back;

FIG. 4 is a schematic illustration of silicon nitride deposition;

FIG. 5 is a schematic diagram of a silicon nitride photolithography process;

FIG. 6 is a schematic diagram illustrating etching of a field oxide layer;

FIG. 7 is a schematic diagram of a shield gate polysilicon etching process;

FIG. 8 is a schematic diagram of silicon nitride removal and oxide layer removal;

FIG. 9 is a schematic illustration of gate oxide and intergate oxide growth;

fig. 10 is a schematic diagram of the control gate polysilicon fill and etch back.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood by those skilled in the art, the present invention is further described with reference to the accompanying drawings and examples.

As shown in fig. 1-10, the present invention provides a method for manufacturing a shielded gate MOSFET device with a top-bottom structure, and particularly provides a unique manufacturing method from the stage after the deposition of the shielded gate to the stage of forming the control gate. After the shielding grid is filled and etched back to the silicon surface for the first time, a silicon nitride layer is deposited to be used as a hard mask, the silicon nitride layer and the field oxide layer are etched on the top of a groove in a primitive cell region, polysilicon etching of the shielding grid is carried out for the second time, and then an oxide layer is grown on the side wall of the groove and the top of the shielding grid by utilizing a thermal oxidation process to form a grid oxide layer and an inter-grid oxide layer (IPO) of the device. The preparation method provided by the invention avoids the traditional mode of forming an inter-gate oxide layer by HDP filling, and the specific preparation method comprises the following steps:

1) depositing an oxide layer with the thickness of 0.5-1 um on the selected N epitaxial silicon substrate 2 as a hard mask, photoetching and deep groove etching on the N epitaxial silicon substrate 2 by using a first mask plate of the invention, and simultaneously forming a groove 3 of a cell region and a terminal region; as shown in fig. 1.

2) Preparing a field oxide layer 4 with a corresponding thickness according to the requirement of the breakdown voltage of a product, wherein the field oxide layer 4 can be formed by thermal oxidation or by a thermal oxidation plus deposition oxide layer; as shown in fig. 2.

3) Depositing polycrystalline silicon, carrying out first back etching on the polycrystalline silicon to form a shielding grid 5 close to the silicon surface, and then, carrying out chemical mechanical polishing to enable the thickness of an oxide layer on the silicon surface to be less than 2000A so as to reduce the lateral etching during subsequent wet etching; as shown in fig. 3.

4) Depositing a silicon nitride layer 6 as a hard mask, wherein the thickness of the silicon nitride layer 6 is about 1000-3000A; as shown in fig. 4.

5) Photoetching the upper part of the groove of the active area by using a second mask plate of the invention, and removing the exposed silicon nitride layer 6 by dry etching; as shown in fig. 5.

6) Removing the field oxide layer 4 on the side wall of the groove of the active region by wet etching, wherein the depth of the oxide layer 4 etched in the groove is 0.5-1.5 um, and the depth is determined by the designed breakdown voltage of a device and the optimal length of the channel; as shown in fig. 6.

7) Performing secondary dry etching on the polycrystalline silicon in the groove of the cell region, wherein silicon nitride is used as a hard mask in the dry etching, so that the polycrystalline silicon layer is lower than the field oxide layer 4, and the height difference between the polycrystalline silicon layer and the field oxide layer 4 is about 0.1-0.3 um; as shown in fig. 7.

8) Wet etching is carried out to remove the silicon nitride layer, and then wet etching is carried out to remove the oxide layer on the silicon surface, so that the height difference between the polysilicon shielding gate in the groove and the field oxide layer 4 is controlled within 0.2 micron; as shown in fig. 8.

9) Forming a gate oxide layer 8 on the side wall of the trench by a thermal oxidation method, and simultaneously forming an inter-gate oxide layer 7 on the top of the polysilicon shielding gate; as shown in fig. 9.

10) Depositing gate polysilicon, and etching the gate polysilicon to the surface of the silicon by using chemical mechanical polishing or wet etching to form a control gate 9 of the device; as shown in fig. 10. The top of the shielding grid MOSFET device formed by the manufacturing method is almost parallel to the bottom of the control grid, so that the area of capacitance between grids is small, and the capacitance is correspondingly low.

11) Carrying out subsequent process treatment to complete the manufacture of the shielded gate MOSFET device, wherein the subsequent process treatment comprises body region injection and annealing; photoetching a source region and injecting the source region; depositing a dielectric layer, photoetching a contact hole, and etching the dielectric layer; sputtering top metal, and photoetching and etching the top metal; depositing a passivation layer, and photoetching the passivation layer to finish the manufacture of the top layer structure; then, wafer thinning, back metal deposition and the like are carried out, and the method specifically comprises the following steps:

17) the back of the silicon chip is thinned to a specific thickness, and back metal is deposited by a sputtering or evaporation method to form the drain electrode 1 of the device.

According to the invention, after the polysilicon is filled in the groove, the polysilicon is etched back for the first time, the silicon nitride layer is deposited to be used as a hard mask, then the field oxide layer is etched, the shielded gate polysilicon etching is carried out for the second time, the oxide layer is etched by a wet method again, and then the gate oxide layer and the inter-gate oxide layer (IPO) are generated by thermal oxidation, so that the inter-gate oxide layer with better quality and uniformity is formed, meanwhile, the overlapping area of the shielded gate and the control gate in the traditional manufacturing method is reduced, and the capacitance of the device is correspondingly reduced; in addition, compared with the traditional manufacturing method for forming the inter-gate oxide layer by filling and etching through HDP, the manufacturing method has the advantages that the cost is low, and the problem of forming sharp corners at the lower end of the control gate is solved. Meanwhile, the preparation method provided by the invention is compatible with the existing process steps, so that the production cost is effectively reduced, and the whole manufacturing process is safe and reliable.

The specific embodiments described herein are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. the manufacture method of the shielded gate MOSFET device of the upper and lower structure, it is characterized in that: described manufacture method comprises the steps:

1) Deposit an oxide layer on the selected N epitaxial silicon substrate as a hard mask, use the first mask to photolithography and etch on the N epitaxial silicon substrate and form the original cell area and the terminal area at the same time deep grooves;

2) Prepare a field oxide layer with a corresponding thickness according to the requirements of the breakdown voltage of the product;

3) Deposit polysilicon, perform the first etchback of polysilicon close to the silicon surface to form a shield gate, and then make the oxide layer thickness on the silicon surface less than 2000A through chemical mechanical polishing, in order to reduce the lateral etching during subsequent wet etching;

4) The silicon nitride layer is deposited, and the thickness of the silicon nitride layer is 1000A~3000A;

5) Use the second mask to perform photolithography on the top of the trench in the active area, and dry-etch to remove the exposed silicon nitride layer;

6) Remove the field oxide layer on the trench sidewall of the active area by wet etching. The depth of the oxide layer etched in the trench is 0.5um~1.5um. The length is optimal to decide;

7) The second dry etching is performed on the polysilicon in the trenches of the original cell region, so that the polysilicon layer in the trenches of the original cell region is 0.1-0.3 microns lower than the field oxide layer;

8) The silicon nitride layer is removed by wet etching, and then the oxide layer on the silicon surface is removed by wet etching, so that the height difference between the polysilicon shielding gate and the field oxide layer in the trench is within 0.2 microns;

9) A gate oxide layer is formed on the sidewall of the trench by thermal oxidation, and an inter-gate oxide layer is formed on the top of the polysilicon shielding gate at the same time;

10) Deposit gate polysilicon, and use chemical mechanical polishing or wet etching to etch the gate polysilicon to the silicon surface to form the control gate of the device;

11) Follow-up processing is performed to complete the fabrication of the shielded gate MOSFET device.

2 . The method for manufacturing a shielded gate MOSFET device with an upper and lower structure according to claim 1 , wherein the subsequent processing in the step 11) includes the following steps: 3 .

12) Perform body region implantation and annealing to form a body region with the opposite conductivity type to that of the substrate and epitaxy;

13) Use the third mask for source area lithography and implant impurities of the same conductivity type as the substrate and epitaxy and anneal to form a heavily doped source area;

14) Deposit a dielectric layer, then use the fourth mask to perform contact hole lithography, and etch to form source, gate and shielded gate contact holes;

15) Sputter the top metal, use the fifth mask to photolithography and etch to form the top metal;

16) Deposit an oxide layer as a passivation layer, and use the sixth mask to etch the passivation layer to complete the fabrication of the top layer structure;

17) Thin the backside of the silicon wafer to a specific thickness, and deposit the backside metal by sputtering or evaporation to form the drain of the device.

3. The method for fabricating a shielded gate MOSFET device with an upper and lower structure according to claim 1 or 2, characterized in that: in step 3), in the process of depositing polysilicon, the polysilicon is etched back close to the silicon surface for the first time, and then chemical mechanical Polishing makes the oxide layer thickness on the silicon surface less than 2000A, in order to reduce lateral etching during subsequent wet etching.

4. The method for manufacturing a shielded gate MOSFET device with an upper and lower structure according to claim 1 or 2, wherein in step 7), silicon nitride is used as a hard mask in the dry etching, and the active After the polysilicon in the area trench is etched back for the second time, the polysilicon layer is lower than the field oxide layer by 0.1um~0.3um.

5 . The method for fabricating a shielded gate MOSFET device with an upper and lower structure according to claim 1 , wherein in step 8 ), the silicon nitride layer is removed by wet etching, and then silicon is removed by wet etching. 6 . The oxide layer on the surface makes the difference between the height of the polysilicon shielding gate in the trench and the height of the field oxide layer within 0.2 microns.