CN108389800A - The manufacturing method of shield grid trench FET - Google Patents

Abstract

The present invention provides a kind of manufacturing method of shield grid trench FET, and high-density plasma is used when manufacturing the isolating oxide layer of shield grid trench FET（HDP）, and wet etching treatment is carried out before depositing the layer, utilize high-density plasma（HDP）The deposit feature of layer, makes its filling have peculiar pattern：Middle flat in groove, groove both sides are in spike, the planarization process before the etching then to discard tradition, such as chemically-mechanicapolish polish（CMP）Ended, but direct wet etching treatment, obtain the target depth of isolating oxide layer in the removal and groove of isolating layer on top simultaneously, reach the process goal effect essentially identical with common process, process costs and process time are greatly reduced, is with a wide range of applications in semiconductor device design and manufacturing field.

Description

Manufacturing method of shielded gate trench field effect transistor

technical field

The invention belongs to the field of design and manufacture of semiconductor devices, in particular to a method for manufacturing a shielded gate trench field effect transistor.

Background technique

Shielded gate trench MOSFET is currently the most advanced power MOSFET device technology, which can realize low on-resistance (Rdson) and low reverse recovery capacitance (Crss) at the same time, thereby reducing the conduction loss and switching loss of the system at the same time, and improving System usage efficiency.

As shown in Figure 1, taking an N-type device as an example, the unit structure of an existing common shielded gate trench (SGT) MOSFET includes:

The lightly doped N ^- type epitaxial layer 104 is formed on the heavily doped N ⁺⁺ type silicon substrate 102, and the metal drain 100 is formed under the heavily doped N ⁺⁺ type silicon substrate 102;

The deep trench 106 is formed in the lightly doped N ^- type epitaxial layer 104, and the trench 106 has a shielding oxide layer 108 on the side wall, and the trench 106 is filled with shielding polysilicon 110 and gate polysilicon 116; shielding polysilicon 110 and gate There is an oxide layer 112 isolation between the polysilicon 116;

The P-type body region 118 is formed on the surface of the lightly doped N ^- type epitaxial layer 104, and the source region 120 is formed in the P-type body region 118; the contact hole 124 enters the P-type body region 118 through the oxide dielectric layer 122 and the source region 120; The metal source 130 is disposed on the contact hole 124 and the oxide dielectric layer 122;

The gate polysilicon 116 is drawn out at the end of the trench 106 through a layout layout (not shown), the shielding polysilicon 110 is connected to the source 120 through a layout layout, and the source 120 and the P-type body region 118 are jointly drawn out through a metal source 130 .

As shown in Figures 2a to 2h, taking an N-type device as an example, the main steps of the existing common shielded gate trench MOSFET manufacturing method include:

As shown in FIG. 2a, an epitaxial layer 104 is grown on a silicon substrate 102, and a trench 106 is formed in the epitaxial layer 104; a shielding oxide layer 108 is grown on the sidewall of the trench 106, and then a shielding polysilicon 110 is filled;

As shown in FIG. 2b, thinning the surface shielding oxide layer 108 and the shielding polysilicon 110 to a target thickness;

As shown in Figure 2c, a layer of silicon nitride (SIN) 111 is deposited on the surface of the wafer; a window is formed above the shielding polysilicon 110 by photolithography, and then the silicon nitride in the window is dry etched away;

As shown in FIG. 2d, dry etching or wet etching etches back the shielding polysilicon 110 and the shielding oxide layer 108 to a target depth;

As shown in FIG. 2e, a high-density plasma (HDP) oxide layer is deposited to form an isolation oxide layer 112 that isolates the shield polysilicon 110 and the gate polysilicon 116;

As shown in FIG. 2f, the chemical mechanical polishing (CMP) wafer surface isolation oxide layer stops at the silicon nitride layer (SIN) 111;

As shown in FIG. 2g, the surface silicon nitride layer (SIN) 111 is removed, and the isolation oxide layer 112 is etched back to the first target depth;

As shown in FIG. 2h, the gate oxide layer 114 is grown, and the gate polysilicon 116 is deposited and etched back to about 1000 angstroms to 3000 angstroms slightly below the silicon surface; the positive ion is implanted with P-type impurities to form a P-type body region ( P-Body) 118; positive ion implantation of N-type impurities to form source (Source) 120; isolation dielectric layer (ILD) 122 deposition, contact hole (Contact) 124 etching, source metal layer 130 deposition and etching back , passivation layer deposition (not shown), drain metal layer 100 deposition, and the like.

The existing method is to obtain the target depth of the isolation oxide layer, as shown in Figure 2c, it is necessary to deposit a stop-layer (stop-layer) silicon nitride (SIN) 111, and it is necessary to etch a window on this layer, in step 6) In addition, chemical mechanical polishing (CMP) technology needs to be used, and the process is required to stop on the stop-layer (stop-layer) silicon nitride (SIN) 111, and the stop layer needs to be removed later. The process is complex and strict, which leads to manufacturing higher cost.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for manufacturing a shielded gate trench field effect transistor, which is used to solve the problem of high manufacturing cost of the shielded gate trench field effect transistor in the prior art .

To achieve the above object and other related objects, the present invention provides a method for manufacturing a shielded gate trench field effect transistor, comprising the steps of: 1) providing a substrate, forming an epitaxial layer on the upper surface of the substrate, and forming an epitaxial layer on the upper surface of the substrate. A deep trench is formed in the epitaxial layer, a shielding oxide layer is formed on the inner wall of the deep trench and the surface of the epitaxial layer, and shielding polysilicon is filled in the deep trench, and the shielding polysilicon also covers and is located above the epitaxial layer 2) thinning the shielding polysilicon and the shielding oxide layer above the epitaxial layer, and the shielding oxide layer remains above the epitaxial layer; 3) taking the shielding oxide layer as Etching back the shielding polysilicon with a mask to form an etching groove, and the shielding oxide layer in the deep trench is exposed on both sides of the etching groove; 4) wet etching both sides of the etching groove side of the shielding oxide layer, while making the upper portion of the shielding polysilicon protrude from the shielding oxide layer; 5) depositing an isolation oxide layer, the isolation oxide layer includes a filling portion filled in the deep trench and the raised portion covering the epitaxial layer; 6) Wet etch back the isolation oxide layer, etch the filling portion to the target thickness while removing the raised portion and the epitaxial layer. 7) deposit a gate oxide layer on the inner wall of the deep trench and the surface of the isolation oxide layer to form a gate trench, and fill the gate polysilicon in the gate trench and 8) forming a body region in the epitaxial layer on both sides of the deep trench, forming a source in the body region, forming an upper metal structure above the epitaxial layer, and A drain metal layer is formed on the lower surface of the substrate.

Preferably, in step 4) in the wet etching, the shielding oxide layers on both sides of the upper part of the shielding polysilicon are partially removed to form side grooves respectively, and after the wet etching, the A certain thickness of the shielding oxide layer remains on both sides of the etching groove and on the surface of the epitaxial layer.

Further, the side groove includes an arc-shaped bottom.

Further, in step 5), the isolation oxide layer is formed by using a high-density plasma deposition process, and the isolation oxide layer includes the flat filling and the peak-shaped protrusion, so that in step 6) and etching the filling portion to a target thickness while completely removing the raised portion and the shielding oxide layer on the epitaxial layer.

Preferably, in step 1), the thickness of the shielding oxide layer is not less than 1000 angstroms.

Preferably, the bottom of the body region is not lower than the bottom of the gate trench.

Preferably, the substrate, the epitaxial layer, and the source are doped with ions of the first conductivity type, the body region is doped with ions of the second conductivity type, and the first conductivity type and the second conductivity type are The conductivity types are mutually opposite conductivity types.

Further, the substrate includes an N++ type substrate, the epitaxial layer includes an N-type epitaxial layer, the N-type source includes an N+ type source, and the body region includes a P-type body region.

Preferably, step 7) further includes the step of etching back the gate polysilicon, so that the top surface of the gate polysilicon is lower than the top surface of the epitaxial layer.

Preferably, step 8) forming the upper metal structure on the epitaxial layer includes the steps: 8-1) depositing an isolation dielectric layer on the gate polysilicon and the epitaxial layer, etching the isolation dielectric layer to Forming a source contact hole and a gate contact hole, the bottom of the source contact hole exposes the body region, the sidewall exposes the source, and the gate contact hole exposes the gate polysilicon; and 8-2 ) depositing a metal layer on the isolation dielectric layer, the source contact hole and the gate contact hole, so as to realize the electrical extraction of the source and the gate polysilicon.

Further, step 8-2) further includes the step of forming a doped contact region in the body region in the source contact hole before depositing the metal layer.

As mentioned above, the manufacturing method of the shielded gate trench field effect transistor of the present invention has the following beneficial effects:

The present invention cancels the deposition, etching back, removal of the cut-off layer, and the cut-off or leveling of chemical mechanical polishing (CMP) necessary to obtain the depth of the isolation oxide layer in the conventional process, and only increases the isolation oxide layer (high The wet etching step before the deposition of the high-density plasma oxide layer) utilizes the characteristics of the high-density plasma filling process to make the filling of the isolation oxide layer have a unique shape, combined with isotropic wet etching characteristics, in Forming the isolation oxide layer with the target thickness in the deep trench while removing the redundant isolation oxide layer on the surface achieves the same process target effect as the conventional process, greatly reducing the process cost and process time, and has a wide range of applications in the field of semiconductor device design and manufacturing. application prospects.

Description of drawings

FIG. 1 is a schematic structural diagram of a shielded gate trench field effect transistor in the prior art.

2a to 2h are schematic diagrams showing the structure of each step of the manufacturing method of the shielded gate trench field effect transistor in the prior art.

3 to 9 are schematic diagrams showing the structure of each step of the manufacturing method of the shielded gate trench field effect transistor of the present invention.

FIG. 10 is a schematic flow chart showing the steps of the manufacturing method of the shielded gate trench field effect transistor of the present invention.

Component designation description

100 Drain metal layer

102 substrate

104 epitaxial layer

106 deep groove

108 shielding oxide layer

109 etch groove

110 shielded polysilicon

112 isolation oxide layer

113 side groove

114 gate oxide layer

115 curved bottom

116 gate polysilicon

118 body area

120 source

122 isolation dielectric layer

124 Source contact hole

130 metal layers

S11～S18 Step 1)～Step 8)

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 3 to Figure 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in FIGS. 3 to 10 , this embodiment provides a method for manufacturing a shielded gate trench field effect transistor (SGT MOSFET), and the shielded gate trench field effect transistor can be an N-type device or a P-type device. device, this embodiment uses an N-type device as an example for illustration. The manufacturing method comprises the steps of:

As shown in Fig. 3 and Fig. 10, at first carry out step 1) S11, provide a substrate 102, form epitaxial layer 104 on the upper surface of described substrate 102, form deep groove 106 in described epitaxial layer 104, in The inner wall of the deep trench 106 and the surface of the epitaxial layer 104 form a shielding oxide layer 108, and the shielding polysilicon 110 is filled in the deep trench 106, and the shielding polysilicon 110 also covers all the layers above the epitaxial layer 104. The shielding oxide layer 108 is described above.

The substrate 102 can be an N++ type doped silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc. In this embodiment, the substrate 102 is selected as an N++ type doped silicon substrate, so The epitaxial layer 104 is selected as an N-type single crystal silicon epitaxial layer.

A deep trench 106 is formed in the epitaxial layer 104 by a photolithography-etching process, and then a shielding oxide layer 108 is formed on the inner wall of the deep trench 106 and the surface of the epitaxial layer 104 by a thermal oxidation process. The thickness of the oxide layer 108 is not less than 1000 angstroms to achieve a good shielding effect, for example, the thickness of the shielding oxide layer 108 may be between 1000 angstroms-8000 angstroms.

As shown in FIG. 4 and FIG. 10, then step 2) S12 is performed to thin the shielding polysilicon 110 and the shielding oxide layer 108 above the epitaxial layer 104, and the shielding oxide layer 108 remains above the epitaxial layer 104. Layer 108.

For example, the shielding polysilicon 110 and the shielding oxide layer 108 above the epitaxial layer 104 can be thinned using a mechanochemical polishing process, and the shielding oxide layer 108 remains above the epitaxial layer 104 as a subsequent etching. mask.

As shown in Fig. 5 and Fig. 10, proceed to step 3) S13, use the shielding oxide layer 108 as a mask to etch back the shielding polysilicon 110 to form an etching groove 109, and the etching groove 109 has two sides The shield oxide layer 108 within the deep trench 106 is exposed.

As an example, the depth of the etched groove 109 may be between 1/4 and 1/2 of the depth of the deep trench 106, so as to ensure the required retention of the shielding polysilicon 110, and for subsequent The shielding oxide layer 108 and the gate polysilicon 116 provide sufficient manufacturing space.

As shown in Figure 6 and Figure 10, then proceed to step 4) S14, wet etching the shielding oxide layer 108 on both sides of the etching groove 109, while making the upper part of the shielding polysilicon 110 protrude from the The shielding oxide layer 108 is described above.

As an example, in the wet etching, the shielding oxide layer 108 on both sides of the upper part of the shielding polysilicon 110 is partially removed to form side grooves 113 respectively. After the wet etching, the A certain thickness of the shielding oxide layer 108 remains on both sides of the etching groove 109 and on the surface of the epitaxial layer 104 . Further, the side groove 113 includes an arc-shaped bottom 115 .

As shown in FIG. 7 and FIG. 10, step 5) S15 is then performed to deposit an isolation oxide layer 112, the isolation oxide layer 112 includes the filling portion filled in the deep trench 106 and covers the epitaxial layer 104 of the bulge.

As an example, the isolation oxide layer 112 is formed by a high-density plasma deposition process. Due to the structure and morphology formed in step 4) and the characteristics of the high-density plasma deposition process, the isolation oxide layer 112 includes the planar Filling and peaking the raised portion, so that in the subsequent step 6), the filling portion is etched to the target thickness while completely removing the raised portion and the shielding on the epitaxial layer 104 oxide layer 108 .

As shown in FIG. 8 and FIG. 10 , then step 6) S16 is performed to etch back the isolation oxide layer 112 by wet etching, and the filling portion is etched to the target thickness while removing the raised portion and the The shielding oxide layer 108 on the epitaxial layer 104.

Based on the isotropic wet etching back to etch the isolation oxide layer 112, due to the unique shape of the isolation oxide layer 112, the peak-shaped protrusions are easier to be preferentially removed, while the deep trenches 106 The planar filling part in the structure will be partly retained as the isolation oxide layer 112 for finally isolating the shielding polysilicon 110 and the gate polysilicon 116 .

As shown in FIG. 9 and FIG. 10, step 7) S17 and step 8) S18 are then performed to deposit a gate oxide layer 114 on the inner wall of the deep trench 106 and the surface of the isolation oxide layer 112 to form a gate trench. , filling the gate polysilicon 116 in the gate trench to form a gate, performing the step of etching back the gate polysilicon 116, so that the top surface of the gate polysilicon 116 is lower than the epitaxial layer 104 , forming a body region 118 in the epitaxial layer 104 on both sides of the deep trench 106, forming a source electrode 120 in the body region 118, forming an upper metal structure above the epitaxial layer 104, and A drain metal layer 100 is formed on the lower surface of the substrate 102 .

As an example, the substrate 102, the epitaxial layer 104, and the source electrode 120 have ion doping of the first conductivity type, and the body region 118 has ion doping of the second conductivity type, and the first conductivity type and The second conductivity types are opposite to each other. For example, for an N-type device, the substrate 102 includes an N++ type substrate, the epitaxial layer 104 includes an N-type epitaxial layer, the N-type source 120 includes an N+ type source, and the body region 118 includes a P - Body area 118.

As an example, the bottom of the body region 118 is not lower than the bottom of the gate trench, that is, there is a height difference W _overlap between the bottom of the body region 118 and the bottom of the gate trench, so as to further improve the The gate polysilicon 116 can control the channel of the shield gate trench field effect transistor.

Specifically, step 8) forming the upper metal structure above the epitaxial layer 104 includes the steps of:

Step 8-1), depositing an isolation dielectric layer 122 on the gate polysilicon 116 and the epitaxial layer 104, etching the isolation dielectric layer 122 to form a source contact hole 124 and a gate contact hole, the source The bottom of the electrode contact hole 124 exposes the body region 118, the sidewall exposes the source electrode 120, and the gate contact hole exposes the gate polysilicon 116;

Step 8-2), depositing a metal layer 130 on the isolation dielectric layer 122, the source contact hole 124 and the gate contact hole, so as to realize the electrical connection between the source electrode 120 and the gate polysilicon 116 sex elicited.

Preferably, step 8-2) further includes the step of forming a doped contact region in the body region 118 in the source contact hole 124 before depositing the metal layer 130. In this embodiment, the The doped contact region is selected as a P+ type doped contact region to reduce the contact resistance between the metal layer 130 and the body region 118 . Finally, an annealing treatment is performed so that the metal layer 130 forms ohmic contact with the source electrode 120 , the body region 118 and the gate polysilicon 116 , so as to further reduce contact resistance.

As mentioned above, the manufacturing method of the shielded gate trench field effect transistor of the present invention has the following beneficial effects:

The present invention cancels the deposition, etching back, and removal of the cut-off layer that must be carried out in order to obtain the depth of the isolation oxide layer 112 in the conventional process, and the cut-off or leveling of chemical mechanical polishing (CMP), and only increases the isolation oxide layer 112 The wet etching step before the deposition of (high-density plasma oxide layer) utilizes the characteristics of the high-density plasma filling process to make the filling of the isolation oxide layer 112 have a unique morphology, combined with isotropic wet etching characteristics, forming the isolation oxide layer 112 of the target thickness in the deep trench 106 while removing the redundant isolation oxide layer 112 on the surface, achieving basically the same process target effect as the conventional process, greatly reducing the process cost and process time, in semiconductor devices The field of design and manufacture has broad application prospects.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (11)

1. A method for manufacturing a shielded gate trench field effect transistor, characterized in that it comprises the steps: 1) Provide a substrate, form an epitaxial layer on the upper surface of the substrate, form a deep trench in the epitaxial layer, form a shielding oxide layer on the inner wall of the deep trench and the surface of the epitaxial layer, and The deep trench is filled with shielding polysilicon, and the shielding polysilicon also covers the shielding oxide layer above the epitaxial layer; 2) thinning the shielding polysilicon and the shielding oxide layer above the epitaxial layer, and the shielding oxide layer remains above the epitaxial layer; 3) Etching back the shielding polysilicon by using the shielding oxide layer as a mask to form an etching groove, and the shielding oxide layer in the deep trench is exposed on both sides of the etching groove; 4) Wet etching the shielding oxide layer on both sides of the etching groove, while making the upper part of the shielding polysilicon protrude from the shielding oxide layer; 5) depositing an isolation oxide layer, the isolation oxide layer comprising a filling portion filled in the deep trench and a raised portion covering the epitaxial layer; 6) Etching back the isolation oxide layer by wet etching, etching the filling portion to a target thickness while removing the raised portion and the shielding oxide layer on the epitaxial layer; 7) depositing a gate oxide layer on the inner wall of the deep trench and the surface of the isolation oxide layer to form a gate trench, and filling the gate polysilicon in the gate trench to form a gate; and 8) forming a body region in the epitaxial layer on both sides of the deep trench, forming a source in the body region, forming an upper metal structure above the epitaxial layer, and forming a drain on the lower surface of the substrate metal layer. 2. The manufacturing method of a shielded gate trench field effect transistor according to claim 1, characterized in that: in step 4) in the wet etching, the shielding oxide layer on both sides of the upper part of the shielding polysilicon The gaps are partially removed to form side grooves respectively. After the wet etching, a certain thickness of the shielding oxide layer remains on both sides of the etching groove and on the surface of the epitaxial layer. 3 . The method for manufacturing a shielded gate trench field effect transistor according to claim 2 , wherein the side groove comprises an arc-shaped bottom. 4 . 4. The manufacturing method of the shielded gate trench field effect transistor according to claim 2, characterized in that: in step 5), the isolation oxide layer is formed by using a high-density plasma deposition process, and the isolation oxide layer includes a planar shaped filling and peak-shaped raised portion, so that in step 6), the filling portion is etched to the target thickness while completely removing the raised portion and all the parts located on the epitaxial layer The shielding oxide layer. 5 . The method for manufacturing a shielded gate trench field effect transistor according to claim 1 , wherein in step 1), the thickness of the shielded oxide layer is not less than 1000 angstroms. 6 . The method for manufacturing a shielded gate trench field effect transistor according to claim 1 , wherein the bottom of the body region is not lower than the bottom of the gate trench. 7. The manufacturing method of shielded gate trench field effect transistor according to claim 1, characterized in that: the substrate, the epitaxial layer, and the source are doped with first conductivity type ions, and the bulk The region is doped with ions of a second conductivity type, the first conductivity type and the second conductivity type being mutually opposite conductivity types. 8. The manufacturing method of shielded gate trench field effect transistor according to claim 7, characterized in that: the substrate comprises an N++ type substrate, the epitaxial layer comprises an N-type epitaxial layer, and the N-type source The pole includes an N+ type source, and the body region includes a P-type body region. 9. The manufacturing method of shielded gate trench field effect transistor according to claim 1, characterized in that: step 7) further comprises the step of etching back the gate polysilicon, so that the top of the gate polysilicon The surface is lower than the top surface of the epitaxial layer. 10. The manufacturing method of shielded gate trench field effect transistor according to claim 1, characterized in that: step 8) forming the upper metal structure above the epitaxial layer comprises the steps of: 8-1) Depositing an isolation dielectric layer on the gate polysilicon and the epitaxial layer, etching the isolation dielectric layer to form a source contact hole and a gate contact hole, and the bottom of the source contact hole exposes the In the body region, the sidewall exposes the source, and the gate contact hole exposes the gate polysilicon; 8-2) Depositing a metal layer on the isolation dielectric layer, the source contact hole and the gate contact hole, so as to realize the electrical extraction of the source and the gate polysilicon. 11. The manufacturing method of shielded gate trench field effect transistor according to claim 10, characterized in that: before step 8-2) depositing the metal layer, the said source contact hole is further included The step of forming doped contact regions in the body region.