CN116487418B - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure includes the following steps. A substrate is provided, and a trench is formed in the substrate. A protective layer is formed, and the protective layer conformally covers the bottom of the trench. An inhibition layer is formed, and the inhibition layer covers the trench sidewall and is in contact with the protective layer. Remove the protective layer. A thermal oxidation process is used to form a first gate oxide layer at the bottom of the trench, and the thermal oxidation inhibition layer is synchronously formed to form a second gate oxide layer; the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; the first gate oxide layer and The second gate oxide layers together constitute a gate oxide layer. The preparation method of the above-mentioned semiconductor structure increases the thickness of the gate oxide layer at the bottom of the trench, thus improving the problem of insufficient voltage resistance of the gate oxide layer at the bottom of the trench, thereby reducing the gate-drain capacitance at the bottom of the trench and improving the performance of the corresponding semiconductor device high frequency performance.

Description

Semiconductor structure and its preparation method

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a preparation method thereof.

Background technique

In the manufacturing process of trench-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET for short), the gate oxide layer and gate electrode are formed inside the trench to control the on and off of the MOSFET. Therefore, the preparation of gate oxide layer and gate electrode is a very important process.

However, due to stress at the bottom of the trench, the gate oxide layer on the sidewalls of the trench in MOSFET is thicker than the gate oxide layer on the bottom of the trench. As a result, the gate oxide layer at the bottom of the trench has insufficient voltage resistance and is easily broken down. In addition, an excessively thin gate oxide layer at the bottom of the trench can easily lead to excessive gate-to-drain capacitance there, limiting the use of corresponding semiconductor devices in high-frequency applications.

Therefore, how to improve the voltage withstand capability of the gate oxide layer is an urgent problem that needs to be solved.

Contents of the invention

Based on this, embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof to effectively improve the voltage withstand capability of the gate oxide layer.

Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, including the following steps:

Provide a substrate and form a trench in the substrate;

A protective layer is formed, and the protective layer covers the bottom of the trench according to the shape;

An inhibition layer is formed, and the inhibition layer covers the sidewall of the trench and is in contact with the protective layer;

Remove protective layer;

forming a first gate oxide layer at the bottom of the trench;

A second gate oxide layer covering the sidewalls of the trench is formed based on the inhibition layer.

In the embodiment of the present disclosure, a protective layer is first formed to conformally cover the bottom of the trench, and then a suppression layer is formed to cover the side walls of the trench, and the suppression layer is brought into contact with the protective layer. The unexpected effect is that after removing the protective layer, an inhibition layer covering only the sidewalls of the trench can be obtained. In this way, by controlling the formation thickness of the suppression layer, the thickness of the second gate oxide layer subsequently formed based on the suppression layer to cover the trench sidewalls can be controlled. In this way, the thickness difference between the first gate oxide layer at the trench bottom and the second gate oxide layer at the trench sidewall can be simply adjusted. For example, the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewalls of the trench. Based on this, the above-mentioned preparation method of the semiconductor structure can simply increase the thickness of the gate oxide layer at the bottom of the trench, thus improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench, thereby reducing the gate leakage at the bottom of the trench. Capacitors improve the high-frequency performance of corresponding semiconductor devices.

Optionally, the step of forming the protective layer includes:

An initial protective layer is formed, and the initial protective layer follows the shape and covers the inner wall of the trench;

Form a mask layer, and the mask layer fills the bottom of the trench to define the formation area of the protective layer;

Pattern the initial protective layer based on the mask layer to form a protective layer;

Remove the mask layer.

In the embodiment of the present disclosure, the protective layer conformally covers the bottom of the trench and is patterned based on the initial protective layer and mask layer. The formation area of the protective layer can be accurately defined, thereby accurately defining the formation of the inhibition layer on the sidewall of the trench. area. In this way, the formation areas of the second gate oxide layer and the first gate oxide layer can be effectively controlled by controlling the formation area of the inhibition layer, thereby accurately controlling the thickness of the first gate oxide layer at the bottom of the trench and the second gate oxide on the sidewalls of the trench. The thickness of the layer. Moreover, the protective layer is obtained based on patterning of the mask layer, which is also conducive to simplifying its preparation process and improving production efficiency.

Optionally, the material of the mask layer includes photoresist.

Optionally, the second gate oxide layer is formed by an oxidation inhibition layer.

Optionally, the first gate oxide layer is formed using a thermal oxidation process; the second gate oxide layer is formed by simultaneously forming the oxidation inhibition layer while forming the first gate oxide layer.

In the embodiment of the present disclosure, when the thermal oxidation process is used to oxidize the structure after removing the protective layer, since the sidewalls of the trench are covered with the inhibition layer, the thickness of the first gate oxide layer formed at the bottom of the trench is larger than that on the side of the trench. The wall forms the thickness of the second gate oxide layer. In this way, the thickness of the gate oxide layer at the bottom of the trench is increased, further improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

Optionally, the oxidation rate for forming the first gate oxide layer is greater than the oxidation rate for forming the second gate oxide layer. In this way, the same thermal oxidation process can be used to ensure that the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed on the sidewalls of the trench, thereby improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench. question.

Optionally, the value range of the ratio of the oxidation rate for forming the first gate oxide layer to the oxidation rate for forming the second gate oxide layer includes: 19~21. In this way, by reasonably selecting the ratio of the oxidation rates between the first gate oxide layer and the second gate oxide layer, the thickness ratio of the first gate oxide layer at the bottom of the trench and the second gate oxide layer on the sidewalls of the trench can be reasonably controlled to achieve Ensure that the formation thickness of the first gate oxide layer and the second gate oxide layer meets the performance requirements of the semiconductor structure.

Optionally, after forming the second gate oxide layer, the method of preparing the semiconductor structure further includes: using a thermal oxidation process to oxidize the substrate close to the surfaces of the first gate oxide layer and the second gate oxide layer to form a third gate oxide layer . Wherein, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together constitute a gate oxide layer.

In embodiments of the present disclosure, a third gate oxide layer is formed on the surface of the substrate close to the first gate oxide layer and the second gate oxide layer, which can further increase the thickness of the gate oxide layer at the bottom of the trench, thereby further improving the gate thickness at the bottom of the trench. The problem of insufficient pressure resistance of the oxide layer.

Optionally, the material of the substrate includes highly doped silicon; the material of the suppression layer includes silicon carbide or low doped silicon.

In the embodiment of the present disclosure, the material of the substrate is highly doped silicon, and the material of the suppression layer is silicon carbide or low-doping silicon, which can ensure that the oxidation rate of the substrate is higher than the oxidation rate of the suppression layer to ensure that the bottom of the trench is formed The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer formed by the trench sidewalls.

Optionally, the inhibition layer is formed using a selective epitaxial growth process.

Based on the same inventive concept, the present disclosure also provides a semiconductor structure, which is obtained by using the preparation methods in some of the above embodiments. The semiconductor structure includes: a substrate, a first gate oxide layer and a second gate oxide layer. There are trenches in the substrate. The first gate oxide layer fills the bottom of the trench. The second gate oxide layer covers the trench sidewall and is connected to the first gate oxide layer. Wherein, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer. The first gate oxide layer and the second gate oxide layer together form a gate oxide layer.

In the embodiments of the present disclosure, the semiconductor structure adopts the above structure. The technical effects achieved by the semiconductor structure are the same as those achieved by the preparation method of the semiconductor structure in the previous embodiments, and will not be described in detail here.

Optionally, the semiconductor structure further includes: a third gate oxide layer. The third gate oxide layer is located between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer. Wherein, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together constitute a gate oxide layer.

In the embodiment of the present disclosure, the third gate oxide layer located between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer further increases the thickness of the gate oxide layer at the bottom of the trench, thereby further The problem of insufficient voltage resistance of the gate oxide layer at the bottom of the trench is improved.

As mentioned above, the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure first form a protective layer conformally covering the bottom of the trench, and then form a suppression layer covering the sidewalls of the trench and make the suppression layer contact the protective layer. In this way, unexpected effects can be obtained after removing the protective layer and forming the gate oxide layer: simply and effectively increasing the thickness of the gate oxide layer at the bottom of the trench to improve the problem of insufficient voltage resistance of the gate oxide layer at the bottom of the trench. The gate-to-drain capacitance at the bottom of the trench is reduced and the high-frequency performance of the corresponding semiconductor device is improved; in addition, the protective layer is obtained based on patterning of the mask layer, which also helps simplify the preparation process of the semiconductor structure to improve production efficiency.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

Figure 2 is a schematic cross-sectional view of the structure obtained in step S10 of a method for preparing a semiconductor structure according to an embodiment;

Figure 3 is a flow chart of forming a protective layer in a method for preparing a semiconductor structure provided in an embodiment;

Figure 4 is a schematic cross-sectional view of the structure obtained in step S21 of a method for preparing a semiconductor structure according to an embodiment;

Figure 5 is a schematic cross-sectional view of the structure obtained in step S22 of a method for preparing a semiconductor structure according to an embodiment;

Figure 6 is a schematic cross-sectional view of the structure obtained in step S23 of a method for preparing a semiconductor structure according to an embodiment;

Figure 7 is a schematic cross-sectional view of the structure obtained in step S24 of a method for preparing a semiconductor structure according to an embodiment;

Figure 8 is a schematic cross-sectional view of the structure obtained in step S30 of a method for preparing a semiconductor structure according to an embodiment;

Figure 9 is a schematic cross-sectional view of the structure obtained in step S40 of a method for preparing a semiconductor structure according to an embodiment;

FIG. 10 is a schematic cross-sectional view of a structure obtained in step S50 of a method for preparing a semiconductor structure according to an embodiment; and FIG. 10 is also a schematic cross-sectional view of a semiconductor structure according to an embodiment;

FIG. 11 is a schematic cross-sectional view of another structure obtained in step S50 of a method for preparing a semiconductor structure provided by an embodiment; and FIG. 11 is also a schematic cross-sectional view of another semiconductor structure provided by an embodiment.

Explanation of reference symbols:

1-Substrate; 11-Trench;

20-protective layer; 200-initial protective layer;

30-mask layer;

40-inhibitory layer;

50-gate oxide layer; 51-first gate oxide layer; 52-second gate oxide layer; 53-third gate oxide layer;

60-Gate.

Implementation

To facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are illustrated in the accompanying drawings. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure.

It should be understood that spatial relational terms such as "under", "under", "under", "under", "on", "above" Etc. may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "consist" and/or "comprise" are used in this specification, the presence of stated features, integers, steps, operations, elements and/or parts may be identified but not to the exclusion of one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used herein, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown are contemplated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the specific shapes of the regions shown herein but include deviations in shapes due, for example, to manufacturing techniques. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the invention.

In the manufacturing process of trench-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET for short), the gate oxide layer and gate electrode are formed inside the trench to control the on and off of the MOSFET. Therefore, the preparation of gate oxide layer and gate electrode is a very important process.

However, due to stress at the bottom of the trench, the gate oxide layer on the sidewalls of the trench in MOSFET is thicker than the gate oxide layer on the bottom of the trench. As a result, the gate oxide layer at the bottom of the trench has insufficient voltage resistance and is easily broken down. In addition, an excessively thin gate oxide layer at the bottom of the trench can easily lead to excessive gate-to-drain capacitance there, limiting the use of corresponding semiconductor devices in high-frequency applications.

Therefore, how to improve the voltage withstand capability of the gate oxide layer is an urgent problem that needs to be solved.

In view of the deficiencies in the above related technologies, the purpose of the embodiments of the present disclosure is to provide a semiconductor structure and a preparation method thereof to effectively improve the voltage withstand capability of the gate oxide layer.

Referring to FIG. 1 , in some embodiments, some embodiments of the present disclosure provide a method for preparing a semiconductor structure, and the method includes the following steps.

S10: Provide a substrate and form a trench in the substrate.

S20: A protective layer is formed, and the protective layer conforms to the bottom of the trench.

S30: Form an inhibition layer, which covers the trench sidewall and is in contact with the protective layer.

S40: Remove the protective layer.

S50: Form the first gate oxide layer at the bottom of the trench;

S60: Form a second gate oxide layer covering the trench sidewall based on the inhibition layer.

In the embodiment of the present disclosure, a protective layer is first formed to conformally cover the bottom of the trench, and then a suppression layer is formed to cover the side walls of the trench, and the suppression layer is brought into contact with the protective layer. The unexpected effect is that after removing the protective layer, an inhibition layer covering only the sidewalls of the trench can be obtained. In this way, by controlling the formation thickness of the suppression layer, the thickness of the second gate oxide layer subsequently formed based on the suppression layer to cover the trench sidewalls can be controlled. In this way, the thickness difference between the first gate oxide layer at the trench bottom and the second gate oxide layer at the trench sidewall can be simply adjusted. For example, the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the sidewalls of the trench. Based on this, the above-mentioned preparation method of the semiconductor structure can simply increase the thickness of the gate oxide layer at the bottom of the trench, thus improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench, thereby reducing the gate leakage at the bottom of the trench. Capacitors improve the high-frequency performance of corresponding semiconductor devices.

The preparation method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2 to 11 .

In step S10 , please refer to S10 in FIG. 1 and FIG. 2 , a substrate 1 is provided, and a trench 11 is formed in the substrate 1 .

In some examples, substrate 1 may include, but is not limited to, a silicon substrate. Moreover, according to the shape distribution of the trench 11 in the substrate 1, the trench 11 can be divided into the bottom of the trench 11 and the side walls of the trench 11; that is, the distance between the bottom of the trench 11 and the side walls of the trench 11 can be seen. To provide a virtual boundary, respective formation positions of the first gate oxide layer and the second gate oxide layer are defined with corresponding distinctions.

In some examples, the surface of the bottom of trench 11 is curved.

Alternatively, a dry etching process may be used to form the trench 11 in the substrate 1 .

In step S20 , please refer to S20 in FIG. 1 and FIGS. 3 to 6 to form a protective layer 20 , and the protective layer 20 conformally covers the bottom of the trench 11 .

Here, the protective layer 20 follows the shape of the bottom of the trench 11, which means that the protective layer 20 has a thin layer structure, and the surface of the protective layer 20 conforms to the surface of the bottom of the trench 11, so that the surface shape of the protective layer 20 is consistent with the groove. The surface shape of the bottom of the groove 11 is similar.

In some embodiments, referring to FIG. 3 , forming the protective layer 20 includes the following steps.

S21: An initial protective layer is formed, and the initial protective layer conforms to the inner wall of the trench.

S22: Form a mask layer, and the mask layer fills the bottom of the trench to define the formation area of the protective layer.

S23: Pattern the initial protective layer based on the mask layer to form a protective layer.

S24: Remove the mask layer.

In the embodiment of the present disclosure, the protective layer 20 conformally covers the bottom of the trench 11 and is patterned based on the initial protective layer and the mask layer. The formation area of the protective layer 20 can be accurately defined, thereby accurately defining the suppression layer on the trench 11 side. Formation area on the wall. In this way, by controlling the formation area of the inhibition layer, the formation areas of the second gate oxide layer and the first gate oxide layer can be effectively controlled, thereby accurately controlling the thickness of the first gate oxide layer at the bottom of the trench 11 and the second thickness of the sidewall of the trench 11. Gate oxide thickness. Moreover, the protective layer 20 is obtained based on the patterning of the mask layer, which is also conducive to simplifying its preparation process and improving production efficiency.

In step S21 , please refer to FIG. 4 , an initial protective layer 200 is formed, and the initial protective layer 200 conformally covers the inner wall of the trench 11 .

In some embodiments, the initial protective layer 200 also extends to cover the upper surface of the substrate 1 .

Optionally, the thickness of the initial protective layer 200 ranges from 200 angstroms to 1000 angstroms. For example, the thickness of the initial protective layer 200 may be 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms or 1000 angstroms, etc.

Optionally, the material of the initial protective layer 200 may include, but is not limited to, silicon oxide.

Optionally, the initial protective layer 200 is formed using a thermal oxidation process.

In step S22 , please refer to FIG. 5 , a mask layer 30 is formed, and the mask layer 30 fills the bottom of the trench 11 to define a formation area of the protective layer 20 .

In some embodiments, forming the mask layer 30 includes: forming an initial mask layer (not shown in FIG. 5 ), which at least fills the trench 11 ; and removing part of the initial mask layer 300 to form a mask layer. 30.

Optionally, an etch-back process may be used to remove part of the initial mask layer 300 .

Optionally, the material of the mask layer 30 includes but is not limited to photoresist.

In step S23 , referring to FIG. 6 , the initial protective layer 200 is patterned based on the mask layer 30 to form the protective layer 20 .

In some embodiments, based on the mask layer 30 , an etching process may be used to remove the initial protective layer 200 on the sidewalls of the trench 11 and the upper surface of the substrate 1 to form the protective layer 20 .

In step S24, referring to FIG. 7, the mask layer 30 is removed.

Optionally, an etch-back process may be used to remove the mask layer 30 .

In step S30 , please refer to S30 in FIG. 1 and FIG. 8 , an inhibition layer 40 is formed, and the inhibition layer 40 covers the sidewall of the trench 11 and is in contact with the protective layer 20 .

Optionally, the material of the substrate 1 includes highly doped silicon, and the material of the inhibition layer 40 includes silicon carbide or low doped silicon. It should be noted that when the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is low doping silicon, the oxidation rate of the suppression layer 40 is approximately 10% to 20% slower than the oxidation rate of the substrate 1 . When the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is silicon carbide, the oxidation rate of the suppression layer 40 is only 5% to 10% of the oxidation rate of the substrate 1 .

In the embodiment of the present disclosure, the material of the substrate 1 is highly doped silicon, and the material of the suppression layer 40 is silicon carbide or low-doped silicon, which can ensure that the oxidation rate of the substrate 1 is higher than the oxidation rate of the suppression layer 40 to ensure that The thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than the thickness of the second gate oxide layer 52 formed on the sidewalls of the trench 11 .

In some embodiments, the inhibition layer 40 also extends to cover the upper surface of the substrate 1 .

Optionally, the inhibition layer 40 is formed using a selective epitaxial growth process.

In some embodiments, the film thickness of the inhibition layer 40 depends on the height difference ΔH between the bottom of the trench 11 and the sidewalls of the trench 11 . Wherein, ΔH is equal to the difference between the height H1 of the side wall of the trench 11 and the height H2 of the bottom of the trench 11.

For example, the ratio of the oxidation rate of the inhibition layer 40 to the oxidation rate of the substrate 1 at the bottom of the trench 11 is 1:20. Without considering the influence of the thickness of the inhibition layer 40 on the oxidation rate, the thickness of the inhibition layer 40 is about 1/19 of the aforementioned height difference ΔH.

It should be noted that after the subsequent inhibition layer 40 is completely oxidized, the substrate 1 at the sidewalls of the trench 11 and the substrate 1 at the bottom of the trench 11 can continue to be oxidized to form a third gate oxide layer. At this time, since the second gate oxide layer formed based on the inhibition layer 40 at the sidewall of the trench 11 is thin and the first gate oxide layer formed at the bottom of the trench 11 is thicker, when the thermal oxidation process continues to be performed, the trench 11 The oxidation rate of substrate 1 at the sidewalls will be greater than the oxidation rate of substrate 1 at the bottom of trench 11 , so that the thickness difference between the oxide layer at the sidewalls of trench 11 and the oxide layer at the bottom of trench 11 is reduced. Here, the oxide layer at the sidewalls of the trench 11 includes a second gate oxide layer and a third gate oxide layer located at the sidewalls of the trench 11 ; the oxide layer at the bottom of the trench 11 includes a first gate oxide layer located at the bottom of the trench 11 and the third gate oxide layer.

Based on this, in some embodiments, the thickness of the suppression layer 40 can be reasonably increased, for example, making the thickness of the suppression layer 40 greater than 1/19 of the aforementioned height difference ΔH.

In step S40, please refer to S40 in FIG. 1 and FIG. 9, the protective layer 20 is removed.

Optionally, a wet etching process can be used to remove the protective layer 20 .

For example, the wet etching solution may include but is not limited to a buffered oxide etching solution (Buffered Oxide Etch, BOE for short) and a hydrofluoric acid etching solution (the ratio of hydrofluoric acid to water may be, for example, 100:1) .

In step S50 , please refer to S50 in FIG. 1 and FIG. 10 , a first gate oxide layer 51 is formed at the bottom of the trench 11 .

In step S60 , please refer to S60 in FIG. 1 and FIG. 10 , a second gate oxide layer 52 covering the sidewalls of the trench 11 is formed based on the inhibition layer 40 .

In some embodiments, second gate oxide layer 52 is formed by oxidation inhibition layer 40 .

In some embodiments, the first gate oxide layer 51 is formed using a thermal oxidation process; the second gate oxide layer 52 is formed by simultaneously forming the first gate oxide layer 51 and the oxidation inhibition layer 40 simultaneously.

In the embodiment of the present disclosure, when a thermal oxidation process is used to oxidize the structure after removing the protective layer 30 , since the sidewalls of the trench 11 are covered with the inhibition layer 40 , the first gate oxide layer 51 formed at the bottom of the trench 11 is The thickness is greater than the thickness of the second gate oxide layer 52 formed on the sidewall of the trench 11 . In this way, the thickness of the gate oxide layer at the bottom of the trench 11 is increased, further improving the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench.

In some embodiments, the inhibition layer 40 also extends to cover the upper surface of the substrate 1 , and accordingly, the second gate oxide layer 52 formed based on the inhibition layer 40 also extends to cover the upper surface of the substrate 1 .

In some embodiments, the oxidation rate to form the first gate oxide layer 51 is greater than the oxidation rate to form the second gate oxide layer 52 . In this way, the same thermal oxidation process can be used to ensure that the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than the thickness of the second gate oxide layer 52 formed on the side walls of the trench 11 , thereby improving the gate oxidation at the bottom of the trench 11 The problem of insufficient pressure resistance of layer 50.

In some examples, the ratio of the oxidation rate to form the first gate oxide layer 51 to the oxidation rate to form the second gate oxide layer 52 ranges from 19 to 21.

It should be noted that the oxidation rate for forming the first gate oxide layer is the oxidation rate of the substrate 1 at the bottom of the trench 11 , and the oxidation rate for forming the second gate oxide layer is the oxidation rate of the inhibition layer 40 .

In the embodiment of the present disclosure, by reasonably selecting the ratio of the oxidation rates between the first gate oxide layer 51 and the second gate oxide layer 52 , the first gate oxide layer 51 at the bottom of the trench 11 and the second gate oxide layer on the side wall of the trench 11 can be reasonably controlled. The thickness ratio of the gate oxide layer 52 is to ensure that the formation thickness of the first gate oxide layer 51 and the second gate oxide layer 52 meets the performance requirements of the semiconductor structure.

In some embodiments, please refer to FIG. 11 . After forming the second gate oxide layer 52 , the preparation method further includes: using a thermal oxidation process to oxidize the surface of the substrate 10 close to the first gate oxide layer 51 and the second gate oxide layer 52 . , to form the third gate oxide layer 53 . The first gate oxide layer 51 , the second gate oxide layer 52 and the third gate oxide layer 53 together constitute the gate oxide layer 50 .

Here, after the inhibition layer 40 is completely oxidized to form the second gate oxide layer 52 , the substrate 1 at the sidewalls of the trench 11 and the substrate 1 at the bottom of the trench 11 can be further oxidized to form the third gate oxide layer 53 . That is, the aforementioned thermal oxidation process for forming the third gate oxide layer 53 and the thermal oxidation process for forming the second gate oxide layer 52 and the first gate oxide layer 51 may be the same thermal oxidation process.

In the embodiment of the present disclosure, the third gate oxide layer 53 is formed on the surface of the substrate 1 close to the first gate oxide layer 51 and the second gate oxide layer 52, which can further increase the thickness of the gate oxide layer 50 at the bottom of the trench 11, thereby further The problem of insufficient voltage resistance of the gate oxide layer 50 at the bottom of the trench 11 is improved.

Alternatively, the material of the gate oxide layer 50 (including the first gate oxide layer 51 , the second gate oxide layer 52 or the third gate oxide layer 53 ) may include but is not limited to silicon oxide.

In some embodiments, please refer to FIGS. 10 and 11 , after forming the gate oxide layer 50 , the preparation method further includes: forming a gate electrode 60 that at least fills the trench 11 on the surface of the gate oxide layer 50 away from the substrate 10 .

For example, the gate 60 is formed of a conductive material with excellent electrical properties, such as doped polysilicon, metallic copper, or metallic tungsten.

Based on the same inventive concept, please refer to FIG. 10 and FIG. 11 , the present disclosure also provides a semiconductor structure, which is obtained by using the preparation method in some of the above embodiments. The semiconductor structure includes: a substrate 1 , a first gate oxide layer 51 and a second gate oxide layer 52 . The substrate 1 has a trench 11 in it. The first gate oxide layer 51 fills the bottom of the trench 11 . The second gate oxide layer 52 covers the sidewall of the trench 11 and is connected to the first gate oxide layer 51 . The thickness of the first gate oxide layer 51 is greater than the thickness of the second gate oxide layer 52 . The first gate oxide layer 51 and the second gate oxide layer 52 together form the gate oxide layer 50 .

In the embodiments of the present disclosure, the semiconductor structure adopts the above structure. The technical effects achieved by the semiconductor structure are the same as those achieved by the preparation method of the semiconductor structure in the previous embodiments, and will not be described in detail here.

Optionally, the material of substrate 1 includes highly doped silicon. The second gate oxide layer 52 is obtained by oxidation based on the inhibition layer 40 . The material of the suppression layer 40 includes silicon carbide or low-doped silicon. It should be noted that when the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is low doping silicon, the oxidation rate of the suppression layer 40 is approximately 10% to 20% slower than the oxidation rate of the substrate 1 . When the material of the substrate 1 is highly doped silicon and the material of the suppression layer 40 is silicon carbide, the oxidation rate of the suppression layer 40 is only 5% to 10% of the oxidation rate of the substrate 1 .

In some embodiments, the thickness of the second gate oxide layer 52 (that is, the film thickness of the inhibition layer 40 ) depends on the height difference ΔH between the bottom of the trench 11 and the sidewalls of the trench 11 . Wherein, ΔH is equal to the difference between the height H1 of the side wall of the trench 11 and the height H2 of the bottom of the trench 11. For example, if the ratio of the oxidation rate of the inhibition layer 40 to the oxidation rate of the substrate 1 at the bottom of the trench 11 is 1:20, then without considering the influence of the film thickness on the oxidation rate, the thickness of the second gate oxide layer 52 ( That is, the film thickness of the suppression layer 40 may be 1/19 of the aforementioned height difference ΔH.

In some examples, the surface of the bottom of trench 11 is curved.

In some embodiments, please refer to FIG. 11 , the semiconductor structure further includes: a third gate oxide layer 53 . The third gate oxide layer 53 is located between the substrate 1 and the first gate oxide layer 51 , and between the substrate 1 and the second gate oxide layer 52 . Among them, the first gate oxide layer 51, the second gate oxide layer 52 and the third gate oxide layer 53 together constitute a gate oxide layer.

In the embodiment of the present disclosure, the third gate oxide layer 53 located between the substrate 1 and the first gate oxide layer 51 and between the substrate 1 and the second gate oxide layer 52 further increases the gate thickness at the bottom of the trench 11. The thickness of the oxide layer 50 further improves the problem of insufficient voltage resistance of the gate oxide layer 50 at the bottom of the trench 11 .

Alternatively, the material of the gate oxide layer 50 (including the first gate oxide layer 51 , the second gate oxide layer 52 or the third gate oxide layer 53 ) may include but is not limited to silicon oxide.

In some embodiments, please refer to FIGS. 10 and 11 , the semiconductor structure further includes: a gate 60 disposed on the surface of the gate oxide layer 50 facing away from the substrate 10 and at least filling the trench 11 .

For example, the gate 60 is formed of a conductive material with excellent electrical properties, such as doped polysilicon, metallic copper, or metallic tungsten.

In summary, the semiconductor structure and its preparation method provided by the embodiments of the present disclosure first form the protective layer 20 conformally covering the bottom of the trench 11, and then form the inhibition layer 40 covering the sidewalls of the trench 11 and make the inhibition layer 40 and The protective layer 20 is in contact with each other, and an unexpected effect can be obtained after the protective layer 20 is removed and the gate oxide layer 50 is formed: simply and effectively increasing the thickness of the gate oxide layer 50 at the bottom of the trench 11 to improve the thickness of the gate oxide layer 50 at the bottom of the trench 11 The problem of insufficient voltage resistance of the gate oxide layer 50 is reduced, thereby reducing the gate-drain capacitance at the bottom of the trench 11 and improving the high-frequency performance of the corresponding semiconductor device; in addition, the protective layer 20 is obtained based on the patterning of the mask layer 30, which is also conducive to simplifying the semiconductor Structure preparation process to improve production efficiency.

In the description of this specification, the technical features of the above-mentioned embodiments can be combined in any way. To simplify the description, all possible combinations of the technical features of the above-mentioned embodiments are not described. However, as long as these technical features are If there is no contradiction in the combination, it should be considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed should be determined by the appended claims.

Claims (11)

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate, and forming a groove in the substrate;

forming a protective layer which covers the bottom of the groove along with the shape;

forming a suppression layer, wherein the suppression layer covers the side wall of the groove and is in contact with the protection layer;

removing the protective layer;

forming a first gate oxide layer at the bottom of the groove;

forming a second gate oxide layer covering the side wall of the groove based on the inhibition layer; the second gate oxide layer is formed by oxidizing the suppression layer; the thickness of the first gate oxide layer is larger than that of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together form a gate oxide layer.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein the step of forming the protective layer comprises:

forming an initial protection layer, wherein the initial protection layer covers the inner wall of the groove along with the shape;

forming a mask layer, wherein the mask layer fills the bottom of the groove to define a forming area of the protective layer;

patterning the initial protective layer based on the mask layer to form a protective layer;

and removing the mask layer.

3. The method of claim 2, wherein the material of the mask layer comprises a photoresist.

4. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein,

the first gate oxide layer is formed by adopting a thermal oxidation process;

the second gate oxide layer is formed by simultaneously oxidizing the suppression layer while forming the first gate oxide layer.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein an oxidation rate at which the first gate oxide layer is formed is greater than an oxidation rate at which the second gate oxide layer is formed.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein the range of values of the ratio of the oxidation rate at which the first gate oxide layer is formed to the oxidation rate at which the second gate oxide layer is formed includes: 19-21.

7. The method of manufacturing a semiconductor structure according to claim 1, wherein after forming the second gate oxide layer, the method further comprises:

oxidizing the surface of the substrate, which is close to the first gate oxide layer and the second gate oxide layer, by adopting a thermal oxidation process to form a third gate oxide layer;

wherein the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together form a gate oxide layer.

8. The method of fabricating a semiconductor structure of claim 1, wherein the material of the substrate comprises highly doped silicon; the material of the inhibition layer comprises silicon carbide or low-doped silicon.

9. The method of claim 8, wherein the inhibiting layer is formed by a selective epitaxial growth process.

10. A semiconductor structure, characterized in that it is prepared by the preparation method according to any one of claims 1 to 9; the semiconductor structure includes:

a substrate having a trench therein;

the first gate oxide layer is filled at the bottom of the groove;

the second gate oxide layer covers the side wall of the groove and is connected with the first gate oxide layer;

wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together form a gate oxide layer.

11. The semiconductor structure of claim 10, further comprising:

a third gate oxide layer between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer;

wherein the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together form a gate oxide layer.