CN109616409B - A kind of polysilicon deposition method, flash memory and manufacturing method thereof - Google Patents
A kind of polysilicon deposition method, flash memory and manufacturing method thereof Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 154
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 108
- 238000000151 deposition Methods 0.000 title claims abstract description 92
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 230000008021 deposition Effects 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000000137 annealing Methods 0.000 claims description 12
- 230000005641 tunneling Effects 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 12
- 239000011265 semifinished product Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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Abstract
本申请提供一种多晶硅沉积方法、闪存及其制作方法，其中多晶硅沉积方法包括：在具有底部尺寸相对于开口尺寸较大的第一凹槽的衬底上进行多晶硅一次沉积，一次沉积后产生空隙，再进行刻蚀，将空隙位置刻蚀形成开口相对于底部较大的第二凹槽，再次进行沉积，从而填充空隙。本发明实施例中还可以进行多次多晶硅沉积，直到第一凹槽中不存在空隙，也即空隙全部被多晶硅填充，从而提高闪存的电性能和良率。
The present application provides a polysilicon deposition method, a flash memory and a method for manufacturing the same, wherein the polysilicon deposition method includes: performing one-time polysilicon deposition on a substrate having a first groove with a larger bottom size than an opening size, and generating voids after the one-time deposition , and then perform etching to etch the void position to form a second groove with a larger opening relative to the bottom, and perform deposition again to fill the void. In the embodiment of the present invention, multiple times of polysilicon deposition may be performed until there is no void in the first groove, that is, the voids are all filled with polysilicon, thereby improving the electrical performance and yield of the flash memory.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a polycrystalline silicon deposition method, a flash memory and a manufacturing method thereof.
Background
In the flash memory manufacturing process, one of the main choices of the grid is the floating gate; the floating gate is usually made of undoped polysilicon, and a series of processes such as furnace tube deposition, ion implantation, annealing, and CMP (Chemical Mechanical polishing) are performed to obtain the floating gate structure and performance meeting the requirements.
However, after a series of processes such as deposition, ion implantation, annealing, and CMP, voids are generated in the polysilicon, which affects the electrical characteristics and reduces the yield.
Disclosure of Invention
In view of the above, the present invention provides a polysilicon deposition method, a flash memory and a method for manufacturing the same, so as to solve the problems of the prior art that the electrical property of the flash memory is changed and the yield is low due to the generation of voids in polysilicon.
In order to achieve the purpose, the invention provides the following technical scheme:
a polysilicon deposition method comprising:
providing a substrate comprising a first surface formed with first grooves, there being at least one first groove having a cross-sectional area greater than an area of an opening of the first groove on the first surface in a cross-section parallel to the first surface;
performing primary deposition of polycrystalline silicon on the first surface of the substrate to form a polycrystalline silicon layer to be etched;
etching the polysilicon layer to be etched in the first groove to form a second groove, wherein in the section parallel to the first surface, the section area of the second groove is gradually increased or the side wall of the second groove is vertical to the first surface along the direction departing from the substrate;
performing secondary deposition of polycrystalline silicon on the surface of the substrate on which the second groove is formed;
and judging whether a gap exists in the first groove, if so, taking a polycrystalline silicon layer formed by secondary deposition of the polycrystalline silicon as a polycrystalline silicon layer to be etched, returning to the step of etching the polycrystalline silicon layer to be etched in the first groove to form a second groove until the first groove is completely filled.
Preferably, the processes for performing the primary deposition of the polysilicon on the first surface of the substrate and performing the secondary deposition of the polysilicon on the surface of the substrate on which the second groove is formed are the same.
Preferably, the specific process adopted for carrying out the primary deposition of the polycrystalline silicon on the first surface of the substrate is low-pressure chemical vapor deposition.
Preferably, etching the polysilicon layer to be etched in the first groove to form a second groove, specifically comprising:
and introducing etching gas, wherein the etching gas is chlorine, the etching temperature is 200-400 ℃, the gas flow is 1slm-10slm under the pressure of 0-2Torr, and the end point value is included, and etching the polycrystalline silicon layer to be etched in the first groove to form a second groove.
Preferably, the second groove is a V-shaped groove.
Preferably, the second groove is a rectangular groove.
The invention also provides a flash memory manufacturing method, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel region, a first doped region and a second doped region, and the first doped region and the second doped region are positioned on the surface of the semiconductor substrate;
sequentially forming tunneling oxide layers on the surfaces of the channel regions;
depositing and forming a polysilicon floating gate on the tunneling oxide layer;
forming an inter-polycrystalline dielectric layer and a control gate on the surface of the polycrystalline silicon floating gate, which is far away from the semiconductor substrate, in sequence;
and the polysilicon floating gate is formed by adopting any one of the polysilicon deposition methods.
Preferably, after the polysilicon floating gate is deposited and formed, the method further comprises:
and annealing and flattening the polysilicon floating gate.
Preferably, the annealing process adopts a rapid thermal annealing process, and the planarization process adopts a chemical mechanical polishing process.
The invention also correspondingly provides a flash memory, which is manufactured by adopting any one of the above flash memory manufacturing methods; the flash memory includes:
the semiconductor substrate comprises a channel region, a first doping region and a second doping region, wherein the first doping region and the second doping region are positioned on the surface of the semiconductor substrate;
and the tunneling oxide layer, the polysilicon floating gate layer, the inter-polycrystalline dielectric layer and the control gate are sequentially stacked on the channel region.
Preferably, the semiconductor substrate is a P-type substrate.
According to the technical scheme, the polycrystalline silicon deposition method comprises the steps of carrying out primary polycrystalline silicon deposition on a substrate with a first groove with a smaller opening relative to the inside, generating a gap after the primary deposition, etching the gap to form a second groove with the same opening as the bottom or a larger opening relative to the bottom, and carrying out polycrystalline silicon deposition again to fill the gap. In the embodiment of the invention, the polysilicon deposition can be carried out for multiple times until no gap exists in the first groove, namely, the gap is completely filled with the polysilicon, so that the electrical property of the flash memory is improved and the yield of the flash memory is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a substrate structure provided in the prior art;
FIG. 2 is a schematic structural diagram of a flash memory semi-finished product after polysilicon deposition in the prior art;
FIG. 3 is a schematic diagram of a flash memory semi-finished product after annealing in the prior art;
FIG. 4 is a schematic diagram of a flattened flash memory semi-finished product in the prior art;
FIG. 5 is a schematic flow chart of a polysilicon deposition method according to an embodiment of the present invention;
FIGS. 6-12 are process step diagrams of a polysilicon deposition method according to an embodiment of the present invention;
FIG. 13 is a flowchart of a method for manufacturing a flash memory according to an embodiment of the present invention;
fig. 14 is a schematic diagram of a flash memory structure according to an embodiment of the invention.
Detailed Description
As described in the background section, in the prior art, voids are easily formed in the polysilicon during the fabrication process, thereby affecting the electrical performance and yield of the flash memory.
The inventor finds that the above phenomenon occurs because, when a floating gate of a flash memory is formed, a groove on a substrate has a smaller opening and a larger bottom, as shown in fig. 1, fig. 1 is a schematic structural diagram of the substrate, and as the shape of the groove 011 on the substrate 01 is limited, when polysilicon deposition is performed in the groove 011, polysilicon 02 is not completely filled in the groove, and polysilicon on the upper portion of the groove is sealed, so that a gap 012 is formed in the groove 011, see fig. 2, and fig. 2 is a schematic structural diagram of a flash memory semi-finished product after polysilicon deposition is completed; although the voids 012 are partially repaired by the subsequent annealing, the sizes of the voids 012 are reduced, please refer to fig. 3, which is a schematic structural diagram of the annealed flash memory semi-finished product; however, in the subsequent planarization process, CMP is usually used for planarization, and the polishing liquid also etches the voids during the process of etching the poly layer, resulting in enlarged voids 012, as shown in fig. 4, fig. 4 is a schematic structural diagram of the planarized flash memory semi-finished product. After the flash memory is formed subsequently, the existence of the gap affects the electrical property of the flash memory, and the yield of the flash memory is reduced.
The invention provides a polycrystalline silicon deposition method, which comprises the following steps:
providing a substrate comprising a first surface formed with first grooves, there being at least one first groove having a cross-sectional area greater than an area of an opening of the first groove on the first surface in a cross-section parallel to the first surface;
performing primary deposition of polycrystalline silicon on the first surface of the substrate to form a polycrystalline silicon layer to be etched;
etching the polysilicon layer to be etched in the first groove to form a second groove, wherein in the section parallel to the first surface, the section area of the second groove is gradually increased or the side wall of the second groove is vertical to the first surface along the direction departing from the substrate;
performing secondary deposition of polycrystalline silicon on the surface of the substrate on which the second groove is formed;
and judging whether a gap exists in the first groove, if so, taking a polycrystalline silicon layer formed by secondary deposition of the polycrystalline silicon as a polycrystalline silicon layer to be etched, returning to the step of etching the polycrystalline silicon layer to be etched in the first groove to form a second groove until the first groove is completely filled.
The polycrystalline silicon deposition method provided by the invention comprises the steps of carrying out primary deposition on polycrystalline silicon on a substrate with a first groove with the bottom size larger than the opening size, generating a gap after the primary deposition, etching again, etching the gap position to form a second groove with the opening larger than the bottom, and carrying out deposition again to fill the gap. In the embodiment of the invention, the polysilicon deposition can be carried out for multiple times until no gap exists in the first groove, namely, the gap is completely filled with the polysilicon, so that the electrical property of the flash memory is improved and the yield of the flash memory is improved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for depositing polysilicon, please refer to fig. 5, where fig. 5 is a schematic flow chart of the method for depositing polysilicon according to the embodiment of the present invention; the polysilicon deposition method provided in the present embodiment will be described in detail with reference to the process step diagrams of the polysilicon deposition method shown in fig. 6 to 12.
The polycrystalline silicon deposition method provided by the embodiment of the invention comprises the following steps:
s101: providing a substrate comprising a first surface formed with first grooves, there being at least one first groove having a cross-sectional area greater than an area of an opening of the first groove on the first surface in a cross-section parallel to the first surface;
referring to fig. 6, the substrate 1 includes a first surface, i.e., the upper surface in fig. 6, and the first surface is formed with a first groove 11, it should be noted that the main reason for generating the void in the polysilicon deposition method provided in this embodiment is caused by the shape of the first groove. Specifically, the shape of the first grooves 11 is a structure in which the bottom size is larger and the opening size on the first surface is smaller, as shown in fig. 6, that is, in the direction Y away from the substrate, in a cross section along a direction parallel to the first surface, there is a case where the cross-sectional area of at least one first groove is larger than the opening area, that is, the first groove 11 having a smaller opening relative to the inside is formed, that is, as shown in fig. 6, the opening area S2 is smaller than the bottom area S1.
It should be noted that, in this embodiment, a specific shape of the first groove is not limited, and may be a regular shape or an irregular shape, which is not limited in this embodiment, where the regular shape may be a trapezoid in a cross section perpendicular to the first surface, that is, the structure shown in fig. 6, or the first groove is in a circular truncated cone shape. For convenience of description, in the embodiment, the cross-sectional area of the first groove in the direction away from the substrate is gradually decreased, that is, the cross-section of the first groove perpendicular to the first surface is a trapezoid. The irregular-shaped groove may also be a groove with an uneven sidewall, which is not limited in this embodiment. As long as the opening of the first recess 11 is small relative to the inner space of the first recess 11, there is a risk of voids occurring during the deposition of polysilicon.
In other embodiments, the shape of the groove is not along the direction away from the substrate, and in the manufacturing process of the semiconductor device, the cross-sectional area is gradually decreased, if necessary, the polysilicon deposition method provided by the present invention may also be adopted, and the embodiment is not particularly limited.
S102: performing primary deposition of polycrystalline silicon on the first surface of the substrate to form a polycrystalline silicon layer to be etched;
the specific process method of the polysilicon one-time deposition is not limited in the embodiment of the invention, and in one embodiment of the invention, low pressure chemical vapor deposition (LP _ CVD) may be used.
Referring to fig. 7, a polysilicon layer 21 to be etched is formed over the entire first surface of the substrate, and at this time, a void 121 is formed in the first groove due to the definition of the profile of the first groove. In the embodiment of the invention, the thickness of the polysilicon layer to be etched is not limited, the inclined angles of the side wall of the first groove relative to the first surface are different, and the condition of forming the gap is different, for example, the included angle between the side wall of the first groove and the bottom surface of the first groove is smaller, the inclined angle of the side wall of the first groove is larger, the gap is easier to form after the bottom surface is deposited and filled with the polysilicon, and when the included angle between the side wall of the first groove and the bottom surface of the first groove is larger, the inclined angle of the side wall is smaller, the polysilicon on the bottom surface is easier to deposit and fill, the formed gap is smaller and is closer to the upper.
Therefore, the thickness of the polysilicon layer to be etched in this embodiment may be different according to the different shapes of the first groove, and the thickness of the polysilicon layer to be etched may be the thickness of the gap opening just sealed or may be smaller than the thickness of the gap opening just sealed. Or may be slightly larger than the thickness of the opening of the gap just before the sealing, which is not limited in this embodiment.
When the thickness of the polysilicon layer to be etched is thicker, as shown in fig. 7, the gap opening is sealed; as shown in fig. 8, when the polysilicon layer 21 to be etched is thinner, the gap opening is not sealed, and an open structure 121' is formed. In any structure, the gap can be completely filled in the following steps in the present embodiment.
S103: etching the polysilicon layer to be etched in the first groove to form a second groove, wherein in the section parallel to the first surface, the section area of the second groove is gradually increased or the side wall of the second groove is vertical to the first surface along the direction departing from the substrate;
etching the polysilicon layer to be etched in the first groove to form a second groove, and specifically comprises the following steps:
and introducing etching gas, wherein the etching gas is chlorine, the etching temperature is 200-400 ℃, the gas flow is 1slm-10slm under the pressure of 0-2Torr, and the end point value is included, and etching the polycrystalline silicon layer to be etched in the first groove to form a second groove. Wherein slm is the unit of gas flow: standard liters per minute.
The second groove formed by etching comprises the gap, namely, the gap position is expanded into the second groove by forming the second groove, and then the second groove is filled, so that the gap is removed.
It should be noted that, in this embodiment, the specific shape of the second groove is not limited, as long as the condition that the area of the cross section of the second groove gradually increases along the direction away from the substrate in the cross section parallel to the first surface is satisfied, that is, in the present invention, the second groove with a larger opening relative to the bottom surface is etched, and then polysilicon deposition is performed, so that the first groove is gradually and fully filled with polysilicon, and a gap is avoided.
In addition, in other embodiments of the present invention, the shape and area of the opening and the inner space of the second groove are the same, that is, the sidewall of the second groove is perpendicular to the first surface, which can also effectively improve the deposition of the polysilicon and reduce the formation of the void.
The shape of the second groove is not limited in this embodiment, and the cross section of the second groove 122 may be a V-shape, as shown in fig. 9, that is, the second groove is a V-shape groove. The opening area S3 is larger than the area of each cross section located below the opening, and the area of the bottom surface of the V-shaped second groove is 0. The second recess 122 shown in fig. 9 may be adapted to the void shown in fig. 7.
The second groove may also be as shown in fig. 10, with the second groove 122' having an opening with an area S5 and a bottom surface with an area S4. Wherein S4 is less than S5. In addition, the second groove may be a rectangular groove, i.e., S4 is equal to S5, as long as the opening is larger than or equal to the second groove of the bottom surface, so that the polysilicon can be deposited again to fully fill the inside of the second groove without forming a void.
S104: performing secondary deposition of polycrystalline silicon on the surface of the substrate on which the second groove is formed;
similarly, in this embodiment, the specific process of the secondary deposition of polysilicon is not limited, and the same process as the sequential deposition of polysilicon may be adopted, or different deposition processes may be adopted. Optionally, in this embodiment, the processes used for the first deposition of polysilicon and the second deposition of polysilicon are the same.
It should be noted that multiple depositions of polysilicon are preferably performed In the same process, and thus may be formed using an In-situ DEP process, which means that In-situ DEP is performed directly In a single station or chamber In one go, rather than In multiple steps performed on multiple different stations.
In this embodiment, the thickness of the polysilicon layer during the second deposition is not limited, and the second groove may be completely filled, as shown in fig. 11, to form a thicker polysilicon layer, so that the inside of the second groove is completely filled. And a thinner polysilicon deposition layer can be formed, and then the subsequent process is carried out.
The fact that the inside of the second groove is completely filled in this embodiment means that the inside of the second groove is completely filled with polysilicon, and no void is generated. It should be noted that, in the actual production process, due to the limitation of the manufacturing process, the polysilicon inside the second groove does not theoretically have any gap at all, but if the size of the gap is small, the gap does not affect the performance of the device, and the performance requirement of the device is met, the gap also falls within the protection range of the second groove being completely filled.
S105: and judging whether a gap exists in the first groove, if so, taking a polycrystalline silicon layer formed by secondary deposition of the polycrystalline silicon as a polycrystalline silicon layer to be etched, returning to the step of etching the polycrystalline silicon layer to be etched in the first groove to form a second groove until the first groove is completely filled.
It should be noted that, in the above steps, if the thickness of the polysilicon layer to be etched generated by the first deposition and the thickness of the polysilicon layer to be etched by the second deposition are both thin, the first deposition may be performed: the process of primary deposition of polysilicon, etching to form a second groove and secondary deposition of polysilicon cannot complete the complete filling of the first groove and may form a gap, so in this embodiment, after the above steps are performed once, a determination step may be performed to determine whether the first groove is completely filled, and if the first groove is completely filled, the subsequent annealing and planarization processes and the performance of the formed flash memory are not affected, and therefore, the polysilicon deposition step may be ended. If there is still a void in the first groove, this is repeated one or more times again: and etching to form a second groove, namely a process of secondary deposition of polysilicon, until the first groove is completely filled with the polysilicon, so that the performance and yield of the formed flash memory are ensured. In other embodiments of the present invention, if the thickness of the polysilicon secondary deposition is also thinner, the polysilicon deposition may be added once again before the etching is performed again.
Similarly, the fact that the inside of the first groove is completely filled with polysilicon in this embodiment means that no void is generated inside the first groove. It should be noted that, in the actual production process, due to the limitation of the manufacturing process, the polysilicon inside the first groove does not theoretically have any gap at all, but if the size of the gap is small, the gap does not affect the performance of the device, and the performance requirement of the device is met, the gap also falls within the protection range of the first groove being completely filled.
In the embodiment of the present invention, a specific process for determining whether a gap exists in the first groove is not limited, and optionally, the process includes:
after the polysilicon CMP, an optical defect scanning machine is used for scanning the wafer to judge whether a gap exists in the first groove.
After the polysilicon deposition, a TEM (Transmission Electron Microscope) stage is used to slice and determine whether there is a void in the first trench.
The polycrystalline silicon deposition method provided by the invention comprises the steps of carrying out primary deposition on polycrystalline silicon on a substrate with a first groove with the bottom size larger than the opening size, generating a gap after the primary deposition, etching again, etching the gap position to form a second groove with the opening larger than the bottom, and carrying out deposition again to fill the gap. In the embodiment of the invention, the polysilicon deposition can be carried out for multiple times until no gap exists in the first groove, namely, the gap is completely filled with the polysilicon, so that the electrical property of the flash memory is improved and the yield of the flash memory is improved.
An embodiment of the present invention further provides a flash memory manufacturing method, please refer to fig. 13, where fig. 13 is a flowchart of the flash memory manufacturing method provided in the embodiment of the present invention, and the flash memory manufacturing method specifically includes:
s201: providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel region, a first doped region and a second doped region, and the first doped region and the second doped region are positioned on the surface of the semiconductor substrate;
in one embodiment of the present invention, the semiconductor substrate is a silicon substrate and is a P-type silicon substrate doped with impurities. The first doping area and the second doping area are both n + areas with larger doping concentration, and a source area and a drain area are formed in the subsequent process.
S202: sequentially forming tunneling oxide layers on the surfaces of the channel regions;
s203: depositing and forming a polysilicon floating gate on the tunneling oxide layer;
it should be noted that the polysilicon floating gate in the embodiment of the present invention is formed by the polysilicon deposition method described in the above embodiment. Therefore, the problems of electric property change and yield reduction of the flash memory caused by the generation of gaps in the floating gate structure are avoided.
S204: forming an inter-polycrystalline dielectric layer and a control gate on the surface of the polycrystalline silicon floating gate, which is far away from the semiconductor substrate, in sequence;
in this embodiment, after the polysilicon floating gate is deposited and formed, Annealing and planarization processes are further performed on the polysilicon floating gate, but the specific processes of Annealing and planarization are not limited in this embodiment, and optionally, an RTA (Rapid Thermal Annealing) process is used for the Annealing. And the planarization adopts a CMP process.
According to the flash memory manufacturing method provided by the embodiment of the invention, in the process of forming the polysilicon floating gate, the polysilicon deposition method is adopted to form the polysilicon floating gate, so that a gap in the polysilicon floating gate is avoided, and therefore, the electrical property of the flash memory can be improved and the yield of the flash memory can be improved.
The embodiment of the invention also provides a flash memory which is manufactured and formed by adopting the flash memory manufacturing method in the embodiment. Referring to fig. 14, fig. 14 is a schematic diagram of a flash memory structure according to an embodiment of the present invention; the flash memory includes:
a semiconductor substrate 140 including a channel region 141, a first doped region 142 and a second doped region 143 on a surface of the semiconductor substrate 140;
and the tunneling oxide layer 15, the polysilicon floating gate layer 16, the interpoly dielectric layer 17 and the control gate 18 are sequentially stacked on the channel region 141.
In one embodiment of the present invention, the semiconductor substrate is a silicon substrate and is a P-type silicon substrate doped with impurities. The first doping area and the second doping area are both n + areas with larger doping concentration, and a source area and a drain area are formed in the subsequent process.
The flash memory structure provided by the embodiment is formed by adopting the polysilicon deposition method in the embodiment in the process of manufacturing the polysilicon floating gate, so that the phenomenon that gaps occur in the process of forming the polysilicon floating gate, the electrical property of the flash memory is influenced, and the yield of the flash memory is reduced can be avoided.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A polysilicon deposition method, characterized in that polysilicon is deposited multiple times by an in-situ deposition process, the polysilicon deposition method comprising:
providing a substrate comprising a first surface formed with first grooves, there being at least one first groove having a cross-sectional area greater than an area of an opening of the first groove on the first surface in a cross-section parallel to the first surface;
performing primary deposition of polycrystalline silicon on the first surface of the substrate to form a polycrystalline silicon layer to be etched;
etching the polysilicon layer to be etched in the first groove to form a second groove, wherein the area of the cross section of the second groove is gradually increased along the direction departing from the substrate in the cross section parallel to the first surface;
performing secondary deposition of polycrystalline silicon on the surface of the substrate on which the second groove is formed;
and judging whether a gap exists in the first groove, if so, taking a polycrystalline silicon layer formed by secondary deposition of the polycrystalline silicon as a polycrystalline silicon layer to be etched, returning to the step of etching the polycrystalline silicon layer to be etched in the first groove to form a second groove until the first groove is completely filled.
2. The method according to claim 1, wherein the primary deposition of polysilicon on the first surface of the substrate and the secondary deposition of polysilicon on the surface of the substrate on which the second grooves are formed are performed by the same process.
3. The method of claim 2, wherein the first deposition of polysilicon on the first surface of the substrate is performed by a low pressure chemical vapor deposition.
4. The method according to claim 1, wherein etching the polysilicon layer to be etched in the first groove to form a second groove comprises:
and introducing etching gas, wherein the etching gas is chlorine, the etching temperature is 200-400 ℃, the pressure is 0-2Torr, the gas flow is 1-10 slm, and the end point value is included, and etching the polycrystalline silicon layer to be etched in the first groove to form a second groove.
5. The method of claim 1, wherein the second groove is a V-shaped groove.
6. The method of claim 1, wherein the second recess is a rectangular recess.
7. A method for manufacturing a flash memory, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel region, a first doped region and a second doped region, and the first doped region and the second doped region are positioned on the surface of the semiconductor substrate;
sequentially forming tunneling oxide layers on the surfaces of the channel regions;
depositing and forming a polysilicon floating gate on the tunneling oxide layer;
forming an inter-polycrystalline dielectric layer and a control gate on the surface of the polycrystalline silicon floating gate, which is far away from the semiconductor substrate, in sequence;
wherein, the deposition for forming the polysilicon floating gate is formed by the polysilicon deposition method of any one of claims 1 to 6.
8. The method of claim 7, further comprising, after depositing and forming the polysilicon floating gate:
and annealing and flattening the polysilicon floating gate.
9. The method of claim 8, wherein the annealing is performed by a rapid thermal annealing process and the planarization is performed by a chemical mechanical polishing process.
10. A flash memory, characterized by being manufactured by the method for manufacturing a flash memory according to any one of claims 7 to 9; the flash memory includes:
the semiconductor substrate comprises a channel region, a first doping region and a second doping region, wherein the first doping region and the second doping region are positioned on the surface of the semiconductor substrate;
and the tunneling oxide layer, the polysilicon floating gate layer, the inter-polycrystalline dielectric layer and the control gate are sequentially stacked on the channel region.
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