CN104733395A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN104733395A CN104733395A CN201310705256.8A CN201310705256A CN104733395A CN 104733395 A CN104733395 A CN 104733395A CN 201310705256 A CN201310705256 A CN 201310705256A CN 104733395 A CN104733395 A CN 104733395A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 139
- 239000000758 substrate Substances 0.000 claims description 53
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- 239000011248 coating agent Substances 0.000 claims description 24
- 238000000576 coating method Methods 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
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- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 10
- 239000000428 dust Substances 0.000 claims description 10
- 238000004151 rapid thermal annealing Methods 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 230000015654 memory Effects 0.000 abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
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- 238000002955 isolation Methods 0.000 description 20
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- 238000000151 deposition Methods 0.000 description 9
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a method for manufacturing a semiconductor device. According to the method, two layers of silicon thin films different in hardness are used for replacing a layer of polycrystalline silicon thin film, so that the problem that after a floating gate polycrystalline silicon layer is subjected to CMP, a concave part is formed in the floating gate polycrystalline silicon layer in a large-area active zone is solved, a loose window is provided for a following technology, and accordingly the whole performance of an embedded type flash memory and the yield of the embedded type flash memory are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of embedded flash memory floating boom.
Background technology
Memory is for storing a large amount of digital information, show according to investigations recently, worldwide, memory chip approximately account for 30% of semiconductor transaction, for many years, the progress of technology and the market demand expedite the emergence of more and more highdensity all kinds memory, as RAM (random asccess memory), SRAM(static random access memory), DRAM (dynamic random access memory) and FRAM (ferroelectric memory) etc.
Random asccess memory, such as DRAM and SRAM in use deposits the problem storing loss of data after a power failure.In order to overcome this problem, people have designed and have developed multiple nonvolatile memory.Recently, based on the flash memory of floating grid concept, due to it, there is little cell size and good service behaviour becomes the most general nonvolatile memory.
Flash memory is the mainstream technology of nowadays nonvolatile memory, and it still can keep data under having powering-off state, and CMOS technology compatibility is good, and can the repeatedly advantage such as erasable data, is widely used in various product.Such as mobile phone, notebook, the storage such as palmtop PC and solid state hard disc and communication apparatus.Flash memory comprises floating grid and control gate, and flash memory adopts multi-crystal silicon floating bar to store data (electric charge) usually, and the voltage on control gate controls the raceway groove of flash cell with certain coupling coefficient by floating boom.
Along with characteristic size is advanced into nanoscale, improve while reducing memory cell, improving storage density and store reading and writing data, erasing and retention, become the key issue that the development of current floating gate memory cell faces.This just requires to be improved conventional floating gate memory cell from materials and structures.
Along with the reduction of device size, the preparation of a lot of companies floating boom adopts the method for floating boom cmp (FG-CMP, Floating Gate CMP).Floating boom CMP is one of critical process making embedded flash memory simultaneously.After CMP process, obtain the uniform floating boom of thickness can leave window for subsequent technique processing procedure, but, different from active area dimensions regular in flash array region, in flush memory device, in logical device region, active area dimensions excursion is large, CMP processing procedure easily forms depression in large-sized active area, and follow-up etching easily forms the destruction to active area.
Therefore, need a kind of new method, to avoid the problem forming depression in the floating gate polysilicon layer in the Large area active district in logic region, to improve the change through the floating boom thickness after CMP in Large area active district, improve the performance of the entirety of embedded flash memory and the yields of embedded flash memory simultaneously.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprising: Semiconductor substrate is provided; Be formed with hard mask layer on the semiconductor substrate, described hard mask layer comprises the oxide skin(coating) and nitride layer that stack gradually; Etch described hard mask layer and described Semiconductor substrate, to form shallow trench; In described shallow trench, fill spacer material layer, the surface of described spacer material layer is concordant with the surface of described hard mask; Remove described nitride layer; Form the first floating gate material layer on the semiconductor substrate; Described first floating gate material layer forms the second floating gate material layer; Perform flatening process, remove all described second floating gate material layer and the described first floating gate material layer of part, till the top of exposing described spacer material layer, form floating gate structure; Wherein, the material hardness of described second floating gate material layer is greater than the material hardness of described first floating gate material layer.
Preferably, the thickness range of described first floating gate material layer is 500 dust to 1000 dusts, and the material of described second floating gate material layer is thickness range is 500 dust to 1000 dusts.
Preferably, the material of described first floating gate material layer is amorphous silicon, and the material of described second floating gate material layer is polysilicon.
Preferably, the step forming described first floating gate material layer comprises first deposition and forms polysilicon, then implements pre-amorphous injection to described polysilicon.
Preferably, the implant angle of described pre-amorphous injection technology is 0 ° to 45 °.
Preferably, the injection ion of pre-amorphous injection technology be the ion of High atomic mass, the ion of described High atomic mass comprises germanium, arsenic or antimony.
Preferably, also comprise rapid thermal annealing is carried out described amorphous silicon to be converted into the step of polysilicon to described floating gate structure.
Preferably, the temperature of described rapid thermal anneal process step is 800 DEG C to 1200 DEG C.
Preferably, adopt cmp to perform described planarisation step, the grinding rate of the first floating gate material layer described in cmp is very fast, and described in cmp, the grinding rate of the second floating gate material layer is slower.
In sum, method of the present invention adopts the different silicon thin film of two-layer hardness to replace one deck polysilicon membrane, to solve the problem forming depression at floating gate polysilicon layer after CMP at the floating gate polysilicon layer being arranged in Large area active district, for subsequent technique provides loose window, with the yields of the performance and embedded flash memory that improve the entirety of embedded flash memory.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
The cross-sectional view of the device that Figure 1A-1D obtains for the correlation step making embedded flash memory floating boom according to one embodiment of the present invention;
Fig. 2 is the process chart making embedded flash memory floating boom according to one embodiment of the present invention;
The cross-sectional view of the device that Fig. 3 A-3C obtains for the correlation step making embedded flash memory floating boom according to another execution mode of the present invention;
Fig. 4 is the process chart making embedded flash memory floating boom according to another execution mode of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention solves the problems of the prior art.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Be described in detail the manufacture method of embedded flash memory floating boom of the present invention below in conjunction with Figure 1A-1D, Figure 1A-1D is the profile making semiconductor device structure in the process of embedded flash memory floating boom according to the present embodiment.
As shown in Figure 1A, provide Semiconductor substrate 100, in the substrate 100 of described semiconductor, be formed with trap.
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Semiconductor substrate 100 is had two regions, be respectively: for the formation of the first area of logical device, logic region; For the formation of the second area of flash memories, memory cell region.It should be noted that, logic region is all be positioned at peripheral circuit region in true layout.Semiconductor substrate 100 has active area.
Form hard mask layer on a semiconductor substrate 100, described hard mask layer comprises the oxide skin(coating) 101 and nitride layer that stack gradually, concrete, and oxide skin(coating) 101 forms nitride layer.Shallow trench and active area is defined on a semiconductor substrate 100 by STI photoetching process.Oxide skin(coating) 101 can pass through thermal oxidation, chemical vapor deposition (CVD) or oxynitridation process and be formed.Oxide skin(coating) can comprise following any conventional dielectric: SiO
2, SiON, SiON
2, and comprise other similar oxide of perofskite type oxide.Wherein, the material of oxide skin(coating) preferably uses silica, and generation type adopts thermal oxidation method.
In a specific embodiment of the present invention, the method for definition shallow trench is: at semiconductor substrate surface coating photoresist, expose and develop, by predefined graph transfer printing on photoresist to photoresist.Then with remaining photoresist for mask etches, Semiconductor substrate part not covered by photoresist is etched successively, etching hard mask layer (nitride layer and oxide skin(coating) 101) and Semiconductor substrate, form shallow trench, the bottom of this shallow trench is arranged in Semiconductor substrate.
Then, the filling of shallow trench is carried out, depositing isolation material layer in described shallow trench and on silicon nitride layer, spacer material layer preferential oxidation nitride layer.In an embodiment of the present invention, adopting HDP(high-density plasma) depositing operation forms oxide skin(coating) in described shallow trench and on nitride layer, the material of oxide skin(coating) is preferably silicon dioxide, adopt HDP-CVD(high density plasma chemical vapor deposition) form oxide skin(coating), HDP-CVD technique synchronously carries out depositing in same reaction chamber and sputter reacting, and the reacting gas that HDP-CVD technique adopts comprises SiH
4and O
2, and sputtering gas hydrogen and helium.Because deposition and sputtering technology are carried out simultaneously, by adjustment SiH
4and O
2and the content of hydrogen and helium is to make sputtering sedimentation ratio for 1:1.
Planarization is carried out to the spacer material layer of Semiconductor substrate, the surface of described spacer material layer is concordant with the surface of described hard mask, concrete, remove the spacer material layer be positioned on nitride layer, then remove nitride layer, define room in the position at original nitride layer place, make the surface of the spacer material layer of filling shallow trench far away higher than other positions, after removal nitride layer, expose oxide skin(coating) 101 simultaneously, form fleet plough groove isolation structure 102.
Exemplarily.In Semiconductor substrate 100, form fleet plough groove isolation structure (STI), the degree of depth of fleet plough groove isolation structure is 2500 to 4000 dusts, and the height of fleet plough groove isolation structure is 1500 dust to 3000 dusts.
After forming fleet plough groove isolation structure 102, described Semiconductor substrate 100 comprises small size active area and Large area active district, is isolated between described Large area active district and described small size active area by fleet plough groove isolation structure 102.
Then, form the preferred polysilicon of material of the first floating gate material layer 103, first floating gate material layer 103 on a semiconductor substrate 100, described first floating gate material layer 103 covers isolation structure 102 and grid oxic horizon 102 completely.Preferably, described first floating gate material layer 103 is unadulterated polysilicon layer, and the thickness range of described polysilicon layer is 500 dust to 1000 dusts.Limiting examples comprises process for chemical vapor deposition of materials with via and physical vapor deposition methods.
The formation method forming the first floating gate material layer in embodiments of the present invention can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
It should be noted that, the method for above-mentioned formation first floating gate material layer is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here.
While the described first floating gate material layer 103 of formation, pre-amorphous injection (PAI) is implemented to described first floating gate material layer 103, the injection ion of pre-amorphous injection is the ion of High atomic mass (high atomicmass), in embodiments of the present invention, the ion of described High atomic mass comprises germanium, arsenic or antimony.In an embodiment of the present invention, the material of described first floating gate material layer 103 is unadulterated polysilicon, and after pre-amorphous injection, unadulterated polysilicon becomes amorphous silicon.
When performing pre-amorphous injection, the energy range of ion implantation is 3-20keV, and the dosage of ion implantation is 1.0 × e
13-9.0 × e
13cm
-2, the incident direction of ion implantation offsets certain angle relative to the direction perpendicular with Semiconductor substrate 100, and the scope of described angle is 0-45 degree.
As shown in Figure 1B, described first floating gate material layer 103 forms the second floating gate material layer 104, preferably, described second floating gate material layer 104 is unadulterated polysilicon layer, and the thickness range of described polysilicon layer is 500 dust to 1000 dusts.Limiting examples comprises process for chemical vapor deposition of materials with via and physical vapor deposition methods.
The formation method forming the second floating gate material layer in embodiments of the present invention can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
It should be noted that, the method for above-mentioned formation second floating gate material layer is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here.
As shown in Figure 1 C, adopt flatening process process first floating gate material layer 103 and the second floating gate material layer 104 until expose fleet plough groove isolation structure 102, to form floating gate structure 105, concrete, perform flatening process, remove all described second floating gate material layer 104 and the described first floating gate material layer 103 of part, till the top of exposing described spacer material layer, form floating gate structure 105, as shown in figure ip, preferably, cmp is adopted to perform described flatening process.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and cmp flattening method.Cmp flattening method is more conventional.
Exemplarily, adopt in the process of cmp first floating gate material layer 103 and the second floating gate material layer 104, described in cmp process during the first floating gate material layer 103 grinding rate very fast, described in cmp process during the second floating gate material layer 104 grinding rate slower, be equivalent to, described in cmp process during unadulterated polysilicon grinding rate comparatively slow, when implementing the polysilicon of pre-amorphous injection described in cmp process, grinding rate is very fast.
Exemplarily, the first floating gate material layer and the second floating gate material layer are after flatening process process, and the first unnecessary floating gate material layer and the second floating gate material layer are removed.
Exemplarily, described second floating gate material layer 104 gets rid of described second floating gate material layer completely after cmp, and described first floating gate material layer 103 gets rid of the first floating gate material layer of part after cmp.
After execution flatening process, rapid thermal annealing process is performed to described floating gate structure 105.When the temperature of described rapid thermal annealing process step is 1000 DEG C, amorphous silicon becomes polysilicon after described RTA process.
Described annealing steps is generally under described substrate is placed in the protection of high vacuum or high-purity gas; be heated to certain temperature and carry out RTA (RTA) technique; nitrogen or inert gas is preferably at high-purity gas of the present invention; the temperature of described rapid thermal annealing process step is 800-1200 DEG C; be preferably 1000 DEG C, the described thermal anneal step time is 1-300s.As further preferred, the rapid thermal annealing selected in the present invention, the one in following several mode can be selected: pulse laser short annealing, the short annealing of the Pulse Electric philosophical works, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc., but be not limited to examples cited.
With reference to Fig. 2, illustrated therein is the process chart into making embedded flash memory floating boom according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide Semiconductor substrate, Semiconductor substrate is had memory cell region and logic region, be arranged in the fleet plough groove isolation structure of Semiconductor substrate, be formed with grid oxic horizon on a semiconductor substrate;
In step 202., form the first floating gate material layer on the semiconductor substrate and pre-amorphous injection is implemented to described first floating gate material layer simultaneously;
In step 203, described first floating gate material layer forms the second floating gate material layer;
In step 204, chemical mechanical milling tech planarization first floating gate material layer and the second floating gate material layer is adopted.
Be described in detail the manufacture method of embedded flash memory floating boom of the present invention below in conjunction with Fig. 3 A-3C, Fig. 3 A-3C is the profile making semiconductor device structure in the process of embedded flash memory floating boom according to the present embodiment.
As shown in Figure 3A, provide Semiconductor substrate 300, in the substrate 300 of described semiconductor, be formed with trap.
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Semiconductor substrate 300 is had two regions, be respectively: for the formation of the first area of logical device, logic region; For the formation of the second area of flash memories, memory cell region.It should be noted that, logic region is all be positioned at peripheral circuit region in true layout.Semiconductor substrate 300 has active area.
Semiconductor substrate 300 forms hard mask layer, and described hard mask layer comprises the oxide skin(coating) 301 and nitride layer that stack gradually, concrete, and oxide skin(coating) 301 forms nitride layer.In Semiconductor substrate 300, shallow trench and active area is defined by STI photoetching process.Oxide skin(coating) 301 can pass through thermal oxidation, chemical vapor deposition (CVD) or oxynitridation process and be formed.Oxide skin(coating) can comprise following any conventional dielectric: SiO
2, SiON, SiON
2, and comprise other similar oxide of perofskite type oxide.Wherein, the material of oxide skin(coating) preferably uses silica, and generation type adopts thermal oxidation method.
In a specific embodiment of the present invention, the method for definition shallow trench is: at semiconductor substrate surface coating photoresist, expose and develop, by predefined graph transfer printing on photoresist to photoresist.Then with remaining photoresist for mask etches, Semiconductor substrate part not covered by photoresist is etched successively, etching hard mask layer (nitride layer and oxide skin(coating) 301) and Semiconductor substrate, form shallow trench, the bottom of this shallow trench is arranged in Semiconductor substrate.
Then, the filling of shallow trench is carried out, depositing isolation material layer in described shallow trench and on silicon nitride layer, spacer material layer preferential oxidation nitride layer.In an embodiment of the present invention, adopting HDP(high-density plasma) depositing operation forms oxide skin(coating) in described shallow trench and on nitride layer, the material of oxide skin(coating) is preferably silicon dioxide, adopt HDP-CVD(high density plasma chemical vapor deposition) form oxide skin(coating), HDP-CVD technique synchronously carries out depositing in same reaction chamber and sputter reacting, and the reacting gas that HDP-CVD technique adopts comprises SiH
4and O
2, and sputtering gas hydrogen and helium.Because deposition and sputtering technology are carried out simultaneously, by adjustment SiH
4and O
2and the content of hydrogen and helium is to make sputtering sedimentation ratio for 1:1.
Planarization is carried out to the spacer material layer of Semiconductor substrate, the surface of described spacer material layer is concordant with the surface of described hard mask, concrete, remove the spacer material layer be positioned on nitride layer, then remove nitride layer, define room in the position at original nitride layer place, make the surface of the spacer material layer of filling shallow trench far away higher than other positions, after removal nitride layer, expose oxide skin(coating) 301 simultaneously, form fleet plough groove isolation structure 302.
Exemplarily.In Semiconductor substrate 300, form fleet plough groove isolation structure (STI), the degree of depth of fleet plough groove isolation structure is 2500 to 4000 dusts, and the height of fleet plough groove isolation structure is 1500 dust to 3000 dusts.
After forming fleet plough groove isolation structure 302, described Semiconductor substrate 100 comprises small size active area and Large area active district, is isolated between described Large area active district and described small size active area by fleet plough groove isolation structure 302.
Then, form the preferred amorphous silicon of material of the first floating gate material layer 303, first floating gate material layer 103 on semiconductor substrate 200, described first floating gate material layer 303 covers isolation structure and grid oxic horizon 302 completely.Preferably, the thickness range of described amorphous silicon is 500 dust to 1000 dusts.Limiting examples comprises process for chemical vapor deposition of materials with via and physical vapor deposition methods.
Then, described first floating gate material layer 303 forms the second floating gate material layer 304, preferably, described second floating gate material layer 304 is polysilicon layer, and the thickness range of described polysilicon layer is 500 dust to 1000 dusts.Limiting examples comprises process for chemical vapor deposition of materials with via and physical vapor deposition methods.
The formation method forming the second floating gate material layer in embodiments of the present invention can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
It should be noted that, the method for above-mentioned formation second floating gate material layer is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here.
As shown in Figure 3 B, adopt flatening process process first floating gate material layer 303 and the second floating gate material layer 304 until expose fleet plough groove isolation structure 302, to form floating gate structure 305, particularly, perform flatening process, remove all described second floating gate material layer 304 and the described first floating gate material layer 303 of part, till the top of exposing described spacer material layer, form floating gate structure 305, as shown in Figure 3 C, preferably, cmp is adopted to perform described flatening process.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and cmp flattening method.Cmp flattening method is more conventional.
Exemplarily, adopt in the process of cmp first floating gate material layer 303 and the second floating gate material layer 304, described in cmp process during the first floating gate material layer 303 grinding rate very fast, described in cmp process during the second floating gate material layer 304 grinding rate slower, be equivalent to, described in cmp process during polysilicon grinding rate comparatively slow, when cmp process amorphous silicon, grinding rate is very fast.
Exemplarily, the first floating gate material layer and the second floating gate material layer are after flatening process process, and the first unnecessary floating gate material layer and the second floating gate material layer are removed.
Exemplarily, described second floating gate material layer gets rid of described second floating gate material layer completely after cmp, and described first floating gate material layer gets rid of the first floating gate material layer of part after cmp.
After execution flatening process, rapid thermal annealing process is performed to described floating gate structure 305.When the temperature of described rapid thermal annealing process step is 1000 DEG C, amorphous silicon becomes polysilicon after described RTA process.
Described annealing steps is generally under described substrate is placed in the protection of high vacuum or high-purity gas; be heated to certain temperature and carry out RTA (RTA) technique; nitrogen or inert gas is preferably at high-purity gas of the present invention; the temperature of described rapid thermal annealing process step is 800-1200 DEG C; be preferably 1000 DEG C, the described thermal anneal step time is 1-300s.As further preferred, the rapid thermal annealing selected in the present invention, the one in following several mode can be selected: pulse laser short annealing, the short annealing of the Pulse Electric philosophical works, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc., but be not limited to examples cited.
With reference to Fig. 4, illustrated therein is the process chart into making embedded flash memory floating boom according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 401, provide Semiconductor substrate, Semiconductor substrate is had memory cell region and logic region, be arranged in the fleet plough groove isolation structure of Semiconductor substrate, be formed with grid oxic horizon on a semiconductor substrate;
In step 402, the first floating gate material layer is formed on the semiconductor substrate;
In step 403, described first floating gate material layer forms the second floating gate material layer;
In step 404, chemical mechanical milling tech planarization first floating gate material layer and the second floating gate material layer is adopted.
In sum, method according to the present invention adopts the different silicon thin film of two-layer hardness to replace one deck polysilicon membrane, to solve the problem forming depression at floating gate polysilicon layer after CMP at the floating gate polysilicon layer being arranged in Large area active district, for subsequent technique provides loose window, with the yields of the performance and embedded flash memory that improve the entirety of embedded flash memory.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (9)
1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided;
Be formed with hard mask layer on the semiconductor substrate, described hard mask layer comprises the oxide skin(coating) and nitride layer that stack gradually;
Etch described hard mask layer and described Semiconductor substrate, to form shallow trench;
In described shallow trench, fill spacer material layer, the surface of described spacer material layer is concordant with the surface of described hard mask;
Remove described nitride layer;
Form the first floating gate material layer on the semiconductor substrate;
Described first floating gate material layer forms the second floating gate material layer;
Perform flatening process, remove all described second floating gate material layer and the described first floating gate material layer of part, till the top of exposing described spacer material layer, form floating gate structure;
Wherein, the material hardness of described second floating gate material layer is greater than the material hardness of described first floating gate material layer.
2. the method for claim 1, is characterized in that, the thickness range of described first floating gate material layer is 500 dust to 1000 dusts, and the material of described second floating gate material layer is thickness range is 500 dust to 1000 dusts.
3. the method for claim 1, is characterized in that, the material of described first floating gate material layer is amorphous silicon, and the material of described second floating gate material layer is polysilicon.
4. the method for claim 1, is characterized in that, the step forming described first floating gate material layer comprises first deposition and forms polysilicon, then implements pre-amorphous injection to described polysilicon.
5. method as claimed in claim 4, it is characterized in that, the implant angle of described pre-amorphous injection technology is 0 ° to 45 °.
6. method as claimed in claim 4, is characterized in that, the injection ion of pre-amorphous injection technology be the ion of High atomic mass, the ion of described High atomic mass comprises germanium, arsenic or antimony.
7. method as claimed in claim 3, is characterized in that, also comprise and carry out rapid thermal annealing described amorphous silicon to be converted into the step of polysilicon to described floating gate structure.
8. method as claimed in claim 7, it is characterized in that, the temperature of described rapid thermal anneal process step is 800 DEG C to 1200 DEG C.
9. the method for claim 1, it is characterized in that, adopt cmp to perform described planarisation step, the grinding rate of the first floating gate material layer described in cmp is very fast, and described in cmp, the grinding rate of the second floating gate material layer is slower.
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| CN114784009A (en) * | 2022-06-20 | 2022-07-22 | 广州粤芯半导体技术有限公司 | Preparation method of embedded flash memory |
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