CN104733395B - A method of making semiconductor devices - Google Patents
A method of making semiconductor devices Download PDFInfo
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- CN104733395B CN104733395B CN201310705256.8A CN201310705256A CN104733395B CN 104733395 B CN104733395 B CN 104733395B CN 201310705256 A CN201310705256 A CN 201310705256A CN 104733395 B CN104733395 B CN 104733395B
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Abstract
The present invention proposes a kind of method making semiconductor devices, the silicon thin film for using two layers of hardness different according to the method for the present invention replaces one layer of polysilicon membrane, to solve the problems, such as to form recess in the floating gate polysilicon layer positioned at Large area active area after CMP in floating gate polysilicon layer, loose window is provided for subsequent technique, to improve the yields of the whole performance and embedded flash memory of embedded flash memory.
Description
Technical field
The present invention relates to semiconductor fabrication process more particularly to a kind of production methods of embedded flash memory floating boom.
Background technology
Memory is shown, worldwide, memory chip is about according to investigations recently for storing a large amount of digital informations
The 30% of semiconductor transaction is accounted for, for many years, the progress of technology and the market demand expedite the emergence of more and more highdensity various
Type memory, such as RAM (random access memory), SRAM（Static RAM）, DRAM (dynamic RAM) and FRAM
(ferroelectric memory) etc..
Random access memory, such as DRAM and SRAM deposit the problem of storing loss of data after a power failure in use.For
Overcome the problems, such as this, people have designed and developed a variety of nonvolatile memories.Recently, based on floating grid concept
Flash memory, since it has become most general nonvolatile memory with small unit size and good working performance.
Flash memory is the mainstream technology of nowadays nonvolatile memory, it has is maintained to data under power blackout situation,
With CMOS technology good compatibility, and can repeatedly erasable data the advantages that, be widely used in various products.Such as mobile phone,
The storages such as notebook, palm PC and solid state disk and communication apparatus.Flash memory includes that floating grid and control grid, flash memory are logical
Frequently with multi-crystal silicon floating bar data (charge) are stored, the voltage on control gate is controlled by floating boom with certain coefficient of coup
The raceway groove of flash cell.
As characteristic size is advanced into nanoscale, storage number is improved while reducing storage unit, improving storage density
According to read-write, erasing and retention property, has become current floating gate memory cell and develop the critical issue faced.This requires from material
Conventional floating gate storage unit is improved in material and structure.
With the reduction of device size, the preparations of many company's floating booms using floating boom chemical mechanical grinding (FG-CMP,
Floating Gate CMP）Method.Floating boom CMP is one of the critical process for making embedded flash memory simultaneously.Through CMP processing
It can be that subsequent technique processing procedure leaves window to obtain floating boom in homogeneous thickness later, however, having with rule in flash array region
Source region size is different, and active area dimensions variation range is big in logical device region in flush memory device, and CMP processing procedures are easy in large scale
Active area form recess, subsequent etching is easy to form destruction to active area.
Therefore, it is necessary to a kind of new methods, more to avoid the floating boom in the Large area active area in logic region
The problem of recess is formed in crystal silicon layer, to improve the variation through the floating boom thickness after CMP process in Large area active area, together
The yields of the whole performance and embedded flash memory of Shi Tigao embedded flash memorys.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, the present invention proposes a kind of method making semiconductor devices, packet
It includes：Semiconductor substrate is provided；It is formed with hard mask layer on the semiconductor substrate, the hard mask layer includes stacking gradually
Oxide skin(coating) and nitride layer；The hard mask layer and the semiconductor substrate are etched, to form shallow trench；In the shallow trench
Middle filling spacer material layer, the flush on the surface of the spacer material layer and the hard mask；Remove the nitride layer；
The first floating gate material layer is formed on the semiconductor substrate；The second floating gate material is formed on the first floating gate material layer
Layer；Flatening process, the whole second floating gate material layers of removal and part the first floating gate material layer are executed, until exposing
Until the top of the spacer material layer, FGS floating gate structure is formed；Wherein, the material hardness of the second floating gate material layer is more than institute
State the material hardness of the first floating gate material layer.
Preferably, the thickness range of the first floating gate material layer is 500 angstroms to 1000 angstroms, the second floating gate material layer
Material be thickness range be 500 angstroms to 1000 angstroms.
Preferably, the material of the first floating gate material layer is non-crystalline silicon, and the material of the second floating gate material layer is more
Crystal silicon.
Preferably, the step of forming the first floating gate material layer includes first depositing to form polysilicon, then to described more
Crystal silicon implements pre-amorphous injection.
Preferably, the implant angle of the pre-amorphous injection technology is 0 ° to 45 °.
Preferably, pre-amorphous injection technology injection ion be High atomic mass ion, the High atomic mass
Ion include germanium, arsenic or antimony.
Preferably, further include that rapid thermal annealing is carried out to convert the non-crystalline silicon to polysilicon to the FGS floating gate structure
Step.
Preferably, the temperature of the rapid thermal anneal process step is 800 DEG C to 1200 DEG C.
Preferably, the planarisation step is executed using chemical mechanical grinding, the first floating boom material described in chemical mechanical grinding
The grinding rate of the bed of material is very fast, and the grinding rate of the second floating gate material layer described in chemical mechanical grinding is slower.
In conclusion the method for the present invention replaces one layer of polysilicon membrane using the different silicon thin film of two layers of hardness, with solution
It forms the problem of being recessed in the floating gate polysilicon layer positioned at Large area active area after CMP certainly in floating gate polysilicon layer, is
Subsequent technique provides loose window, to improve the yields of the whole performance and embedded flash memory of embedded flash memory.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.In the accompanying drawings,
Figure 1A -1D is make the device that is obtained of correlation step of embedded flash memory floating boom according to one embodiment of the present invention
The cross-sectional view of part；
Fig. 2 is the process flow chart that embedded flash memory floating boom is made according to one embodiment of the present invention；
What Fig. 3 A-3C were obtained to make the correlation step of embedded flash memory floating boom according to another embodiment of the present invention
The cross-sectional view of device；
Fig. 4 is the process flow chart that embedded flash memory floating boom is made according to another embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it will be apparent to one skilled in the art that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to illustrate the present invention be as
What solves the problems of the prior art.Obviously presently preferred embodiments of the present invention is detailed is described as follows, however removes these in detail
Description is outer, and the present invention can also have other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or combination thereof.
Now, exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
The production method of embedded flash memory floating boom of the present invention is described in detail below in conjunction with Figure 1A -1D, is schemed
1A-1D be according to the present embodiment make embedded flash memory floating boom during semiconductor device structure sectional view.
As shown in Figure 1A, semiconductor substrate 100 is provided, trap is formed in the substrate 100 of the semiconductor.
The semiconductor substrate can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator（SOI）、
Silicon is laminated on insulator（SSOI）, SiGe is laminated on insulator（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And
Germanium on insulator（GeOI）Deng.As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
By the tool of semiconductor substrate 100, there are two regions, respectively：It is used to form the first area of logical device, logic area
Domain；It is used to form the second area of flash memories, memory cell region.It should be noted that logic region is really being laid out
In all be located at peripheral circuit region.Semiconductor substrate 100 has active area.
Hard mask layer is formed on a semiconductor substrate 100, and the hard mask layer includes 101 He of oxide skin(coating) stacked gradually
Nitride layer, specifically, forming nitride layer on oxide skin(coating) 101.On a semiconductor substrate 100 by STI photoetching processes
Define shallow trench and active area.Oxide skin(coating) 101 can pass through thermal oxide, chemical vapor deposition（CVD）Or oxynitridation process
It is formed.Oxide skin(coating) may include following any conventional dielectric：SiO2、SiON、SiON2And it is aoxidized including Ca-Ti ore type
Other similar oxides of object.Wherein, the material of oxide skin(coating) preferably uses silica, generation type to use thermal oxidation method.
In the specific embodiment of the present invention, the method for defining shallow trench is：It is coated with photoetching in semiconductor substrate surface
Glue is exposed photoresist and develops, and predefined figure is transferred on photoresist.Then it is to cover with remaining photoresist
Film is etched, and the part that semiconductor substrate is not covered by photoresist is sequentially etched, and etches hard mask layer（Nitride layer and oxygen
Compound layer 101）And semiconductor substrate, shallow trench is formed, the bottom of the shallow trench is located in semiconductor substrate.
Then, the filling for carrying out shallow trench, depositing isolation material layer in the shallow trench and on silicon nitride layer, isolation
Material layer preferred oxides layer.In an embodiment of the present invention, using HDP（High-density plasma）Depositing operation is in the shallow ridges
Oxide skin(coating) is formed in slot and on nitride layer, the material of oxide skin(coating) is preferably silica, using HDP-CVD（It is highly dense
Spend plasma chemical vapor deposition）Formed oxide skin(coating), HDP-CVD techniques be synchronously carried out in the same reaction chamber it is heavy
Product is reacted with sputtering, and the reaction gas that HDP-CVD techniques use includes SiH4And O2And the gas hydrogen and helium of sputtering.
Since deposition and sputtering technology are carried out at the same time, by adjusting SiH4And O2And the content of hydrogen and helium is so that sputtering is heavy
Product is than being 1:1.
Planarization process is carried out to the spacer material layer of semiconductor substrate, the surface of the spacer material layer is covered firmly with described
The flush of film then removes nitride layer, in original nitrogen specifically, removal is located at the spacer material layer on nitride layer
Position where compound layer forms vacancy, so that the surface of the spacer material layer of filling shallow trench is significantly larger than other positions, together
When after removing nitride layer expose oxide skin(coating) 101, formed fleet plough groove isolation structure 102.
Illustratively.Fleet plough groove isolation structure is formed in semiconductor substrate 100（STI）, the depth of fleet plough groove isolation structure
Degree is 2500 to 4000 angstroms, and the height of fleet plough groove isolation structure is 1500 angstroms to 3000 angstroms.
It is formed after fleet plough groove isolation structure 102, the semiconductor substrate 100, which includes small area active area and large area, to be had
Source region is isolated between the Large area active area and the small area active area by fleet plough groove isolation structure 102.
Then, the first floating gate material layer 103 is formed on a semiconductor substrate 100, and the material of the first floating gate material layer 103 is excellent
Select polysilicon, the first floating gate material layer 103 that isolation structure 102 and grid oxic horizon 102 is completely covered.Preferably, described
First floating gate material layer 103 is undoped polysilicon layer, and the thickness range of the polysilicon layer is 500 angstroms to 1000 angstroms.It is non-
Limitative examples include process for chemical vapor deposition of materials and physical vapor deposition methods.
Low-pressure chemical vapor phase deposition can be selected in the forming method for forming the first floating gate material layer in embodiments of the present invention
(LPCVD) technique.The process conditions for forming the polysilicon layer include：Reaction gas is silane (SiH4), the stream of the silane
It can be 100~200 cc/mins (sccm) to measure range, such as 150sccm；Temperature range can be 700~750 in reaction chamber
Degree Celsius；It can be 250~350 milli millimetress of mercury (mTorr) to react cavity pressure, such as 300mTorr；In the reaction gas also
May include buffer gas, the buffer gas can be helium (He) or nitrogen, the range of flow of the helium and nitrogen can be 5~
20 liters/min (slm), such as 8slm, 10slm or 15slm.
It should be noted that the method for above-mentioned formation the first floating gate material layer is illustrative, it is not limited to described
Method can be applied to the present invention as long as this field other methods can realize the purpose, and details are not described herein.
The first floating gate material layer 103 is implemented while forming the first floating gate material layer 103 pre-amorphous
Injection（PAI）, the injection ion of pre-amorphous injection is High atomic mass（high atomic mass）Ion, in the present invention
In embodiment, the ion of the High atomic mass includes germanium, arsenic or antimony.In an embodiment of the present invention, first floating boom
The material of material layer 103 is undoped polysilicon, and undoped polysilicon becomes non-crystalline silicon after pre-amorphous injection.
When executing pre-amorphous injection, the energy range of ion implanting is 3-20keV, and the dosage of ion implanting is 1.0
×e13-9.0×e13cm-2, the incident direction of ion implanting is certain relative to the direction offset perpendicular with semiconductor substrate 100
Angle, the ranging from 0-45 degree of the angle.
As shown in Figure 1B, the second floating gate material layer 104 is formed on the first floating gate material layer 103, it is preferable that described
Second floating gate material layer 104 is undoped polysilicon layer, and the thickness range of the polysilicon layer is 500 angstroms to 1000 angstroms.It is non-
Limitative examples include process for chemical vapor deposition of materials and physical vapor deposition methods.
Low-pressure chemical vapor phase deposition can be selected in the forming method for forming the second floating gate material layer in embodiments of the present invention
(LPCVD) technique.The process conditions for forming the polysilicon layer include：Reaction gas is silane (SiH4), the stream of the silane
It can be 100~200 cc/mins (sccm) to measure range, such as 150sccm；Temperature range can be 700~750 in reaction chamber
Degree Celsius；It can be 250~350 milli millimetress of mercury (mTorr) to react cavity pressure, such as 300mTorr；In the reaction gas also
May include buffer gas, the buffer gas can be helium (He) or nitrogen, the range of flow of the helium and nitrogen can be 5~
20 liters/min (slm), such as 8slm, 10slm or 15slm.
It should be noted that the method for above-mentioned formation the second floating gate material layer is illustrative, it is not limited to described
Method can be applied to the present invention as long as this field other methods can realize the purpose, and details are not described herein.
As shown in Figure 1 C, the first floating gate material layer 103 and the second floating gate material layer 104 are handled using flatening process until
Expose fleet plough groove isolation structure 102, to form FGS floating gate structure 105, specifically, execute flatening process, removal all described the
Two floating gate material layers 104 and part the first floating gate material layer 103, until the top for exposing the spacer material layer,
FGS floating gate structure 105 is formed, as shown in figure iD, it is preferable that execute the flatening process using using chemical mechanical grinding.
The planarization on surface can be realized using flattening method conventional in field of semiconductor manufacture.The planarization side
The non-limiting examples of method include mechanical planarization method and chemical mechanical grinding flattening method.Chemical mechanical grinding planarizes
Method is more often used.
Illustratively, using the process of the first floating gate material of chemical mechanical grinding layer 103 and the second floating gate material layer 104
In, when chemical mechanical grinding handles the first floating gate material layer 103, grinding rate is very fast, and institute is handled in chemical mechanical grinding
Grinding rate is slower when stating the second floating gate material layer 104, is equivalent to, in the chemical mechanical grinding processing undoped polysilicon
When grinding rate it is slower, when chemical mechanical grinding handles the polysilicon for implementing pre-amorphous injection, grinding rate is very fast.
Illustratively, the first floating gate material layer and the second floating gate material layer are extra after planarized process
First floating gate material layer and the second floating gate material layer are removed.
Illustratively, the second floating gate material layer 104 is floating through completely removing described second after chemical mechanical grinding
Gate material layer, the first floating gate material layer 103 get rid of the first floating gate material layer of part through chemical mechanical grinding later.
After executing flatening process, rapid thermal annealing process is executed to the FGS floating gate structure 105.Described quick
When the temperature of thermal annealing process step is 1000 DEG C, non-crystalline silicon becomes polysilicon after being handled through the rapid temperature annealing.
The annealing steps are usually to be placed in the substrate under the protection of high vacuum or high-purity gas, are heated to certain
Temperature carries out rapid temperature annealing (RTA) technique, is preferably nitrogen or inert gas in high-purity gas of the present invention, described fast
The temperature of fast thermal annealing process step is 800-1200 DEG C, and preferably 1000 DEG C, the thermal anneal step time is 1-300s.
As a further preference, the rapid thermal annealing selected in the present invention can select one kind in following methods：Pulse
Laser short annealing, the short annealing of pulsed electron book, ion beam short annealing, continuous wave laser short annealing and incoherent width
Band light source（Such as halogen lamp, arc lamp, graphite heating）Short annealing etc., but it is not limited to examples cited.
With reference to Fig. 2, it is shown to make the technique stream of embedded flash memory floating boom according to one embodiment of the present invention
Cheng Tu, the flow for schematically illustrating entire manufacturing process.
In step 201, semiconductor substrate is provided, semiconductor substrate is had into memory cell region and logic region, position
Fleet plough groove isolation structure in semiconductor substrate, is formed with grid oxic horizon on a semiconductor substrate；
In step 202, the first floating gate material layer is formed on the semiconductor substrate simultaneously to the first floating boom material
The bed of material implements pre-amorphous injection；
In step 203, the second floating gate material layer is formed on the first floating gate material layer；
In step 204, the first floating gate material layer and the second floating gate material layer are planarized using chemical mechanical milling tech.
The production method of embedded flash memory floating boom of the present invention is described in detail below in conjunction with Fig. 3 A-3C, is schemed
3A-3C be according to the present embodiment make embedded flash memory floating boom during semiconductor device structure sectional view.
As shown in Figure 3A, semiconductor substrate 300 is provided, trap is formed in the substrate 300 of the semiconductor.
The semiconductor substrate can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator（SOI）、
Silicon is laminated on insulator（SSOI）, SiGe is laminated on insulator（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And
Germanium on insulator（GeOI）Deng.As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
By the tool of semiconductor substrate 300, there are two regions, respectively：It is used to form the first area of logical device, logic area
Domain；It is used to form the second area of flash memories, memory cell region.It should be noted that logic region is really being laid out
In all be located at peripheral circuit region.Semiconductor substrate 300 has active area.
Hard mask layer is formed in semiconductor substrate 300, the hard mask layer includes 301 He of oxide skin(coating) stacked gradually
Nitride layer, specifically, forming nitride layer on oxide skin(coating) 301.By STI photoetching processes in semiconductor substrate 300
Define shallow trench and active area.Oxide skin(coating) 301 can pass through thermal oxide, chemical vapor deposition（CVD）Or oxynitridation process
It is formed.Oxide skin(coating) may include following any conventional dielectric：SiO2、SiON、SiON2And it is aoxidized including Ca-Ti ore type
Other similar oxides of object.Wherein, the material of oxide skin(coating) preferably uses silica, generation type to use thermal oxidation method.
In the specific embodiment of the present invention, the method for defining shallow trench is：It is coated with photoetching in semiconductor substrate surface
Glue is exposed photoresist and develops, and predefined figure is transferred on photoresist.Then it is to cover with remaining photoresist
Film is etched, and the part that semiconductor substrate is not covered by photoresist is sequentially etched, and etches hard mask layer（Nitride layer and oxygen
Compound layer 301）And semiconductor substrate, shallow trench is formed, the bottom of the shallow trench is located in semiconductor substrate.
Then, the filling for carrying out shallow trench, depositing isolation material layer in the shallow trench and on silicon nitride layer, isolation
Material layer preferred oxides layer.In an embodiment of the present invention, using HDP（High-density plasma）Depositing operation is in the shallow ridges
Oxide skin(coating) is formed in slot and on nitride layer, the material of oxide skin(coating) is preferably silica, using HDP-CVD（It is highly dense
Spend plasma chemical vapor deposition）Formed oxide skin(coating), HDP-CVD techniques be synchronously carried out in the same reaction chamber it is heavy
Product is reacted with sputtering, and the reaction gas that HDP-CVD techniques use includes SiH4And O2And the gas hydrogen and helium of sputtering.
Since deposition and sputtering technology are carried out at the same time, by adjusting SiH4And O2And the content of hydrogen and helium is so that sputtering is heavy
Product is than being 1:1.
Planarization process is carried out to the spacer material layer of semiconductor substrate, the surface of the spacer material layer is covered firmly with described
The flush of film then removes nitride layer, in original nitrogen specifically, removal is located at the spacer material layer on nitride layer
Position where compound layer forms vacancy, so that the surface of the spacer material layer of filling shallow trench is significantly larger than other positions, together
When after removing nitride layer expose oxide skin(coating) 301, formed fleet plough groove isolation structure 302.
Illustratively.Fleet plough groove isolation structure is formed in semiconductor substrate 300（STI）, the depth of fleet plough groove isolation structure
Degree is 2500 to 4000 angstroms, and the height of fleet plough groove isolation structure is 1500 angstroms to 3000 angstroms.
It is formed after fleet plough groove isolation structure 302, the semiconductor substrate 100, which includes small area active area and large area, to be had
Source region is isolated between the Large area active area and the small area active area by fleet plough groove isolation structure 302.
Then, the first floating gate material layer 303 is formed on semiconductor substrate 200, and the material of the first floating gate material layer 103 is excellent
Select non-crystalline silicon, the first floating gate material layer 303 that isolation structure and grid oxic horizon 302 is completely covered.Preferably, the amorphous
The thickness range of silicon is 500 angstroms to 1000 angstroms.Non-limiting examples include process for chemical vapor deposition of materials and physical vapor deposition side
Method.
Then, the second floating gate material layer 304 is formed on the first floating gate material layer 303, it is preferable that described second is floating
Gate material layer 304 is polysilicon layer, and the thickness range of the polysilicon layer is 500 angstroms to 1000 angstroms.Non-limiting examples include
Process for chemical vapor deposition of materials and physical vapor deposition methods.
Low-pressure chemical vapor phase deposition can be selected in the forming method for forming the second floating gate material layer in embodiments of the present invention
(LPCVD) technique.The process conditions for forming the polysilicon layer include：Reaction gas is silane (SiH4), the stream of the silane
It can be 100~200 cc/mins (sccm) to measure range, such as 150sccm；Temperature range can be 700~750 in reaction chamber
Degree Celsius；It can be 250~350 milli millimetress of mercury (mTorr) to react cavity pressure, such as 300mTorr；In the reaction gas also
May include buffer gas, the buffer gas can be helium (He) or nitrogen, the range of flow of the helium and nitrogen can be 5~
20 liters/min (slm), such as 8slm, 10slm or 15slm.
It should be noted that the method for above-mentioned formation the second floating gate material layer is illustrative, it is not limited to described
Method can be applied to the present invention as long as this field other methods can realize the purpose, and details are not described herein.
As shown in Figure 3B, the first floating gate material layer 303 and the second floating gate material layer 304 are handled using flatening process until
Expose fleet plough groove isolation structure 302, to form FGS floating gate structure 305, specifically, executes flatening process, removal all described the
Two floating gate material layers 304 and part the first floating gate material layer 303, until the top for exposing the spacer material layer,
FGS floating gate structure 305 is formed, as shown in Figure 3 C, it is preferable that execute the flatening process using using chemical mechanical grinding.
The planarization on surface can be realized using flattening method conventional in field of semiconductor manufacture.The planarization side
The non-limiting examples of method include mechanical planarization method and chemical mechanical grinding flattening method.Chemical mechanical grinding planarizes
Method is more often used.
Illustratively, using the process of the first floating gate material of chemical mechanical grinding layer 303 and the second floating gate material layer 304
In, when chemical mechanical grinding handles the first floating gate material layer 303, grinding rate is very fast, and institute is handled in chemical mechanical grinding
Grinding rate is slower when stating the second floating gate material layer 304, is equivalent to, the grinding speed when chemical mechanical grinding handles the polysilicon
Degree is slower, and when chemical mechanical grinding handles non-crystalline silicon, grinding rate is very fast.
Illustratively, the first floating gate material layer and the second floating gate material layer are extra after planarized process
First floating gate material layer and the second floating gate material layer are removed.
Illustratively, the second floating gate material layer after chemical mechanical grinding through completely removing the second floating boom material
The bed of material, the first floating gate material layer get rid of the first floating gate material layer of part through chemical mechanical grinding later.
After executing flatening process, rapid thermal annealing process is executed to the FGS floating gate structure 305.Described quick
When the temperature of thermal annealing process step is 1000 DEG C, non-crystalline silicon becomes polysilicon after being handled through the rapid temperature annealing.
The annealing steps are usually to be placed in the substrate under the protection of high vacuum or high-purity gas, are heated to certain
Temperature carries out rapid temperature annealing (RTA) technique, is preferably nitrogen or inert gas in high-purity gas of the present invention, described fast
The temperature of fast thermal annealing process step is 800-1200 DEG C, and preferably 1000 DEG C, the thermal anneal step time is 1-300s.
As a further preference, the rapid thermal annealing selected in the present invention can select one kind in following methods：Pulse
Laser short annealing, the short annealing of pulsed electron book, ion beam short annealing, continuous wave laser short annealing and incoherent width
Band light source（Such as halogen lamp, arc lamp, graphite heating）Short annealing etc., but it is not limited to examples cited.
With reference to Fig. 4, it is shown to make the technique stream of embedded flash memory floating boom according to one embodiment of the present invention
Cheng Tu, the flow for schematically illustrating entire manufacturing process.
In step 401, semiconductor substrate is provided, semiconductor substrate is had into memory cell region and logic region, position
Fleet plough groove isolation structure in semiconductor substrate, is formed with grid oxic horizon on a semiconductor substrate；
In step 402, the first floating gate material layer is formed on the semiconductor substrate；
In step 403, the second floating gate material layer is formed on the first floating gate material layer；
In step 404, the first floating gate material layer and the second floating gate material layer are planarized using chemical mechanical milling tech.
In conclusion the silicon thin film for using two layers of hardness different according to the method for the present invention replaces one layer of polysilicon membrane,
To solve to form asking for recess in the floating gate polysilicon layer positioned at Large area active area after CMP in floating gate polysilicon layer
Topic, loose window is provided for subsequent technique, to improve the yields of the whole performance and embedded flash memory of embedded flash memory.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
Member it is understood that the invention is not limited in above-described embodiment, according to the present invention can also make more kinds of modifications and
Modification, these variants and modifications are all fallen within scope of the present invention.
Claims (9)
1. a kind of method making semiconductor devices, including：
Semiconductor substrate is provided；
It is formed with hard mask layer on the semiconductor substrate, the hard mask layer includes the oxide skin(coating) stacked gradually and nitridation
Nitride layer；
The hard mask layer and the semiconductor substrate are etched, to form shallow trench；
Spacer material layer, the flush on the surface of the spacer material layer and the hard mask are filled in the shallow trench；
Remove the nitride layer；
The first floating gate material layer is formed on the semiconductor substrate；
The second floating gate material layer is formed on the first floating gate material layer；
Flatening process, the whole second floating gate material layers of removal and part the first floating gate material layer are executed, until dew
Until the top for going out the spacer material layer, FGS floating gate structure is formed；
Wherein, the material hardness of the second floating gate material layer is more than the material hardness of the first floating gate material layer, to avoid
It is recessed in the FGS floating gate structure after executing flatening process.
2. the method as described in claim 1, which is characterized in that the thickness range of the first floating gate material layer be 500 angstroms extremely
1000 angstroms, it is 500 angstroms to 1000 angstroms that the material of the second floating gate material layer, which is thickness range,.
3. the method as described in claim 1, which is characterized in that the material of the first floating gate material layer is non-crystalline silicon, described
The material of second floating gate material layer is polysilicon.
4. the method as described in claim 1, which is characterized in that the step of forming the first floating gate material layer includes first depositing
Polysilicon is formed, pre-amorphous injection then is implemented to the polysilicon.
5. method as claimed in claim 4, which is characterized in that the implant angle of the pre-amorphous injection technology be 0 ° extremely
45°。
6. method as claimed in claim 4, which is characterized in that the injection ion of the pre-amorphous injection technology is high atom
The ion of the ion of quality, the High atomic mass includes germanium, arsenic or antimony.
7. method as claimed in claim 3, which is characterized in that further include carrying out rapid thermal annealing to the FGS floating gate structure to incite somebody to action
The step of non-crystalline silicon is converted into polysilicon.
8. the method for claim 7, which is characterized in that the temperature of the rapid thermal anneal process step be 800 DEG C extremely
1200℃。
9. the method as described in claim 1, which is characterized in that execute the flatening process using chemical mechanical grinding, change
The grinding rate for learning the first floating gate material layer described in mechanical lapping is very fast, and the second floating gate material layer grinds described in chemical mechanical grinding
It is slower to grind speed.
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