CN104835773B - A method of making semiconductor devices - Google Patents
A method of making semiconductor devices Download PDFInfo
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- CN104835773B CN104835773B CN201410045802.4A CN201410045802A CN104835773B CN 104835773 B CN104835773 B CN 104835773B CN 201410045802 A CN201410045802 A CN 201410045802A CN 104835773 B CN104835773 B CN 104835773B
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- 238000002955 isolation Methods 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 121
- 125000006850 spacer group Chemical group 0.000 claims description 67
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- 230000003647 oxidation Effects 0.000 claims description 6
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- 230000015654 memory Effects 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
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- 239000010703 silicon Substances 0.000 description 8
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- 229910000042 hydrogen bromide Inorganic materials 0.000 description 2
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- 238000003698 laser cutting Methods 0.000 description 2
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- 238000001947 vapour-phase growth Methods 0.000 description 2
- -1 8slm Chemical compound 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
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- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a kind of methods for making semiconductor devices, production method according to the present invention proposes the oxide being etched back in sti region and then fills the method to form low K oxide to form fleet plough groove isolation structure in the empty place of the oxide of removal, due to having the oxide compared with low-k to be formed in the interval of floating gate and floating gate, coupling between floating gate and floating gate reduces, to reduce the interference mechanism in semiconductor devices.
Description
Technical field
The present invention relates to semiconductor fabrication process more particularly to a kind of production sides of the isolation structure for NOR Flash
Method.
Background technique
Memory is shown, worldwide, memory chip is about according to investigations recently for storing a large amount of digital informations
The 30% of semiconductor transaction is accounted for, for many years, the progress of technology and the market demand expedite the emergence of more and more highdensity various
Type memory, such as RAM (random access memory), SRAM(Static RAM), DRAM (dynamic RAM) and FRAM
(ferroelectric memory) etc..Wherein, flash memories, that is, FLASH becomes the mainstream of non-volatile semiconductor storage technology, even if
Information in retention tab is remained to after power supply closing；In memory electric erasable and repeatable programming, without special
High voltage；Flash memories have the characteristics that at low cost, density is big.Its unique performance makes it widely apply to each neck
Domain, including embedded system, such as PC and equipment, telecommunications switch, cellular phone, network interconnection apparatus, network interconnection, instrument and meter and automobile
Device, while further including emerging voice, image, data storage class product.In various FLASH devices, insertion
Formula flush memory device is one kind of system on chip (SOC), and integrated logic circuit module and flash memory are electric simultaneously in a piece of integrated circuit
Road module has been widely used in the products such as smart card, microcontroller.
Scalability (scalablity) is the key factor of flash memories technology development, with semiconductor integrated circuit
The maturation of industrial technology increasingly, the rapid development of ultra-large integrated circuit, have higher performance and it is more powerful integrate
The bigger component density of circuit requirement, and between all parts, element or size, size and the space of each element itself
It needs to further reduce, for the flash memories with autoregistration floating gate (self aligned floating gate), float
The distance between grid and floating gate are smaller and smaller, this will generate the performance in interference mechanism limitation flash memory storage area.Floating gate and floating gate it
Between coupling be interference mechanism (disturb mechanisms) generate the main reason for.Therefore, the coupling between floating gate and floating gate
Conjunction is the key factor of flash memories technology development.
Use HARP(high aspect ratio process at present) manufacture craft in shallow trench fill oxide with
It is formed fleet plough groove isolation structure (STI), the dielectric constant of oxide is about 3.9 in the fleet plough groove isolation structure, floating gate and floating gate
Between spacing it is smaller, the coupling between floating gate and floating gate is bigger.Specifically, result C=ks/d of coupling, wherein k is shallow ridges
The dielectric constant of slot fill oxide, s are the area of fleet plough groove isolation structure, d shallow trench isolation knot between floating gate and floating gate
The length of structure, with the diminution of distance between floating gate and floating gate, the coupling between floating gate will cause stronger interference mechanism.
Therefore, it is necessary to a kind of methods of new production semiconductor devices, to solve the problems of the prior art.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, the invention proposes a kind of method for making semiconductor devices, packets
It includes: semiconductor substrate is provided, sequentially form pad oxide and pad nitride layer on the semiconductor substrate；Etch the pad oxygen
Change layer, the pad nitride layer and the semiconductor substrate, to form shallow trench；The first isolation of filling material in the shallow trench
The bed of material, the flush on the surface of first spacer material layer and the pad nitride layer；It is etched back to the described of removal part
First spacer material layer；The second spacer material layer, the second isolation material are formed on remaining first spacer material layer
The flush on the surface of the bed of material and the pad nitride layer, wherein second spacer material layer has than first isolation
The smaller dielectric constant of material layer；The nitride layer and the pad oxide are removed, to expose the semiconductor substrate；Revealing
Tunnel oxide layer is formed on the surface of semiconductor lining out；Floating gate is formed on the tunnel oxide layer；It is etched back to
Remove second spacer material layer of part.
It preferably, further include after second spacer material layer for being etched back to removal part in the semiconductor substrate
On sequentially form gate dielectric layer and control gate material layers the step of.
Preferably, further include after forming the gate dielectric layer and the control gate material layers execution etching technics with
The step of forming gate stack structure.
Preferably, the material of first spacer material layer is oxide, and the material of second spacer material layer is low K
Oxide.
Preferably, the pad oxide with a thickness of 40 angstroms to 200 angstroms, it is described pad nitride layer with a thickness of 500 angstroms extremely
2000 angstroms.
Preferably, the depth for being etched back to first spacer material layer is 300 angstroms to 2500 angstroms.
Preferably, the depth for being etched back to second spacer material layer is 100 angstroms to 2000 angstroms,.
Preferably, the depth for being etched back to first spacer material layer is greater than the depth for being etched back to second spacer material layer
Degree.
Preferably, the depth that first spacer material layer is etched back to is than the depth that second spacer material layer is etched back to
More 100 angstroms to 1000 angstroms.
It is then being removed in conclusion production method according to the present invention proposes the oxide being etched back in sti region
The empty place of oxide fill the method to form low K oxide to form fleet plough groove isolation structure, due to lower dielectric
The oxide of constant is formed in the interval of floating gate and floating gate, and the coupling between floating gate and floating gate reduces, and is partly led to reduce
Interference mechanism in body device.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.In the accompanying drawings,
Figure 1A -1K is according to the correlation step institute of the FGS floating gate structure in one embodiment of the present invention production flash memories
The schematic diagram of the section structure of the device of acquisition；
Fig. 2 is the process flow chart that the FGS floating gate structure in flash memories is made according to one embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it will be apparent to one skilled in the art that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to illustrate the present invention be as
What solve the problems, such as presently, there are.Obviously presently preferred embodiments of the present invention is detailed is described as follows, however removes these and retouch in detail
Outside stating, the present invention can also have other embodiments.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
The oxide skin(coating) in the sti region of nonvolatile memory is etched back to the present invention below in conjunction with Figure 1A -1K
Production method is described in detail, and Figure 1A -1K is the oxygen being etched back in the sti region of nonvolatile memory according to the present embodiment
The structural section figure of memory during compound layer.
As shown in Figure 1A, semiconductor substrate 100 is provided, is formed with trap in the substrate 100 of the semiconductor.
The semiconductor substrate can be following at least one of the material being previously mentioned: silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and
Germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
One bulk silicon substrate 100 including active area is provided, forms liner (pad) oxidation on a semiconductor substrate 100
Layer 101, main material are silica.The pad oxide can be formed by thermal oxidation method, and general thickness is 40~200 angstroms,
It is mainly as separation layer to protect active area when removing silicon nitride not by chemical spot (i.e. as isolating oxide layer).It is padding
Pad nitride layer 102 is formed in oxide layer 101, the preferred silicon nitride layer of the material of nitride layer 102 can use boiler tube deposition side
Method or Low Pressure Chemical Vapor Deposition form pad nitride layer, and thickness is generally 500~2000 angstroms, the pad nitride layer
102 are mainly used for protecting active area during the deposition oxide in fleet plough groove isolation structure, and in chemical mechanical grinding institute
It can be used as the barrier material of grinding when the silica of filling.
Preferably, forming dielectric anti-reflective coating (DARC) on pad nitride layer 102, material is nitrogen oxidation
Silicon can prepare dielectric anti-reflective coating using the method for chemical gas deposition, and deposition forms the mesh of dielectric anti-reflective coating
Be reflectivity in order to reduce silicon nitride layer, photoresist layer is formed on dielectric anti-reflective coating, using photoetching process, warp
Exposure development and etc. rear form patterned photoresist layer.
In a specific embodiment of the invention, the method for shallow trench 103 is defined are as follows: apply lighting in semiconductor substrate surface
Photoresist is exposed photoresist and develops, and predefined figure is transferred on photoresist.According to patterned photoresist layer
It is sequentially etched dielectric anti-reflective coating, pad nitride layer 102, pad oxide 101.Wherein, etching gas can be used and is based on
The mixed gas of the gas of chlorine or gas based on hydrogen bromide or both.Using dry etch process, dry etching work
Skill includes but is not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Preferably by
One or more RIE step carries out dry etching.The range of flow of etching gas can be 0~200 cc/min
(sccm), reaction room pressure can be 5~20 milli millimetress of mercury (mTorr).Then, patterned photoresist, dielectric are removed
Anti-reflection coating, to form opening in pad nitride layer 102 and pad oxide skin(coating) 101.Then, then main etching is carried out, with shape
At shallow trench 103.Specifically, according to pad nitride layer 102 and padding the opening etched portions semiconductor in oxide skin(coating) 101
Substrate 100, to form shallow trench 103.The etching agent generallyd use is fluorine-containing gas, such as CF4Or CHF3.It can use
Dry etching, such as reactive ion etching, ion beam etching, plasma etching, any group of laser ablation or these methods
It closes.Single lithographic method can be used, or more than one lithographic method also can be used.Etching gas include HBr,
Cl2、CH2F2、O2One or several kinds of gases and some addition gas such as nitrogen, argon gas.The flow model of the etching gas
Enclosing to be 0~150 cc/min (sccm), and reaction room pressure can be 3~50 millitorrs (mTorr), be in radio-frequency power
Plasma etching is carried out under conditions of 600W~1500W.
Then, as shown in Figure 1B, carry out shallow trench 103 filling, in the shallow trench 103 and pad silicon nitride layer
Depositing isolation material layer 104 on 102, the material of spacer material layer 104 are oxide, the preferred silica of spacer material layer 104.
Spacer material layer 104 is formed in shallow trench 103 and on pad silicon nitride layer 102 using HARP technique, material is isolated
The bed of material 104 fills groove 103, and spacer material layer 104 covers semiconductor substrate 100, the thickness range of spacer material layer 104
It is 800 angstroms to 9000 angstroms.
In a specific embodiment of the invention, using HDP(high-density plasma) depositing operation is in the shallow trench
And spacer material layer is formed on nitride layer, the material of spacer material layer is preferably silica, highly dense using HDP-CVD(
Spend plasma chemical vapor deposition) formed oxide skin(coating), HDP-CVD technique be synchronously carried out in the same reaction chamber it is heavy
Product is reacted with sputtering, and the reaction gas that HDP-CVD technique uses includes SiH4And O2And the gas hydrogen and helium of sputtering.
Since deposition and sputtering technology carry out simultaneously, by adjusting SiH4And O2And the content of hydrogen and helium is so that sputtering is heavy
Product is than being 1:1.
Planarization process, the surface of the spacer material layer 104 and institute are carried out to the spacer material layer 104 of semiconductor substrate
The flush of pad silicon nitride layer 102 is stated, specifically, executing flatening process using chemical mechanical grinding.
As shown in Figure 1 C, it is etched back to the spacer material layer 104 that removal part is located in shallow trench 103, to form groove
105, the depth bounds for being etched back to removal spacer material layer are 300 angstroms to 2500 angstroms, the remaining spacer material layer after being etched back to
104'.Wet etching or dry etching can be used by being etched back to technique.
In a specific embodiment of the invention, technique, dry method etch technology can be etched back to using dry etching execution
Including but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.For example, by using etc.
Plasma etching, etching gas can be using based on oxygen (O2- based) gas.Specifically, using lower RF energy
And low pressure and highdensity plasma gas can be generated to realize dry etching.As an example, using plasma is carved
Etching technique, the etching gas used is based on oxygen (O2- based) gas, the range of flow of etching gas can be 50 cubes
Cm per minute (sccm)~150 cc/min (sccm), reaction room pressure can be 5 millitorrs (mTorr)~20 millitorr
(mTorr).Wherein, the etching gas of dry etching can also be bromination hydrogen, carbon tetrafluoride gas or nitrogen trifluoride gas
Body.It should be noted that above-mentioned engraving method is only exemplary, limitation and this method, those skilled in the art may not be used also
To select other common methods.
As shown in figure iD, spacer material layer 106 is formed on a semiconductor substrate 100, wherein described have from material layer 106
Than the smaller dielectric constant of the spacer material layer 104, the material of spacer material layer 106 is low k oxide, for example, isolation material
The material of the bed of material 106 can be the silica of the silica of carbon doping, boron doped silica or phosphorus doping, isolation
Material layer 106 fills groove 105 and covering pad silicon nitride layer 102.Then, it executes flatening process and gets rid of extra isolation material
The bed of material 106, so that the top of spacer material layer 106 and the top of pad silicon nitride layer 102 flush, as referring to figure 1E, using chemistry
Mechanical lapping executes flatening process.
As shown in fig. 1F, removal pad oxide 101 and pad nitride layer 102, to expose the surface of semiconductor substrate 100,
The top of spacer material layer 106 is higher than the surface of semiconductor substrate 100.
Illustratively, removing nitride layer 102 and pad oxide 101, the wet-cleaning using wet-cleaning can be used
One of diluted hydrofluoric acid or hot phosphoric acid or two kinds of removal pad oxides 101 and nitride layer 102.The wet process is carved
Erosion is to spacer material layer 104,106 etching selection ratios with higher.
Then, to flash cell execute Vt injection step again by the way of ion implanting in semiconductor substrate 100 shape
It at the well region of different function, is equivalent to, the well region of different function, the well region of different function is defined by way of ion implanting
Including high pressure P/N well region and low pressure P/N well region, entirety is carried out after defining different function well region and pushes away trap technique.
As shown in Figure 1 G, tunnel oxide skin(coating) 107, the tunnelling oxygen are formed on 100 surface of the semiconductor substrate of exposing
The material for changing layer 107 can be silica, silicon oxynitride, silicon rich oxide, silicon nitride.The effect of the tunnel oxide is
Floating gate polysilicon layer and semiconductor substrate isolation, thickness are set in 10 angstroms to 150 angstroms.The technology for depositing above-mentioned tunnel oxide is
The prior art well known to those skilled in the art such as forms silicon oxide layer using thermal oxidation technology.
As shown in fig. 1H, deposition forms floating gate material layer on a semiconductor substrate 100, and the material of floating gate material layer is preferably more
106 tunnel oxide 107 of spacer material layer is completely covered in crystal silicon, the floating gate material layer.
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method for forming floating gate material layer in the present invention.
It is silane (SiH4) that the process conditions for forming the polysilicon layer, which include: reaction gas, and the range of flow of the silane can be 100
~200 cc/mins (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；Reaction chamber
Interior pressure can be 250~350 milli millimetress of mercury (mTorr), such as 300mTorr；It may also include buffering gas in the reaction gas
Body, the buffer gas can be helium (He) or nitrogen, and the range of flow of the helium and nitrogen can be 5~20 liters/min
(slm), such as 8slm, 10slm or 15slm.
It should be noted that the method for above-mentioned formation floating gate material layer is illustrative, it is not limited to the method,
As long as this field other methods can be realized the purpose, the present invention can be applied to, details are not described herein.
Flatening process is executed to floating gate material layer, until the top for exposing the spacer material layer 106, to be formed
FGS floating gate structure 108.Optionally, it after exposing the top of the spacer material layer 106 in shallow plough groove isolation area, carries out certain
Amount crosses polishing to guarantee that process window then stops flatening process, to form FGS floating gate structure 108.Pass through planarization process treating
Filling is set to be formed in the FGS floating gate structure 108 on tunnel oxide layer 107 and between spacer material layer 106 after floating gate material layer
It is separated from each other.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The planarization side
The non-limiting example of method includes mechanical planarization method and chemically mechanical polishing flattening method.Chemically mechanical polishing planarization
Method is more often used.
Such as Fig. 1 I, execute be etched back to technique to remove the spacer material layer 106 of part, the technique that is etched back to is each
Spacer material layer 106 is etched to the same sex, specifically, being first located at fleet plough groove isolation structure region using wet etching removal part
In spacer material layer 106, remaining spacer material layer 106 ' is higher than tunnel oxide layer lower than FGS floating gate structure 108 after etching
107.Wherein, being etched back to removal 106 depth of part spacer material layer is 100 angstroms to 2000 angstroms, is etched back to removal part isolation material
The depth of the bed of material 106 is less than the depth for being etched back to removal part spacer material layer 104, is etched back to removal part isolation material for the second time
The depth of the bed of material 106 is 100 angstroms to 1000 angstroms smaller than the depth for being etched back to removal part spacer material layer 104 for the first time.
In a specific embodiment of the invention, after using spacer material layer 106 described in wet etching, formation every
It is flat from 106 ' surface of material layer, wet etch method can use hydrofluoric acid solution, such as buffer oxide etch agent or hydrogen
Fluoric acid buffer solution.Wet-cleaning removes the spacer material layer using diluted hydrofluoric acid and hot phosphoric acid.
As shown in figure iJ, gate dielectric layer 109 is formed in the semiconductor substrate 100, gate dielectric layer 109 can be oxidation
Object, nitride, oxide three layers of ONO sandwich structure in total, those skilled in the art is it should be understood that gate dielectric layer
109 may be that the gate dielectric layers such as one layer of oxide are formed on one layer of nitride or one layer of oxide or one layer of nitride
Structure.Can be used including but not limited to: the method for process for chemical vapor deposition of materials and physical vapor deposition methods forms grid dielectric
Layer 109.
Such as Fig. 1 K, gate material layers 110 are formed on gate dielectric layer 109 and are used to form control grid, specifically, in flash memory
Gate material layers 110 are formed on gate dielectric layer 109 in unit area, the material of gate material layers 110 is polysilicon.Then,
Etch step is executed to form gate stack structure to semiconductor devices described above.
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon.Form the work of the polysilicon
Skill condition includes: that reaction gas is silane (SiH4), the range of flow of the silane can be 100~200 cc/mins
(sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；Reacting cavity pressure can be 250~350
Milli millimetres of mercury (mTorr), such as 300mTorr；It may also include buffer gas in the reaction gas, the buffer gas can be
The range of flow of helium or nitrogen, the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
Referring to Fig. 2, it is shown to make the FGS floating gate structure in flash memories according to one embodiment of the present invention
Process flow chart.For schematically illustrating the process of entire manufacturing process.
In step 201, providing one includes active area bulk silicon substrate, forms pad oxide on a semiconductor substrate,
Pad silicon nitride layer is formed on pad oxide, pad silicon nitride layer, pad oxide and semiconductor substrate is sequentially etched, to form shallow ridges
Slot；
In step 202, the first spacer material layer is filled in the shallow trench, then executes flatening process；
In step 203, it is etched back to first spacer material layer of removal part；
In step 204, the second spacer material layer is formed on the semiconductor substrate；
In step 205, flatening process is executed to expose the pad silicon nitride layer；
In step 206, the pad silicon nitride layer and the pad oxide are removed, to expose semiconductor substrate surface；
In step 207, tunnel oxide layer is formed on the surface of the semiconductor substrate of exposing, then in tunnel oxide
Floating gate is formed in nitride layer；
In a step 208, it is etched back to second spacer material layer of removal part；
In step 209, gate dielectric layer and control gate material layers are sequentially formed on the semiconductor substrate.
It is then being removed in conclusion production method according to the present invention proposes the oxide being etched back in sti region
The empty place of oxide fill the method to form low K oxide to form fleet plough groove isolation structure, due to lower dielectric
The oxide of constant is formed in the interval of floating gate and floating gate, and the coupling between floating gate and floating gate reduces, and is partly led to reduce
Interference mechanism in body device.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
Member it is understood that the present invention is not limited to the above embodiments, can also make according to the present invention more kinds of modifications and
Modification, all fall within the scope of the claimed invention for these variants and modifications.
Claims (8)
1. a kind of method for making semiconductor devices, comprising:
Semiconductor substrate is provided,
Pad oxide and pad nitride layer are sequentially formed on the semiconductor substrate；
The pad nitride layer, the pad oxide and the semiconductor substrate are etched, to form shallow trench；
The first spacer material layer, the surface of first spacer material layer and the pad nitride layer are filled in the shallow trench
Flush；
It is etched back to first spacer material layer of removal part；
Form the second spacer material layer on remaining first spacer material layer, the surface of second spacer material layer with
The flush of the pad nitride layer, wherein second spacer material layer is with more smaller than first spacer material layer
Dielectric constant, the material of first spacer material layer are oxide, and the material of second spacer material layer is low K oxidation
Object；
The pad nitride layer and the pad oxide are removed, to expose the semiconductor substrate；
Tunnel oxide layer is formed on the surface of the semiconductor substrate of exposing；
Floating gate is formed on the tunnel oxide layer；
It is etched back to second spacer material layer of removal part.
2. the method as described in claim 1, which is characterized in that further include in the second isolation material for being etched back to removal part
The step of gate dielectric layer and control gate material layers are sequentially formed after the bed of material on the semiconductor substrate.
3. method according to claim 2, which is characterized in that further include forming the gate dielectric layer and the control grid
The step of etching technics is to form gate stack structure is executed after material layer.
4. the method as described in claim 1, which is characterized in that the pad oxide with a thickness of 40 angstroms to 200 angstroms, the pad
Nitride layer with a thickness of 500 angstroms to 2000 angstroms.
5. the method as described in claim 1, which is characterized in that the depth for being etched back to first spacer material layer is 300 angstroms
To 2500 angstroms.
6. the method as described in claim 1, which is characterized in that the depth for being etched back to second spacer material layer is 100 angstroms
To 2000 angstroms.
7. the method as described in claim 1, which is characterized in that the depth for being etched back to first spacer material layer is greater than back quarter
Lose the depth of second spacer material layer.
8. the method as described in claim 1, which is characterized in that the depth that first spacer material layer is etched back to is than described
The depth that two spacer material layers are etched back to is 100 angstroms to 1000 angstroms more.
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| US20070212874A1 (en) * | 2006-03-08 | 2007-09-13 | Micron Technology, Inc. | Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device |
| CN101299442A (en) * | 2007-04-30 | 2008-11-05 | 三星电子株式会社 | Non-volatile semiconductor device including floating gate, method for manufacturing non-volatile semiconductor device and related system |
| US20110278658A1 (en) * | 2007-05-14 | 2011-11-17 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of manufacturing the same |
| US20120126303A1 (en) * | 2010-11-18 | 2012-05-24 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing nonvolatile semiconductor memory device |
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| US20070212874A1 (en) * | 2006-03-08 | 2007-09-13 | Micron Technology, Inc. | Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device |
| CN101299442A (en) * | 2007-04-30 | 2008-11-05 | 三星电子株式会社 | Non-volatile semiconductor device including floating gate, method for manufacturing non-volatile semiconductor device and related system |
| US20110278658A1 (en) * | 2007-05-14 | 2011-11-17 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of manufacturing the same |
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