CN106252286A - The system of selection of the polysilicon dry etching process of embedded flash memory - Google Patents
The system of selection of the polysilicon dry etching process of embedded flash memory Download PDFInfo
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- CN106252286A CN106252286A CN201610885898.4A CN201610885898A CN106252286A CN 106252286 A CN106252286 A CN 106252286A CN 201610885898 A CN201610885898 A CN 201610885898A CN 106252286 A CN106252286 A CN 106252286A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 117
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 117
- 238000000034 method Methods 0.000 title claims abstract description 83
- 230000008569 process Effects 0.000 title claims abstract description 80
- 238000001312 dry etching Methods 0.000 title claims abstract description 61
- 238000007667 floating Methods 0.000 claims abstract description 163
- 238000005530 etching Methods 0.000 claims abstract description 88
- 230000007334 memory performance Effects 0.000 abstract description 3
- 239000000047 product Substances 0.000 description 28
- 239000010410 layer Substances 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 108700002783 roundabout Proteins 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The system of selection of the polysilicon dry etching process of a kind of embedded flash memory, said method comprising the steps of: provide the domain of the active area of described embedded flash memory and the domain of floating gate region；Domain according to described active area and the domain of floating gate region, determine the layout density of described active area and the actual etching area of described floating gate region, and described actual etching area is the region by dry etching process etching polysilicon；Layout density according to described actual reproduction region and the oxide layer being positioned under described polysilicon preset thickness after the etching, selects corresponding dry etching process.The present invention program can select suitable polysilicon dry etching process, thus accurately control floating boom sharp distal tip according to the layout density of the actual etching area of polysilicon, to improve flash memory performance.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, the polysilicon dry etching process of a kind of embedded flash memory
System of selection.
Background technology
In embedded flash memory, the height of floating boom sharp distal tip and sharpness can affect floating boom programming, erasable time coupling
Close voltage, and then affect flash memory program, erasable time performance.Therefore, floating boom sharp distal tip is accurately controlled for controlling to dodge
The performance deposited is significant.In concrete technology is implemented, polysilicon dry etching process (Poly Dry-Etch) can be passed through
The precise degrees of the thickness of rear residual oxide layer (such as silicon dioxide, silicon nitride etc.) on the active area knows floating boom tip
Tip is the most accurate.
In the prior art, for the product determined, can be close according to the domain of the layout density of active area or floating gate region
Degree, and it is positioned at the preset thickness after the etching of the oxide layer under described polysilicon, select polysilicon dry etching process.This be because of
For, understand according to the load effect (loading effect) of etch process, the etch-rate ratio in the region that reaction density is bigger
The less region of density is slow, is i.e. actually needed that to carry out the polysilicon of dry ecthing the most, and occupied area is the biggest, can select etching speed
The etch process that rate is the fastest, etching period is the longest or etch temperature is the highest.Wherein it is possible to pass through chip area and the product in region
The area of whole domain of product is divided by, to obtain the layout density in described region.
More specifically, according to the layout density of active area or the layout density of floating gate region, needs can be carried out dry corrosion
The area of the polysilicon carved carries out pre-judgement.Specifically, the layout area of embedded flash memory comprises memory area and logic
Region, in memory area, active area is evenly distributed with the territory pattern of floating gate region, namely active area or floating gate region
Chip area has linear relationship, described active area or the chip area of floating gate region with the area needing the polysilicon being etched
The biggest, need the area carrying out the polysilicon of dry ecthing the biggest.
It is possible to further according to the layout density of active area or the size of the layout density of floating gate region, in conjunction with oxide layer
Preset thickness after the etching, selects polysilicon dry etching process.
But, for new product, only by the domain of active area, or only by the domain of floating gate region, it is difficult to through pre-
Judging i.e. to select correct dry etching process, cause the oxidated layer thickness obtained not meet expection, floating boom sharp distal tip controls
The most accurate.This is because, in logic region, active area and the territory pattern of floating gate region uneven arrangement, i.e. active area
Or the chip area of floating gate region is with to need the area of polysilicon being etched be non-linear relation, namely active area or floating gate region
The big product of chip area, need the area carrying out the polysilicon of dry ecthing but may not be big.The feature of this non-linear relation,
For the product that logic region area ratio is bigger, the most prominent.
Summary of the invention
Present invention solves the technical problem that the system of selection of the polysilicon dry etching process being to provide a kind of embedded flash memory,
Suitable polysilicon dry etching process can be selected according to the layout density of the actual etching area of polysilicon, thus to floating boom
The pattern of sharp distal tip accurately controls, to improve flash memory performance.
For solving above-mentioned technical problem, the embodiment of the present invention provides the polysilicon dry etching process of a kind of embedded flash memory
System of selection, comprises the following steps: provide the domain of the active area of described embedded flash memory and the domain of floating gate region；According to described
The domain of active area and the domain of floating gate region, determine that described active area is close with the domain of the actual etching area of described floating gate region
Degree, described actual etching area is the region by dry etching process etching polysilicon；According to described actual reproduction region
Layout density and the oxide layer being positioned under described polysilicon preset thickness after the etching, selects corresponding dry etching process.
Optionally, described determine that described active area includes with the layout density of the actual etching area of described floating gate region: root
According to domain and the domain of floating gate region of described active area, determine the overlapping region of described floating gate region and described active area；According to institute
The layout density of the layout density and described overlapping region of stating active area determines the layout density of described actual etching area.
Optionally, described actual erosion is determined according to the layout density of described active area and the layout density of described overlapping region
The layout density carving region includes: utilize the layout density of described active area to deduct the layout density of described overlapping region, with
Layout density to described actual etching area.
Optionally, the layout density of described overlapping region is multiplied by the first default ratio equal to the layout density of described floating gate region
Value.
Optionally, described determine that described active area includes with the layout density of the actual etching area of described floating gate region: root
According to domain and the domain of floating gate region of described active area, determine the overlapping region of described floating gate region and described active area, described heavy
Close the layout density in region as the first layout density；Determine the layout density of the actual etching area of described floating gate region, as
Second layout density；Layout density according to described active area, described first layout density and the second layout density, determine described
The layout density of the actual etching area of active area and described floating gate region.
Optionally, utilize the layout density of described active area to deduct described first layout density and add described second domain
Density, to obtain the layout density of described active area and the actual etching area of described floating gate region.
Optionally, the etch depth of described polysilicon is calculated according to the volume of the polysilicon of etching actual in described floating gate region
Value；The volume of described floating gate region under same depth is calculated according to described etch depth value；Actual etching in calculating described floating gate region
The ratio of volume of volume and described floating gate region of polysilicon；The layout density utilizing described floating gate region is multiplied by described ratio,
To determine the layout density of the actual etching area of described floating gate region.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that
The embodiment of the present invention provides the system of selection of the polysilicon dry etching process of a kind of embedded flash memory, including following step
Rapid: the domain of the active area of described embedded flash memory and the domain of floating gate region are provided；Domain according to described active area and floating boom
The domain in district, determines the layout density of described active area and the actual etching area of described floating gate region, described actual etching area
For the region by dry etching process etching polysilicon；Layout density according to described actual reproduction region and be positioned at described many
Oxide layer under crystal silicon preset thickness after the etching, selects corresponding dry etching process.Use the embodiment of the present invention, Ke Yigen
According to the layout density of the actual etching area of polysilicon, select suitable polysilicon dry etching process, thus to floating boom distal tip
The pattern of end accurately controls, to improve flash memory performance.
Further, in embodiments of the present invention, during for need not in floating gate region, polysilicon is etched, can
The layout density of actual etching area is calculated to be subtracted each other by layout density or to be multiplied by the multiple calculations such as default ratio, for
User provides convenient.
Further, in embodiments of the present invention, during for needing in described floating gate region, polysilicon to be etched,
Acquisition floating gate region can be more precisely calculated according to the volume of polysilicon of etching actual in floating gate region and the volume of floating gate region
The layout density of the polysilicon of interior actual etching, contributes to calculating the layout density of actual etching area, enters
And select more particularly suitable polysilicon dry etching process, thus the pattern of floating boom sharp distal tip is accurately controlled.
Accompanying drawing explanation
Fig. 1 is the flow process of the system of selection of the polysilicon dry etching process of a kind of embedded flash memory in the embodiment of the present invention
Figure；
Fig. 2 shows the domain of a kind of active area in the embodiment of the present invention and the arrangement mode of the domain of floating gate region；
Fig. 3 to Fig. 4 is the cross-sectional view of the polysilicon dry etching process process in first embodiment of the invention.
Fig. 5 to Fig. 6 is the cross-sectional view of the polysilicon dry etching process process in second embodiment of the invention.
Detailed description of the invention
As it was previously stated, in embedded flash memory, the height of floating boom sharp distal tip and sharpness can affect floating boom in programming, wiping
When writing coupling voltage, and then affect flash memory program, erasable time performance.Specifically, too low, the most blunt floating boom tip
Most advanced and sophisticated can cause too small tunnelling current, and then owing to electric field intensity is too low, programming, erasable electric current is too small and causes programming, wipe
Write the situation of overlong time.
In concrete technology is implemented, can be by remaining the thickness of oxide layer on the active area after polysilicon dry etching process
The precise degrees of degree knows that floating boom sharp distal tip is the most accurate.Specifically, the oxide layer of residual is the thinnest, represents that polysilicon is done
Etch the heaviest to the etching degree of described floating boom sharp distal tip, be more easily caused floating boom sharp distal tip too low, the most blunt.But chase after simply
Seek blocked up oxide layer, it is possible to cause polysilicon etch not enough, time serious, cause component failure.So, keep oxide layer
The precision of thickness is significant.
In the prior art, for the product determined, can be close according to the domain of the layout density of active area or floating gate region
Degree, by selecting polysilicon dry etching process, it is thus achieved that corresponding oxidated layer thickness.But, for new product, only pass through active area
Domain, or only by the domain of floating gate region, it is difficult to select correct dry etching process, cause the oxidated layer thickness that obtains not
Meeting expection, floating boom sharp distal tip controls the most accurate.
The present inventor finds through research, the problems referred to above it is critical only that prior art relies only on active area or floating
Monolayer domain in grid region, it is difficult to accurately calculate the layout density of actual etching and the dependency of etch-rate.This is because,
In logic region, active area and the territory pattern of floating gate region the chip area of uneven arrangement, i.e. active area or floating gate region
It is non-linear relation with needing the area of polysilicon being etched, namely the product that the chip area of active area or floating gate region is big
Product, need the area carrying out the polysilicon of dry ecthing but may not be big.
Use the embodiment of the present invention, by active area and floating gate region two-layer domain being analyzed simultaneously, can be in conjunction with two
Layer domain is calculated the layout density of the actual etching area of polysilicon, thus selects correct polysilicon dry etching process,
So that floating boom sharp distal tip is accurately controlled.
Understandable for enabling the above-mentioned purpose of the present invention, feature and beneficial effect to become apparent from, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Reference Fig. 1, Fig. 1 are the selecting partys of the polysilicon dry etching process of a kind of embedded flash memory in the embodiment of the present invention
The flow chart of method.The system of selection of the polysilicon dry etching process of described embedded flash memory includes that step S101 is to step S103.
Step S101: the domain of the active area of described embedded flash memory and the domain of floating gate region are provided.
Step S102: according to domain and the domain of floating gate region of described active area, determines described active area and described floating boom
The layout density of the actual etching area in district, described actual etching area is the region by dry etching process etching polysilicon.
Step S103: layout density and the oxide layer being positioned under described polysilicon according to described actual reproduction region exist
Preset thickness after etching, selects corresponding dry etching process.
In being embodied as of step S101, the domain of the active area of embedded flash memory and the domain of floating gate region can led
Enter the product stage of described embedded flash memory, obtain in the product layout information imported.
Fig. 2 shows the domain of a kind of active area in the embodiment of the present invention and the arrangement mode of the domain of floating gate region.As
Shown in Fig. 2, the domain of active area 110 is cross arrangement with the domain of floating gate region 120, forms the district that overlaps of floating gate region and active area
Territory 121.
Wherein, the dotted line connecting A to B can serve to indicate that the polysilicon dry etching process process to embedded flash memory is carried out
During section detection, selectable profile position.Concrete cross-sectional view will be described hereinafter.
As it was previously stated, the layout area of embedded flash memory comprises memory area and logic region, in memory area,
Active area 110 arranges in an uniform way with the domain of floating gate region 120, such as the cross arrangement mode shown in Fig. 2, now active area
110 or the chip area of floating gate region 120 and the area of overlapping region 121 there is linear relationship.But it is in logic region, active
The territory pattern arrangement mode of district 110 or floating gate region 120 presents multiformity, complexity, i.e. active area 110 or floating gate region 120
The area of chip area and overlapping region 121 not there is linear relationship.
With continued reference to Fig. 1, in being embodied as of step S102, according to domain and the version of floating gate region of described active area
Figure, determines the layout density of described active area and the actual etching area of described floating gate region, and described actual etching area is for passing through
The region of dry etching process etching polysilicon.
In the first embodiment of the present invention, it is not necessary in the layout area of floating gate region, polysilicon is etched, only
The polysilicon to being positioned in remaining region above active area is needed to be etched PROCESS FOR TREATMENT.
Reference Fig. 3, Fig. 3 are the cross-section structure signals of the polysilicon dry etching process process in first embodiment of the invention
Figure.Its profile position connects the dotted line of A to B as shown in Figure 2.
As it is shown on figure 3, on Semiconductor substrate 100 surface, be sequentially formed with oxide 101, floating boom (Floating Gate)
111 and floating boom side wall (Floating Gate Spacer) 112.At the oxide not covered by floating boom 111 and floating boom side wall 112
On 101 regions, it is formed with polysilicon 130 to be etched.
Wherein, the region between the edge of adjacent floating boom side wall 112 is floating gate region 120 (with reference to Fig. 2), floating gate region 120
Having included at least the polysilicon 131 between floating boom side wall 112 and floating boom side wall 112, wherein, the edge of floating boom side wall 112 is
The edge that floating boom side wall 112 is adjacent with polysilicon 130 to be etched.Floating boom side wall 112 is using as polysilicon dry etching process
Hard mask layer (Hard Mask), controls described etching step and occurs over just the region do not protected by floating boom side wall 112.
It is pointed out that between adjacent floating boom side wall 112, i.e. also shape in the region of floating gate region 120 (with reference to Fig. 2)
Become to have polysilicon 131.In the manufacturing process of the embedded flash memory product of the embodiment of the present invention, it is coated with protective layer 121 to protect
Protect it to be not etched by.Therefore, in the first embodiment, the actual etching area that polysilicon dry etching process processes only includes many
Crystal silicon 130 is etched.
Fig. 4 is illustrated that after described polysilicon dry etching process, it is thus achieved that the cross-section structure of embedded flash memory show
It is intended to.
As shown in Figure 4, after polysilicon 130 (with reference to Fig. 3) is etched, floating boom sharp distal tip 113 and position are exposed
Oxide layer 101 under polysilicon.
Wherein, the pattern accurately controlling floating boom sharp distal tip 113 is significant for the performance controlling flash memory.Specifically
For, if etching is excessively, cause described floating boom sharp distal tip 113 to be excessively passivated, will affect embedded flash memory programming, erasable
Time performance.Whereas if undercut, the polysilicon 130 of residual may cause bridge joint short circuit (bridge) phenomenon, reduce and produce
The yield of product.
According to prior art, it is thus achieved that the layout density of actual etching area the most accurate, more can select more adduction
Suitable polysilicon dry etching process.
With continued reference to Fig. 1, in the one of described first embodiment is embodied as, according to the domain of described active area and floating
The domain in grid region, it may be determined that overlapping region, and then according to the layout density of described active area and the domain of described overlapping region
Density may determine that the layout density of described actual etching area.
In being embodied as, can be by the domain of described active area and the domain of floating gate region be processed, to determine
Overlapping region.Such as by conventional Overlapping radar image, repeat data processing technique etc..This is not limited by the embodiment of the present invention
System.
It is possible to further utilize the layout density of described active area to deduct the layout density of described overlapping region, with
Layout density to described actual etching area.
Specifically, according to the region that overlapping region is the active area blocked by floating gate region, can be by the domain of active area
Density deducts the layout density of overlapping region, to obtain the layout density of actual etching area, thus obtains not hidden by floating gate region
The layout density of the polysilicon above the active area of gear.
In the another kind of described first embodiment is embodied as, the layout density of described overlapping region is equal to described floating boom
The layout density in district is multiplied by the first default ratio.
Specifically, the first ratio is in the region of floating gate region, the layout density ratio that active area occupies, namely active area accounts for
According to area ratio.
The first ratio preset can be configured according to the empirical value of the manufacturing process of similar-type products, it is also possible to is leading
Enter the product stage of described embedded flash memory, obtained by the product layout information imported.The present invention is to obtaining the first ratio
Mode does not limits.As a nonrestrictive example, can arrange the first default ratio is 50%, now in floating gate region
Region in, the area equation of active area and non-active area (such as shallow trench isolation region).
In the first embodiment of the present invention, for need not in the layout area of floating gate region, polysilicon is etched
Situation, can select multiple calculation calculate actual etching area layout density, provide the user convenience.
In the second embodiment of the present invention, except being positioned at the polysilicon above active area, in addition it is also necessary in described floating gate region
Layout area in polysilicon is etched PROCESS FOR TREATMENT.
Reference Fig. 5, Fig. 5 are the cross-section structure signals of the polysilicon dry etching process process in second embodiment of the invention
Figure.Its profile position connects the dotted line of A to B as shown in Figure 2.
As it is shown in figure 5, on Semiconductor substrate 200 surface, be sequentially formed with oxide 201, floating boom 211 and floating boom side wall
212.On oxide 201 region not covered by floating boom 211 and floating boom side wall 212, it is formed with polysilicon 230 to be etched,
And between adjacent floating boom side wall 212, it is formed with polysilicon 231 to be etched.Wherein, the limit of adjacent floating boom side wall 212
Region between edge is floating gate region 120 (with reference to Fig. 2), and floating gate region 120 has included at least floating boom side wall 212 and floating boom side wall
Polysilicon 231 between 212, wherein, the edge of floating boom side wall 212 is that floating boom side wall 212 is adjacent with polysilicon 230 to be etched
Edge.
In a second embodiment, the actual etching area that polysilicon dry etching process processes includes polysilicon 230 with many
Crystal silicon 231 is etched.
Fig. 6 is illustrated that after described polysilicon dry etching process, it is thus achieved that the cross-section structure of embedded flash memory show
It is intended to.
As shown in Figure 6, after polysilicon 230 (with reference to Fig. 5) is etched, floating boom sharp distal tip 213 and position are exposed
Oxide layer 201 under polysilicon.The polysilicon 231 of partial volume is etched simultaneously.
With continued reference to Fig. 1, in described second embodiment of the invention, according to domain and the version of floating gate region of described active area
Figure, determines the overlapping region of described floating gate region and described active area, and the layout density of described overlapping region is close as the first domain
Degree.
According to Such analysis, utilize the layout density of described active area to deduct described first layout density, be
In the oxide areas not covered by floating boom and floating boom side wall, determine the layout density of polysilicon to be etched.
Further, it is determined that the layout density of the actual etching area of described floating gate region, as the second layout density, it is
Between adjacent floating boom side wall, determine the layout density of polysilicon to be etched.
Further, utilize the layout density of described active area to deduct described first layout density and add described second
Layout density, to obtain the layout density of described active area and the actual etching area of described floating gate region.
In view of the polysilicon between adjacent floating boom side wall is not completely etched away, can be by calculating described floating boom
In district, the volume of the polysilicon of actual etching obtains the second layout density with the ratio of the volume of described floating gate region under same depth.
Specifically, the etch depth of described polysilicon is calculated according to the volume of the polysilicon of etching actual in described floating gate region
Value, calculates the volume of described floating gate region under same depth according to described etch depth value, actual etching in calculating described floating gate region
The ratio of volume of volume and described floating gate region of polysilicon, and then utilize the layout density of described floating gate region to be multiplied by described ratio
Value, to determine the layout density of the actual etching area of described floating gate region, namely the second layout density.
Wherein, in described floating gate region, the volume of the polysilicon of actual etching can be according to the manufacturing process of similar-type products
Empirical value obtains, such as after polysilicon dry etching process, by SEM (Scanning Electronic
Microscope, scanning electron microscope) obtain embedded flash memory product or the profile of semi-finished product, measured calculating obtains
?.
In embodiments of the present invention, feelings polysilicon being etched in the layout area of described floating gate region by needs
Condition, in the range of can calculating the domain obtaining floating gate region the most accurately, the layout density of the polysilicon of actual etching, contributes to
Calculate the layout density of actual etching area, thus select more particularly suitable polysilicon dry etching process.
In being embodied as of step S103, according to the layout density in described actual reproduction region be positioned at described polycrystalline
Oxide layer under silicon preset thickness after the etching, selects corresponding polysilicon dry etching process.
In the prior art, can be according to the experience of the manufacturing process of similar-type products, it is thus achieved that the domain of etching area is close
Right between degree, oxide layer under described polysilicon thickness and different polysilicon dry etching process threes after the etching
Should be related to, etch process parameters is overlapped in preparation in advance more, thus when new product introduction, according to layout density and the oxygen of etching area
The preset thickness changing layer just can select etch process the most accurately, to facilitate new product volume production quickly.As a non-limit
The example of property processed, the preset thickness that can arrange described oxide layer is that 0.1 nanometer is to 40 nanometers.
But, only by the domain of active area, or only by the domain of floating gate region, to the judgement of actual etching area also
Inaccurate, cause, in further development, etch process conditions to be determined by round-about way, such as, produce few
After volume production product or semi-finished product, obtained the profile of product by SEM, and then it is dry to revise polysilicon according to the measurement data of profile
Etch process parameters, and then again produce with new technological parameter, detection SEM result the most again.
Above-mentioned flow process not only spends higher production cost, and because of the finiteness of SEM number of samples existence, it is difficult to one
The adjustment of technology of product is put in place by secondary property, and after causing new product introduction, the lifting cycle of yield is longer than expection.
Use the embodiment of the present invention, it is possible to obtain the layout density of actual etching area, presetting then in conjunction with oxide layer
Thickness, can select etch process the most accurately, thus accurately control the most advanced and sophisticated pattern of different product flash memory floating gate, high
Realize to effect the smooth importing of new product.
In being embodied as, the etch-rate of described polysilicon dry etching process be 0.1 nm/minute to 1000 nanometers/
Minute, the etch-rate of described oxide layer is that 0.1 nm/minute is to 500 nm/minute.Described polysilicon dry etching process
Etching period is main etching 2 seconds to 100 seconds, overetch (over etch) 0 to 500 second.The erosion of described polysilicon dry etching process
Carving temperature is-80 degrees Celsius to 300 degrees Celsius.The etching gas of described polysilicon dry etching process can be chlorine (Cl2), bromine
Change hydrogen (HBr) etc..The etching pressure of described polysilicon dry etching process is 1mTorr to 5000mTorr.Described polysilicon dry corrosion
The etch voltage of carving technology is 1V to 2000V.The original thickness of described oxide layer is that 2 nanometers are to 50 nanometers.It is pointed out that
The technological parameter of described polysilicon dry etching process is not restricted by the embodiment of the present invention.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Limit in the range of standard.
Claims (7)
1. the system of selection of the polysilicon dry etching process of an embedded flash memory, it is characterised in that comprise the following steps:
The domain of the active area of described embedded flash memory and the domain of floating gate region are provided；
Domain according to described active area and the domain of floating gate region, determine the actual etching region of described active area and described floating gate region
The layout density in territory, described actual etching area is the region by dry etching process etching polysilicon；
Layout density according to described actual reproduction region and the oxide layer that is positioned under described polysilicon presetting after the etching
Thickness, selects corresponding dry etching process.
The system of selection of the polysilicon dry etching process of embedded flash memory the most according to claim 1, it is characterised in that institute
State and determine that described active area includes with the layout density of the actual etching area of described floating gate region:
Domain according to described active area and the domain of floating gate region, determine the overlapping region of described floating gate region and described active area；
Layout density according to described active area and the layout density of described overlapping region determine the version of described actual etching area
Figure density.
The system of selection of the polysilicon dry etching process of embedded flash memory the most according to claim 2, it is characterised in that root
The layout density of described actual etching area is determined according to the layout density of described active area and the layout density of described overlapping region
Including: utilize the layout density of described active area to deduct the layout density of described overlapping region, to obtain described actual etching region
The layout density in territory.
The system of selection of the polysilicon dry etching process of embedded flash memory the most according to claim 2, it is characterised in that institute
The layout density stating overlapping region is multiplied by the first default ratio equal to the layout density of described floating gate region.
The system of selection of the polysilicon dry etching process of embedded flash memory the most according to claim 1, it is characterised in that institute
State and determine that described active area includes with the layout density of the actual etching area of described floating gate region:
Domain according to described active area and the domain of floating gate region, determine the overlapping region of described floating gate region and described active area,
The layout density of described overlapping region is as the first layout density；
Determine the layout density of the actual etching area of described floating gate region, as the second layout density；
Layout density according to described active area, described first layout density and the second layout density, determine described active area with
The layout density of the actual etching area of described floating gate region.
The system of selection of the polysilicon dry etching process of embedded flash memory the most according to claim 5, it is characterised in that root
According to the layout density of described active area, described first layout density and the second layout density, determine that described active area is floating with described
The layout density of the actual etching area in grid region includes: utilize the layout density of described active area to deduct described first layout density
Add described second layout density, to obtain the layout density of described active area and the actual etching area of described floating gate region.
The system of selection of the polysilicon dry etching process of embedded flash memory the most according to claim 5, it is characterised in that institute
The layout density stating the actual etching area determining described floating gate region includes:
The volume of the polysilicon according to etching actual in described floating gate region calculates the etch depth value of described polysilicon；
The volume of described floating gate region under same depth is calculated according to described etch depth value；
Calculate the ratio of the volume of the polysilicon of actual etching and the volume of described floating gate region in described floating gate region；
The layout density utilizing described floating gate region is multiplied by described ratio, to determine the domain of the actual etching area of described floating gate region
Density.
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| CN109616409A (en) * | 2018-12-04 | 2019-04-12 | 武汉新芯集成电路制造有限公司 | A kind of polysilicon deposition method, flash memory and manufacturing method thereof |
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