CN118888435B - Preparation method of floating gate structure, floating gate structure and flash memory device - Google Patents
Preparation method of floating gate structure, floating gate structure and flash memory device Download PDFInfo
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- CN118888435B CN118888435B CN202411365189.4A CN202411365189A CN118888435B CN 118888435 B CN118888435 B CN 118888435B CN 202411365189 A CN202411365189 A CN 202411365189A CN 118888435 B CN118888435 B CN 118888435B
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- 238000007667 floating Methods 0.000 title claims abstract description 87
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 110
- 229920005591 polysilicon Polymers 0.000 claims abstract description 107
- 238000002955 isolation Methods 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 230000005641 tunneling Effects 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000005429 filling process Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000011800 void material Substances 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明提供一种浮栅结构的制备方法、浮栅结构及闪存器件，具体涉及半导体技术领域。所述制备方法包括：提供衬底，所述衬底上形成有至少两个隔离结构，相邻的两个所述隔离结构之间形成上窄下宽的梯形沟槽；在所述梯形沟槽的底部形成隧穿氧化层；在所述梯形沟槽的侧壁上形成多晶硅垫层，以使所述梯形沟槽转变成矩形沟槽；向所述矩形沟槽内填充多晶硅，形成浮栅。该方法可以有效改善浮栅填充过程中的空洞问题，提高器件的可靠性。
The present invention provides a method for preparing a floating gate structure, a floating gate structure and a flash memory device, and specifically relates to the field of semiconductor technology. The preparation method comprises: providing a substrate, on which at least two isolation structures are formed, and a trapezoidal groove with a narrow top and a wide bottom is formed between two adjacent isolation structures; forming a tunneling oxide layer at the bottom of the trapezoidal groove; forming a polysilicon pad layer on the sidewall of the trapezoidal groove to transform the trapezoidal groove into a rectangular groove; and filling the rectangular groove with polysilicon to form a floating gate. The method can effectively improve the void problem in the floating gate filling process and improve the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a floating gate structure, the floating gate structure and a flash memory device.
Background
Flash memory (Flash) is a long-life nonvolatile memory, and is widely used in high-tech industries such as mobile communication, data processing, intelligent terminals, embedded systems, etc., as well as in personal computers and external devices thereof, automotive electronics, network switches, internet devices, instruments, etc., because of its advantages such as high integration level, fast access speed, easy erasing and rewriting.
Floating Gate (FG) is a key structure for storing charges in a flash memory device, and its performance directly affects the data retention capability, read-write speed, and reliability of the device. With the continuous development of integrated circuit manufacturing technology, the size of flash memory is continuously reduced, and the critical dimensions of the floating gate in flash memory are also gradually reduced, which brings challenges to the formation of the floating gate.
At present, in the floating gate forming process, a mask layer needs to be removed to form a gap for filling the floating gate, and a trapezoid gap with a vertical section being narrow at the upper part and wide at the lower part is easy to form after the mask layer is removed, and the opening of the trapezoid gap is smaller, so that a cavity is easy to form in the middle of filling the floating gate due to the higher depth-to-width ratio and the smaller filling opening, and the yield of products is reduced.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention provides a method for manufacturing a floating gate structure, a floating gate structure and a flash memory device, so as to improve the problem of voids during floating gate filling.
To achieve the above and other related objects, the present invention provides a method for manufacturing a floating gate structure, including the steps of:
Providing a substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoid groove with a narrow upper part and a wide lower part is formed between two adjacent isolation structures;
Forming a tunneling oxide layer at the bottom of the trapezoid groove;
forming a polysilicon pad layer on the side wall of the trapezoid groove so as to convert the trapezoid groove into a rectangular groove;
And filling polysilicon into the rectangular groove to form a floating gate.
In an example of the present invention, forming a polysilicon pad layer on a sidewall of the trapezoid trench includes:
Forming a polysilicon layer on the inner wall of the trapezoid groove, wherein the polysilicon layer covers the tunneling oxide layer, the side wall of the trapezoid groove and the isolation structures on two sides of the trapezoid groove;
and removing the polysilicon layer on the isolation structure and the tunneling oxide layer and part of the polysilicon layer on the side wall of the trapezoid groove so as to form a polysilicon cushion layer on the side wall of the trapezoid groove, so that the trapezoid groove forms a rectangular groove.
In an example of the present invention, removing the polysilicon layer on the isolation structure and the tunneling oxide layer and a portion of the polysilicon layer on the sidewall of the trapezoid trench includes:
etching the polysilicon layer by adopting a dry etching process, and removing the polysilicon layer on the isolation structure, the polysilicon layer on the tunneling oxide layer and part of the polysilicon layer on the side wall of the trapezoid groove;
And forming a polysilicon cushion layer by reserving part of the polysilicon layer on the side wall of the trapezoid groove, so that the trapezoid groove forms a rectangular groove.
In an example of the present invention, a side of the polysilicon pad layer attached to the sidewall of the trapezoid trench is inclined, and a side of the polysilicon pad layer facing away from the sidewall of the trapezoid trench is perpendicular to the bottom of the trapezoid trench.
In an example of the present invention, after filling the polysilicon into the rectangular trench, the method further includes using a chemical mechanical planarization process to process the polysilicon to remove the polysilicon on the isolation structure and form a floating gate.
In one example of the present invention, the forming process of at least two isolation structures includes:
forming a pad oxide layer on a substrate;
forming a hard mask layer on the pad oxide layer;
forming a patterned photoresist layer on the hard mask layer, the patterned photoresist layer including at least two openings defining the isolation structures;
Sequentially etching the hard mask layer, the pad oxide layer and the substrate by taking the patterned photoresist layer as a mask to form a shallow trench;
and filling isolation oxide in the shallow trench to form an isolation structure.
In an example of the present invention, after forming the isolation structure, the method further includes a step of removing the patterned photoresist layer, the hard mask layer and the pad oxide layer, and a trapezoid trench with a narrow top and a wide bottom is formed between two adjacent isolation structures.
In an example of the present invention, the tunnel oxide layer includes silicon dioxide, and the method of forming the tunnel oxide layer at the bottom of the trapezoid trench includes a thermal oxidation method.
The invention also provides a floating gate structure, which is prepared by adopting the preparation method, and comprises the following steps:
A substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoid groove with a narrow upper part and a wide lower part is formed between two adjacent isolation structures;
the tunneling oxide layer is formed at the bottom of the trapezoid groove;
the polysilicon cushion layer is formed on the side wall of the trapezoid groove so that the trapezoid groove forms a rectangular groove;
And the floating gate is formed in the rectangular groove.
The invention further provides a flash memory device, which comprises the floating gate structure.
In an example of the present invention, the flash memory device further includes an inter-gate dielectric layer disposed on the floating gate and a control gate disposed on the inter-gate dielectric layer.
According to the preparation method of the floating gate structure, before floating gate filling, the polysilicon cushion layer is formed on the side wall of the trapezoid groove, the polysilicon cushion layer is completely attached to the side wall of the trapezoid groove, the trapezoid groove with the narrow upper part and the wide lower part can be converted into the rectangular groove, the cavitation phenomenon can be effectively improved in the subsequent floating gate filling process, and the reliability of a device is improved. In addition, the polysilicon is adopted as the cushion layer and is the same as the polysilicon floating gate, so that the problem of hollow holes in the floating gate is solved, other impurities can be prevented from being introduced, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a floating gate structure prepared in the prior art;
FIG. 2 is a flow chart of a method for fabricating a floating gate structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a substrate in an embodiment of a method for fabricating a floating gate structure according to the present invention;
FIG. 4 is a schematic diagram illustrating a method for forming shallow trenches in an embodiment of a floating gate structure according to the present invention;
FIG. 5 is a schematic diagram illustrating an isolation structure formed by the method for fabricating a floating gate structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a method for fabricating a floating gate structure according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a method for fabricating a floating gate structure according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a method for fabricating a floating gate structure according to an embodiment of the present invention;
FIG. 9 is an enlarged schematic view of a portion of the area A of FIG. 8;
FIG. 10 is an enlarged partial schematic view of area B of FIG. 8;
FIG. 11 is a schematic diagram of a method for fabricating a floating gate structure according to an embodiment of the present invention for filling floating gate polysilicon;
FIG. 12 is a schematic diagram of a floating gate structure according to an embodiment of the present invention.
Description of element numbers:
100. The semiconductor device comprises a substrate, 110, a pad oxide layer, 120, a hard mask layer, 130, an isolation structure, 131, a shallow trench, 140, a trapezoid trench, 141, a tunneling oxide layer, 142, a polysilicon layer, 143, a polysilicon cushion layer, 144, a rectangular trench, 150 and a floating gate.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
In the present application, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship based on that shown in the drawings, for convenience of description and simplicity of description, only, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
In the prior art, the preparation method of the floating gate comprises the steps of sequentially forming a pad oxide layer and a mask layer on a substrate, etching a groove, filling oxide in the groove to form an isolation structure, and removing the mask layer and the pad oxide layer to form gaps for filling the floating gate between adjacent isolation structures. In the preparation process of the floating gate, a very thick mask layer is usually formed, and a trapezoid isolation groove is easily formed in the etching process of the mask layer, so that a gap for filling the floating gate formed after the mask layer is removed later is also a trapezoid gap with a narrow upper part and a wide lower part, and the trapezoid gap is easy to cause a cavity in the floating gate filling process (see fig. 1), so that the device is opened or even invalid, and the reliability of the device is affected.
Based on the method, the floating gate structure and the flash memory device, the preparation method of the floating gate structure can effectively improve the problem of hollowness in the floating gate filling process by forming the polysilicon liner on the side wall of the trapezoid groove to convert the trapezoid groove into the rectangular groove before filling the floating gate.
Referring to fig. 2 to 12, a first aspect of the present invention provides a method for preparing a floating gate structure, which includes the following steps:
S1, providing a substrate 100, wherein at least two isolation structures 130 are formed on the substrate 100, and a trapezoid groove 140 (see FIG. 5) with a narrow upper part and a wide lower part is formed between two adjacent isolation structures 130;
s2, forming a tunneling oxide layer 141 at the bottom of the trapezoid groove 140 (see FIG. 6);
s3, forming a polysilicon pad layer 143 on the sidewall of the trapezoid trench 140 to convert the trapezoid trench 140 into a rectangular trench 144 (see fig. 8 to 10);
and S4, filling polysilicon into the rectangular grooves 144 to form floating gates 150 (see FIG. 12).
The following describes in detail the steps of the method for manufacturing the floating gate structure according to the embodiment of the present invention with reference to fig. 3 to 12.
Referring to fig. 3, in step S1, the substrate 100 may be selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or other III/V compound semiconductor materials. In addition, the substrate may be a stacked substrate material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI). In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 may form the active region through a doping process, for example, an ion implantation process.
Referring to fig. 3 to 5, the isolation structures 130 formed on the substrate 100 extend downward into the substrate 100 to isolate active regions on the substrate 100, each of which can be used to form a semiconductor device, and the top of the isolation structures 130 is higher than the upper surface of the substrate 100, and the recess regions between two adjacent isolation structures 130 form filling regions of the floating gate 150.
In one embodiment, the isolation structure 130 is a shallow trench isolation structure (Shallow Trench Isolation, STI). The shallow trench isolation structure is formed as follows:
Referring to fig. 3, a pad oxide layer 110 is formed on a substrate 100. Pad oxide 110 includes, but is not limited to, silicon dioxide (SiO 2). The pad oxide layer 110 may be prepared by a process such as thermal oxidation (thermal oxidation method) or chemical vapor deposition (Chemical Vapor Deposition, CVD), for example.
A hard mask layer 120 is formed on the pad oxide layer 110. The hard mask layer 120 is, for example, silicon nitride (Si 3N4), and the hard mask layer 120 may be formed by a chemical vapor deposition physical vapor deposition (Physical Vapor Deposition, PVD) or the like process. The pad oxide layer 110 may serve as a buffer layer to prevent the hard mask layer 120 having a relatively high hardness from directly contacting the substrate 100 to damage the substrate 100, and the hard mask layer 120 may serve as a hard mask to etch and copy a corresponding pattern.
Further, before etching, a patterned photoresist layer (not shown) is formed on the hard mask layer 120, i.e., a photoresist layer is first spin-coated on the hard mask layer 120, and at least two openings are formed on the photoresist layer through exposure and development processes, so as to form a patterned photoresist layer with an etched pattern on the hard mask layer 120. The at least two openings define the locations of the isolation structures 130, and the openings expose the bottom hard mask layer 120.
Referring to fig. 4, the hard mask layer 120, the pad oxide layer 110 and a portion of the substrate 100 are etched in sequence by using the patterned photoresist layer as a mask, so as to form a shallow trench 131, wherein the shallow trench 131 does not penetrate the substrate 100. The etching process may be performed using methods well known to those skilled in the art, such as dry etching and/or wet etching. The shallow trench 131 structure is formed to be gradually narrowed from top to bottom, which is helpful for filling the subsequent insulating material, and also gradually narrows the hard mask layer 120 from bottom to top.
Referring to fig. 5, after the shallow trench 131 is formed, an isolation oxide, such as an insulating material, for example, silicon dioxide, is filled in the shallow trench 131 to form the isolation structure 130. The isolation oxide is filled by, for example, a high aspect Ratio filling Process (HIGH ASPECT Ratio Process, HARP), low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD), or plasma chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD). After the isolation oxide deposition is completed, the isolation oxide is planarized until the isolation oxide is level with the hard mask layer 120. The planarization process uses, for example, a Chemical Mechanical Polishing (CMP) process. After the planarization process is completed, the isolation structure 130 is formed. However, it will be understood by those skilled in the art that the isolation structure 130 of the present invention may be formed by other methods known in the art, and the above-mentioned process of forming the isolation structure 130 is not limited thereto.
After the isolation structure 130 is formed, the process of removing the patterned photoresist layer, the hard mask layer 120 and the pad oxide layer 110 may be further included, wherein the patterned photoresist layer may be removed by a plasma ashing process, and the hard mask layer 120 and the pad oxide layer 110 may be removed by an etching process, for example, a dry etching process and/or a wet etching process. Since the shallow trenches 131 are formed to be gradually narrowed from top to bottom, correspondingly, the hard mask layer 120 between two adjacent isolation structures 130 is gradually narrowed from bottom to top, and the trapezoid trenches 140 are formed to be gradually narrowed from bottom to top after the hard mask layer 120 and the pad oxide layer 110 are removed, that is, the longitudinal section of the formed trenches is trapezoid with narrow top and wide bottom.
Referring to fig. 6 and 12, step S2 is performed to form a tunnel oxide layer 141 at the bottom of the trapezoid trench 140. The tunnel oxide layer 141 serves to isolate the floating gate 150 from the substrate 100, preventing charge from flowing directly from the floating gate 150 to other portions of the transistor. The tunnel oxide layer 141 allows charge to move from one region to another region by quantum tunneling. In the flash memory erasing process, charges stored on the floating gate 150 are tunneled to the source or the body region through the tunneling oxide layer 141, thereby realizing data erasing. The tunnel oxide layer 141 is, for example, silicon dioxide, and the tunnel oxide layer 141 can be formed by thermal oxidation, such as wet oxidation, dry oxidation or in-situ vapor generation, chemical vapor deposition, physical vapor deposition, and the like.
Referring to fig. 6, 8, 10 and 11, since the trench for filling the floating gate 150 formed in step S1 is a trapezoid trench 140 having a longitudinal section that is narrow at the top and wide at the bottom, the trench having such a shape is liable to form a void during the subsequent filling of the floating gate 150 due to the small opening size. In order to improve the void problem during the filling of the floating gate 150, the present invention adds step S3 to form a polysilicon pad layer 143 on the sidewall of the trapezoid trench 140. The polysilicon pad layer 143 is gradually widened from top to bottom, and the polysilicon pad layer 143 is completely attached to the side wall of the trapezoid trench 140, so that the trapezoid trench 140 is converted into a rectangular trench 144 with a rectangular longitudinal section under the assistance of the polysilicon pad layer 143.
Referring to fig. 9, specifically, the side of the polysilicon pad layer 143 attached to the sidewall of the trapezoid trench 140 is inclined, the inclination angle (the angle between the hypotenuse of the polysilicon pad layer 143 and the bottom wall of the trapezoid trench 140) is the same as the inclination angle (the angle between the sidewall and the bottom of the trapezoid trench 140) of the sidewall of the trapezoid trench 140, one side of the polysilicon pad layer 143 away from the sidewall of the trapezoid trench 140 is perpendicular to the bottom of the trapezoid trench 140, and the polysilicon pad layer 143 of the structure is filled in the trapezoid trench 140 to compensate the inclination angle of the sidewall of the trapezoid trench 140, so that the trapezoid trench 140 is converted into the rectangular trench 144. In addition, since the subsequently filled floating gate 150 also adopts polysilicon, no additional impurity is introduced in this step by using polysilicon as a pad layer.
Referring to fig. 7 to 10, in one embodiment, the polysilicon pad layer 143 is formed as follows:
A polysilicon layer 142 is formed on the inner wall of the trapezoid trench 140, and the polysilicon layer 142 covers the tunnel oxide layer 141 at the bottom of the trapezoid trench 140, the sidewall of the trapezoid trench 140, and the isolation structures 130 at both sides of the trapezoid trench 140 (see fig. 7).
Methods of forming the polysilicon layer 142 include, but are not limited to, low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD). The deposition thickness of the polysilicon layer 142 is not particularly limited as long as the trapezoid trench 140 is not filled. Further, the polysilicon layer 142 is deposited to a thickness of at least the dimension of the top of the sidewall of the trapezoid trench 140 beyond the bottom. For example, the polysilicon layer 142 is deposited to a thickness of at least 5nm at the top of the sidewalls of the trapezoid trench 140 beyond the bottom, so that the polysilicon pad layer 143 obtained during the subsequent process completely compensates for the inclined portion of the sidewalls of the trapezoid trench 140. Further, the thickness of the polysilicon layer 142 is less than or equal to half of the size of the top opening of the trapezoid trench 140, since the polysilicon layer 142 is deposited on the sidewalls of the trapezoid trench 140 at the same time, when the thickness of the polysilicon layer 142 is equal to half of the size of the top opening of the trapezoid trench 140, the top opening of the trapezoid trench 140 is filled by adding the thicknesses of the sidewalls of the trapezoid trench 140. Thus, the polysilicon layer 142 is deposited to a thickness less than or equal to half the size of the top opening of the trapezoid trench 140. By way of example, the top opening size of the trapezoid trench 140 is 40nm, and the deposition thickness of the polysilicon layer 142 is 20nm or less.
The polysilicon layer 142 on the isolation structure 130 and the tunnel oxide layer 141 and a portion of the polysilicon layer 142 on the sidewall of the trapezoid trench 140 are removed to form a polysilicon pad layer 143 on the sidewall of the trapezoid trench 140 (see fig. 8 and 9).
Since the polysilicon layer 142 is deposited on all exposed surfaces of the wafer substrate 100, i.e., the tunnel oxide layer 141 at the bottom of the trench 140, the sidewalls of the trapezoid trench 140, and the isolation structures 130 at both sides of the trapezoid trench 140, polysilicon is deposited on all exposed surfaces, and only a portion of the polysilicon on the sidewalls of the trapezoid trench 140 needs to be remained for forming the polysilicon pad 143, the polysilicon layer 142 on the isolation structures 130 and the tunnel oxide layer 141 and a portion of the polysilicon layer 142 on the sidewalls of the trapezoid trench 140 need to be removed. In this embodiment, the process of removing the polysilicon layer 142 uses dry etching, such as plasma etching (PLASMA ETCHING), reactive ion etching (Reactive Ion Etching, RIE), and the like. Since the trapezoid trench 140 has a structure with a narrow top and a wide bottom, the isolation oxide on the sidewall of the trapezoid trench 140 has a certain blocking effect in the etching process, so that the polysilicon layer 142 covered by the sidewall is reserved to form the polysilicon pad layer 143, and the polysilicon layer 142 not covered by the sidewall is etched. After the etching is completed, the trapezoid groove 140 is converted into a rectangular groove 144 with the same upper and lower widths with the aid of the polysilicon pad layer 143.
Referring to fig. 10 to 12, step S4 is performed to fill polysilicon into the rectangular trench 144 to form the floating gate 150.
The filling of the polysilicon in this step may be performed by techniques known in the art, such as Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like. The polysilicon fills the rectangular trenches 144 while covering the isolation structures 130 on both sides of the rectangular trenches 144 to provide a margin for subsequent planarization of the polysilicon. After the polysilicon deposition is completed, the polysilicon is further processed by adopting a chemical mechanical planarization process until the top of the isolation structure 130 is exposed, and the thickness of the remaining polysilicon reaches the requirement of the thickness of the floating gate, so as to form the floating gate 150.
Referring to fig. 12, another aspect of the present invention further provides a floating gate structure, where the floating gate structure is manufactured by using the manufacturing method of the present invention. The floating gate structure includes a substrate 100, a tunnel oxide layer 141, a polysilicon pad layer 143, and a floating gate 150.
The substrate 100 may be selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or other III/V compound semiconductor materials. In addition, the substrate may be a stacked substrate material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI). In this embodiment, the substrate 100 is a silicon substrate.
At least two isolation structures 130 are formed on the substrate 100, and the bottom of the isolation structures 130 extends into the substrate 100, and the top of the isolation structures 130 is higher than the upper surface of the substrate 100. The isolation structure 130 is, for example, a Shallow Trench Isolation (STI) structure. A trapezoid groove 140 with a narrow upper part and a wide lower part is formed between two adjacent isolation structures 130.
The tunnel oxide layer 141 is formed at the bottom of the trapezoid trench 140, and the tunnel oxide layer 141 is, for example, silicon oxide, and its thickness may be designed according to a conventional method in the art.
A polysilicon pad layer 143 is formed on sidewalls of the trapezoid trench 140. Specifically, the polysilicon pad layer 143 is obliquely arranged on one side of the sidewall of the trapezoid groove 140, the inclination angle (the included angle between the hypotenuse of the polysilicon pad layer 143 and the bottom wall of the trapezoid groove 140) is the same as the inclination angle (the included angle between the sidewall and the bottom of the trapezoid groove 140) of the sidewall of the trapezoid groove 140, one side of the polysilicon pad layer 143 away from the sidewall of the trapezoid groove 140 is perpendicular to the bottom of the trapezoid groove 140, and the polysilicon pad layer 143 of the structure is filled in the trapezoid groove 140 to compensate the inclination angle of the lower part of the sidewall of the trapezoid groove 140, so that the trapezoid groove 140 is converted into the rectangular groove 144.
The floating gate 150 is made of polysilicon, and the polysilicon is filled in the rectangular trench 144.
According to the floating gate structure, the polysilicon cushion layer 143 is additionally arranged in the trapezoid groove, so that the trapezoid groove 140 is converted into the rectangular groove 144 under the action of the polysilicon cushion layer 143, the problem of holes in polysilicon of the floating gate 150 can be effectively solved in the subsequent filling process, and the reliability of the floating gate structure is improved.
Based on the same inventive concept, the invention also provides a flash memory device, which comprises the floating gate structure.
In one embodiment, the flash memory device further includes an inter-gate dielectric layer disposed on the floating gate 150 and a control gate disposed on the inter-gate dielectric layer. The inter-gate dielectric layer is used to isolate the floating gate 150 from the control gate, and the material of the inter-gate dielectric layer may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO), and the material of the control gate may be polysilicon.
According to the preparation method of the floating gate structure, before floating gate filling, the polysilicon cushion layer is formed on the side wall of the trapezoid groove, the trapezoid groove with the narrow upper part and the wide lower part is converted into the rectangular groove by utilizing the polysilicon cushion layer, so that the cavitation phenomenon in the floating gate can be effectively improved in the subsequent filling process, and the reliability of a device is improved. Therefore, the invention effectively overcomes some practical problems in the prior art, thereby having high utilization value and use significance.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (7)
1. The preparation method of the floating gate structure is characterized by comprising the following steps of:
Providing a substrate, wherein at least two isolation structures are formed on the substrate, a trapezoid groove with a narrow upper part and a wide lower part is formed between two adjacent isolation structures, and the isolation structures are composed of isolation oxides;
Forming a tunneling oxide layer at the bottom of the trapezoid groove;
forming a polysilicon pad layer on the side wall of the trapezoid groove so as to convert the trapezoid groove into a rectangular groove;
filling polysilicon into the rectangular groove to form a floating gate;
Forming a polysilicon cushion layer on the side wall of the trapezoid groove, wherein the polysilicon cushion layer comprises the following components:
Forming a polysilicon layer on the inner wall of the trapezoid groove, wherein the polysilicon layer covers the tunneling oxide layer, the side wall of the trapezoid groove and the isolation structures on two sides of the trapezoid groove;
removing the polysilicon layer on the isolation structure and the tunneling oxide layer and part of the polysilicon layer on the side wall of the trapezoid groove by adopting dry etching so as to form a polysilicon cushion layer on the side wall of the trapezoid groove, so that the trapezoid groove forms a rectangular groove;
In the etching process, the isolation oxide of the isolation structure has a certain blocking effect, the polysilicon layer below the isolation oxide is reserved to form the polysilicon cushion layer, and the polysilicon layers at the rest positions are etched;
the polycrystalline silicon cushion layer is obliquely arranged on one side, attached to the side wall of the trapezoid groove, of the polycrystalline silicon cushion layer, and one side, away from the side wall of the trapezoid groove, of the polycrystalline silicon cushion layer is perpendicular to the bottom of the trapezoid groove.
2. The method of claim 1, further comprising removing polysilicon on the isolation structure by chemical mechanical planarization after filling polysilicon into the rectangular trench to form a floating gate.
3. The method of claim 1, wherein the forming of the at least two isolation structures comprises:
forming a pad oxide layer on a substrate;
forming a hard mask layer on the pad oxide layer;
forming a patterned photoresist layer on the hard mask layer, the patterned photoresist layer including at least two openings defining the isolation structures;
Sequentially etching the hard mask layer, the pad oxide layer and the substrate by taking the patterned photoresist layer as a mask to form a shallow trench;
and filling isolation oxide in the shallow trench to form an isolation structure.
4. The method of claim 1, wherein the tunnel oxide layer comprises silicon dioxide and the method of forming the tunnel oxide layer at the bottom of the trapezoid trench comprises a thermal oxidation process.
5. The floating gate structure is characterized by being prepared by adopting the preparation method of any one of claims 1 to 4, and comprises the following steps:
A substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoid groove with a narrow upper part and a wide lower part is formed between two adjacent isolation structures;
the tunneling oxide layer is formed at the bottom of the trapezoid groove;
the polysilicon cushion layer is formed on the side wall of the trapezoid groove so that the trapezoid groove forms a rectangular groove;
And the floating gate is formed in the rectangular groove.
6. A flash memory device comprising the floating gate structure of claim 5.
7. The flash memory device of claim 6, further comprising an inter-gate dielectric layer disposed on the floating gate and a control gate disposed on the inter-gate dielectric layer.
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