CN110600371A - Polycrystalline silicon filling method, semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

The invention provides a polysilicon filling method, a semiconductor device manufacturing method and a semiconductor device. The polysilicon deposition and polysilicon etching are performed in the same process chamber, which can avoid natural occurrence of polysilicon in the process of transferring from the etching process chamber to the deposition process chamber. Oxidation, thereby avoiding the problem that the natural oxide layer causes the delamination of polysilicon deposited twice in the trench; polysilicon deposition and polysilicon etching are performed in the same process chamber, and it can also avoid the transfer from the deposition process chamber to the etching process chamber. The polysilicon undergoes natural oxidation in the process of annealing, thereby avoiding the problem of poor etching caused by the natural oxide layer. And the use of fluorine-containing gas to etch polysilicon can make the product after etching polysilicon gas, avoid unnecessary etching by-products from accumulating in the trench and affect the effect of subsequent processes such as the next polysilicon deposition, and avoid two times before and after. Delamination problems occur in the deposited polysilicon.

Description

Polysilicon filling method, semiconductor device manufacturing method, and semiconductor device

technical field

The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for filling polysilicon, a method for manufacturing a semiconductor device, and a semiconductor device.

Background technique

Shielded gate trench (SGT) power field effect transistor (MOSFET) device is the most advanced power MOSFET device technology, which can achieve low on-resistance (Rdson) and low gate-to-drain capacitance (Cgd) at the same time, thereby At the same time, the conduction loss and switching loss of the system are reduced, and the use efficiency of the system is improved.

Referring to FIG. 1 , the cell structure of a shielded gate trench power MOSFET device includes: a substrate 100 having a gate trench 104 , a source region 102 formed on the top layer of the substrate 100 on both sides of the gate trench 104 , a source region 102 formed on the source In the well region 101 in the substrate 100 under the region 102, the gate trench 104 has an oxide layer 105 on the sidewall and bottom wall, and the gate trench 104 is filled with shielding polysilicon (ie, shielding electrode) 106 and gate polysilicon 107 , there is also an oxide layer 105 between the shielding polysilicon 106 and the gate polysilicon 107, and the surface of the source region 102 and the gate polysilicon 107 is covered with an interlayer dielectric layer 103, and the interlayer dielectric layer 103 can be formed with the source region 102 or Contact plugs (not shown) to which gate polysilicon 107 is electrically contacted.

In the existing shielded gate trench power MOSFET device, the shielding polysilicon 106 and the gate polysilicon 107 need to be separated by an oxide layer 105. During the manufacturing process, the shielding polysilicon layer needs to be deposited in the gate trench 104, and then the The masking polysilicon layer is etched to a suitable depth to form the masking polysilicon 106, and then the oxide layer 105 between the masking polysilicon 106 and the gate polysilicon 107 is formed, after which the gate polysilicon layer is again deposited and subjected to chemical mechanical planarization (CMP). ) and other processes to remove the excess gate polysilicon layer on the surface of the substrate 100 to form the gate polysilicon 107 . In this way, it is required that, before etching the shielding polysilicon layer, the shielding polysilicon layer filled in the gate trench 104 is not filled with gaps (or, in other words, voids), because the gaps, on the one hand, will affect the morphology of the subsequently formed shielding polysilicon 106 . and shielding performance, which affects the production yield and reliability of the device. On the other hand, when the oxide layer 105 between the shielding polysilicon 106 and the gate polysilicon 107 is subsequently formed, the oxidation on the sidewalls of the gate trench 104 will be squeezed due to oxidation. layer 105, resulting in poor device reliability.

However, when the conventional polysilicon filling process is used to achieve the purpose that the shielding polysilicon layer filled in the gate trench 104 does not fill the gap, it is required that the sidewall of the gate trench 104 be inclined to the outside, that is, the gate The pole trench 104 has a structure with a wide upper portion and a narrow lower portion, and the sidewall of the gate trench 104 has an inclination angle of θ<90°. However, this solution to avoid filling voids will lead to the problem that a single gate trench 104 occupies more chip area, and when the required gate trench 104 is relatively deep, the side of the gate trench 104 will also be affected. The wall is too sloping to cause the problem of tipping of the shielding polysilicon 106 at the bottom of the gate trench 104, which in turn leads to the problem of lower gate-to-source withstand voltage Vgs and the problem of excessive leakage current caused by the accumulated charges at the tip.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for filling polysilicon, a method for fabricating a semiconductor device, and a semiconductor device without increasing the size of the trench and avoiding the defect of filling the gap in the trench.

In order to achieve the above purpose, the present invention provides a polysilicon filling method, comprising:

Step S11, providing a substrate on which trenches are formed;

Step S12, depositing polysilicon in the trench, and the deposited polysilicon closes the top opening of the trench;

Step S13, using etching gas to etch the polysilicon to open the filling gap in the trench;

Step S14, depositing polysilicon in the trench again;

Wherein, the steps S12 to S14 are performed in the same process chamber.

Optionally, in the step S14, after the polysilicon is deposited again, the steps S13 and S12 are performed cyclically until the filling gap of the polysilicon in the trench is eliminated and the trench is filled with polysilicon.

Optionally, according to the aspect ratio of the groove in the step S11, the number of cycles in the step S14 is preset.

Optionally, the etching gas includes at least one of ClF ₃ , SF ₆ , NF ₆ , SF ₄ , C _x F _y and C _m H _n Fi , wherein x, y, m, n, _i Both are integers not less than 1.

Optionally, in the step S11, the trench is a trench with a narrow upper portion and a wide lower portion or a vertical trench with sidewalls perpendicular to the surface of the substrate.

Optionally, the new trench formed when the filling gap in the trench is opened is a U-shaped trench or a V-shaped trench or a trench whose top opening area is smaller than the bottom wall area.

Optionally, after the step S11 is performed and before the step S12 is performed for the first time, a shielding medium layer is also formed on the inner surface of the trench.

Optionally, after step S14, the method further includes: planarizing the top of the polysilicon to form a gate, and/or etching back the polysilicon to a certain depth in the trench to form a shield gate.

Based on the same inventive concept, the present invention also provides a method for fabricating a semiconductor device, comprising: using the polysilicon filling method of the present invention to fill a corresponding trench of a substrate with polysilicon.

Optionally, the trenches in the substrate include a first type trench and a second type trench; the polysilicon filled at the bottom of the first type trench using the polysilicon filling method is located in the first type trench. A shielding gate at the bottom of the trench-like trench, the top of the first-type trench is also filled with a control gate, and an insulating dielectric layer is sandwiched between the control gate and the shielding gate; the polysilicon filling method is used in the first The polysilicon filled in the trenches of the second type is connection polysilicon. The bottom of the connection polysilicon in the trenches of the second type is flush with the bottom of the shield gate at the bottom of the trenches of the first type. The top of the connecting polysilicon is flush with the top of the control gate in the first type of trenches.

Optionally, the manufacturing method of the semiconductor device further includes:

performing trap ion implantation on the substrate around the trench to form a well region on top of the substrate;

performing source ion implantation on the well region around the trench to form a source region on the surface of the well region;

forming an interlayer dielectric layer covering the trench region and the surface of the source region;

forming a contact plug through the interlayer dielectric layer, the bottom of the contact plug being in electrical contact with the polysilicon or the source region; and,

Drain ion implantation is performed on the surface of the substrate facing away from the contact plug to form a drain region.

Based on the same inventive concept, the present invention also provides a semiconductor device, which is fabricated by using the semiconductor device fabrication method of the present invention, the semiconductor device comprising: a substrate having a trench in the substrate; and polysilicon, filled with in the groove.

Optionally, the semiconductor device is a shielded gate trench power MOSFET device, the polysilicon is filled at the bottom of the trench and serves as a shielded gate, and the semiconductor device further includes:

a control gate, filled on the top of the trench;

an insulating dielectric layer, located between the shielding gate and the control gate and surrounding the sidewall of the control gate;

a shielding dielectric layer surrounding the sidewalls and bottom walls of the shielding grid;

a source region formed in the surface layer of the substrate on both sides of the trench; and,

A drain region is formed on the surface of the substrate facing away from the source region.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

1. Polysilicon deposition and polysilicon etching are performed in the same process chamber, which can avoid the natural oxidation of polysilicon during the transfer from the etching process chamber to the deposition process chamber, thereby preventing the natural oxide layer from causing two depositions in the trench. The problem of polysilicon delamination; polysilicon deposition and polysilicon etching are performed in the same process chamber, which can also avoid the natural oxidation of polysilicon during the process of transferring from the deposition process chamber to the etching process chamber, thereby avoiding the natural oxidation layer. Poor etching problem.

2. Using fluorine-containing gas to etch polysilicon can make the products after etching polysilicon all gas, avoid unnecessary etching by-products from accumulating in the trenches and affect the effect of subsequent processes such as the next polysilicon deposition, and avoid before and after The double-deposited polysilicon suffers from delamination problems.

3. By cyclically performing polysilicon etching and polysilicon deposition, the size of the polysilicon gap filled in the trench is gradually reduced and the position is raised until the polysilicon filling gap in the trench is eliminated.

4. The number of times of polysilicon etching and polysilicon deposition is pre-set according to the aspect ratio of the trench, which can avoid the need to check whether the deposited polysilicon has a gap filling operation after each deposition, and can ensure the final filling in the trench. The polysilicon in the groove can not only fill the groove, but also no longer have the problem of filling the gap.

5. The trenches are allowed to be narrow at the top and wide at the bottom or vertical grooves with sidewalls perpendicular to the surface of the substrate, thereby avoiding the single trench occupying more space caused by the trenches with the width at the top and the narrow at the bottom. The chip area and the polysilicon filled at the bottom of the trench have the problem of the tip, which is beneficial to the further scaling of the device and avoids the problem of excessive leakage current caused by the electric charge accumulated at the tip.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a typical structure of a cell structure of a shielded gate trench power MOSFET device.

FIG. 2 is a flowchart of a method for filling polysilicon according to a specific embodiment of the present invention.

3A to 3G are schematic diagrams of cross-sectional structures of a device in a method for filling polysilicon according to an embodiment of the present invention.

FIG. 4 is a flowchart of a method for fabricating a semiconductor device according to a specific embodiment of the present invention.

FIG. 5 is a schematic diagram of a device cross-sectional structure of a semiconductor device according to a specific embodiment of the present invention.

Detailed ways

In order to make the objectives, advantages and features of the present invention clearer, the technical solutions proposed by the present invention will be described in further detail below with reference to the accompanying drawings. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Referring to FIG. 2, an embodiment of the present invention provides a polysilicon filling method, including:

Step S11, providing a substrate on which trenches are formed;

Step S12, depositing polysilicon in the trench, and the deposited polysilicon closes the top opening of the trench;

Step S13, using etching gas to etch the polysilicon to open the filling gap in the trench;

Step S14, depositing polysilicon in the trench again;

Wherein, the steps S12 to S14 are performed in the same process chamber.

Referring to FIG. 3A , in step S11 , a substrate 300 is provided, and a trench 302 is formed on the substrate 300 . The trench 302 is a trench whose top opening area is smaller than the bottom wall area or whose sidewalls are perpendicular to the bottom wall. The vertical trenches on the surface of the substrate 300 are described above, but the solution of the present invention is not limited to the trenches of the above two shapes, but is applicable to any trenches with gap filling problems. The specific process of step S11 includes: first, a substrate 300 is provided, and the substrate can be any suitable substrate known to those skilled in the art, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator substrate , a germanium-on-insulator substrate; then, a hard mask layer 301 is formed on the surface of the substrate 300, and the hard mask layer 301 is etched by photolithography combined with dry etching to pattern the hard mask The mold layer 301 is used to form a pattern for defining the formation region of the trench 302 in the hard mask layer 301, and the material of the hard mask layer 301 may include at least one of silicon oxide, silicon nitride and silicon oxynitride, It can be a single-layer structure or a stacked-layer structure; then, using the patterned hard mask layer 301 as a mask, anisotropic etching is performed on the substrate 300 to form trenches 302, The depth of the etch (ie, the etch stop) depends on the depth requirements of the trenches 302 . The formed trench 302 is a trench whose top opening area is smaller than the bottom wall area, or a vertical trench (such as a U-shaped trench) whose sidewalls are perpendicular to the surface of the substrate, whereby the trench 302 can be avoided The problem that the trench 302 takes up too much chip area due to the sidewalls sloping outwards. When the required trenches 302 are relatively deep, the sidewalls of the trenches 302 will not be too inclined to cause subsequent filling in the trenches. The polysilicon at the bottom of 302 has a tipping problem.

It should be noted that, in other embodiments of the present invention, the specific shape of the groove 302 may be a regular shape or an irregular shape. Polysilicon filling method. In addition, the irregular-shaped trench 302 may be a trench with uneven sidewalls. In addition, the hard mask layer 301 can be left until the polysilicon is filled to protect the substrate around the trenches 302 . In addition, only one trench 302 is shown in FIG. 3A , but the technical solution of the present invention is not limited to this. In other embodiments of the present invention, two or more trenches may be formed at the same time according to the needs of the device. The grooves 302, and the widths of the grooves 302 can be the same or different, the depths of the grooves 302 can be the same or different, and the intervals between the grooves 302 can be the same or different.

In other embodiments of the present invention, the substrate 300 may include a base (not shown) and a semiconductor epitaxial layer on the base, and the trench 302 may be completely formed in the semiconductor epitaxial layer, thereby being defined by the thickness of the semiconductor epitaxial layer Depth of trench 302 .

Please continue to refer to FIG. 3A , after step S11 is performed, when the insulating isolation between the polysilicon to be subsequently filled and the substrate 300 is required, a thermal oxidation process or a chemical vapor deposition process, etc. A shielding dielectric layer 303 is formed thereon, and the material of the shielding dielectric layer 303 can include at least one of silicon oxide, silicon nitride and silicon oxynitride, and the shielding dielectric layer 303 can be a single-layer structure or a laminated structure. , such as ONO stack structure (ie, silicon oxide-silicon nitride-silicon oxide stack structure).

Referring to FIG. 3B, in step S12, the substrate on which the shielding dielectric layer 303 and the trench 302 are formed can be placed into the corresponding process chamber of the furnace tube equipment, silane or chlorosilane is used as the reactive gas source, and Polysilicon 304a is further deposited using a low pressure chemical vapor deposition (LP_CVD) process. The reduction of the process technology node leads to further shrinking of the device size, which in turn leads to the fact that the aspect ratio of the trench 302 is generally larger. Sealing, and then burying the trench 302, so far, the deposited polysilicon 304a not only fills the trench 302, but also covers the surface of the hard mask layer 301 around the trench 302, and the deposited polysilicon 304a fills the trench 304a. The top opening of 302 is closed. The larger depth-to-width ratio of the trench 302 will cause the polysilicon 304a filled in the trench 302 to be sealed earlier, thereby forming a filling gap 305a inside the trench 302. At this time, the height of the filling gap 305a is relatively low, for example, the gap bottom is far from the lining The height of the bottom surface of the bottom 300 is h1.

It should be noted that, when doped polysilicon needs to be formed in the trench 302, in step S12, doping and implantation of polysilicon may be performed along with the low pressure chemical vapor deposition reaction, for example, it needs to be filled with P-type doped polysilicon When using boron ethane as a doping gas source, on the one hand, boron is doped into polysilicon, and on the other hand, boron ethane is used as a catalyst to greatly improve the deposition rate of polysilicon; for example, N-type doping needs to be deposited. When producing polysilicon, phosphine can be used as a doping gas source. On the one hand, phosphorus is added to the polysilicon, and on the other hand, phosphine is used as a catalyst to greatly improve the deposition rate of polysilicon.

Referring to FIGS. 3B and 3C , usually after the polysilicon 304a is deposited for the first time, there must be a filling gap 305a in the trench 302. Therefore, in step S13, first, continue to maintain the process used in step S12 for the device filled with polysilicon 304a. Then, the etching gas containing fluorine is changed to etch the polysilicon 304a, so as to open the filling gap 305a in the trench 302, thereby forming a new trench 302a. The fluorine-containing etching gas includes at least one of ClF ₃ , SF ₆ , NF ₆ , SF ₄ , C _x F _y and C _m H _n Fi , wherein x, y, m, n, and _i are all is an integer not less than 1, for example, when x=1, F=4, C _x F _y is CF ₄ (carbon tetrafluoride), and when x=4, F=8, C _x F _y is C ₄ F ₈ (octafluorocyclobutane), another example when m=1, n=1, F=3, C _m H _n F _i is CHF ₃ (trifluoromethane). The advantage of using fluorine-containing etching gas to etch polysilicon 304a is that in the presence of fluorine, the strong chemical properties of fluorine make the products after etching polysilicon all gas, thus avoiding the generation of etching deposits In this way, unnecessary etching by-products are prevented from accumulating in the trenches to affect the effect of subsequent processes such as the next polysilicon deposition, and the problem of delamination of polysilicon deposited twice before and after is avoided. In this embodiment, the etching gas is ClF ₃ . Step S13 and step S12 are performed in the same process chamber, which can avoid the problem that the device is brought out of the furnace tube process chamber after step S13 and cause the natural oxidation of polysilicon, thereby preventing the natural oxide layer from causing two times in the trench. The problem of delamination of the deposited polysilicon can prevent the device from being taken out of the furnace tube process chamber after step S12 and cause natural oxidation, thereby preventing the natural oxide layer grown on the polysilicon surface after depositing polysilicon from hindering the process in step S13. The problem of etching effect.

It should be noted that, in step S13, the degree of etching polysilicon depends on the degree of opening of the filling gap. Generally, it is necessary to ensure that there is a certain thickness of polysilicon 304a around the filling gap and the top opening of the filling gap is wide enough to allow subsequent deposition. Polysilicon can be filled in, and the aspect ratio of the new trench 302a formed can be much smaller than the aspect ratio of the trench 302. Therefore, the technical solution of the present invention is effective for the new trench 302 formed when the filling gap 305a is opened. The shape and depth of the groove 302a are not specifically limited. For example, the new groove 302a can be a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove with a wide upper and a narrow lower, or even an open top. A groove with an area smaller than the area of the bottom wall. The height h2 of the bottom of the new trench 302a relative to the bottom surface of the substrate 300 may be equal to the height h1 of the filling gap 305a, or slightly smaller than h1, thereby reducing the number of subsequent deposition and etching cycles and improving production efficiency.

Referring to FIGS. 3B to 3E, in step S14, polysilicon can be redeposited into the new trench 302a using the same process parameters as in step S12, and the redeposited polysilicon closes the top opening of the new trench 302a, and then according to Steps S13 and S12 need to be executed in a loop, and the number of loop executions depends on the aspect ratio of the trench 302. Specifically, the size and height of the filling gap 305a and the depth of the trench 302 can be determined through historical data on the production line. width ratio relationship, and then preset the specific number of times of loop execution according to this relationship, so that the corresponding times of loop execution can be directly executed in step S14 to ensure that the polysilicon filled in the final trench can fill the trench and the filled polysilicon There is no filling gap in the middle, and at the same time, the operation of transferring the device for filling gap inspection after each polysilicon deposition can be avoided. In step S14, with the progress of the cycle, the filling gap after step S12 is executed the next time will be smaller in size and the position will be higher than the filling gap after step S12 is executed in the previous time, as shown in FIG. 3B and FIG. The filling gap 305b formed in the trench with the polysilicon 304b filled after step S12 is performed for the second time, compared with the filling gap 305a formed in the trench with the polysilicon 304a filled after step S12 is performed for the first time shown in FIG. 3B, the width, The volumes are much smaller, and the height h3 of the filled gap 305b (ie, the vertical distance from the bottom of the filled gap 305b to the bottom surface of the substrate 300 ) is greater than the height h1 of the filled gap 305a. As shown in FIG. 3E , after step S12 is performed for the last time, the filled polysilicon 304c fills the trench 302 and no gap is left within the effective height of the trench 301 (ie, in the height area below the top surface of the hard mask layer 301 ). . Therefore, after going through the number of cycles of step S14, the filling gap of polysilicon in the trench 302 is eliminated, wherein the meaning of eliminating the filling gap is that no filling gap exceeding the specification can be detected, or in other words, all the filling gaps filled in the trench 302 are eliminated. Even if there is still a filling gap in the polysilicon, the size of the filling gap is very small and the position is high, which will not affect the effect of the subsequent process and meet the requirements of device fabrication.

It should be noted that, in step S14, the meaning of cyclically executing steps S13 and S12 is: after the polysilicon is deposited for the second time, step S13 and step S12 are sequentially executed at least once as required, and step S12 is taken as the final end of the entire cycle process. Therefore, after step S13 is performed for the last time, the trench 302 can be filled with polysilicon once again, thereby ensuring that the final filled polysilicon can fill the trench 302 and eliminating the filling gap of the polysilicon filled in the trench 302 .

In addition, in other embodiments of the present invention, when the aspect ratio of the trench 302 is small, after the redeposition of polysilicon (ie, the second deposition of polysilicon into the trench 302 ) is completed in step S14 , the trench has been eliminated If the polysilicon in 302 fills the gap, it is unnecessary to perform the subsequent cycle process of step S13 and step S12. That is to say, in this embodiment, only two polysilicon deposition operations need to be performed and a polysilicon etching operation is sandwiched between the two polysilicon deposition operations, so that the polysilicon filling gap in the trench 302 can be eliminated And the trench 302 is filled with polysilicon.

In one embodiment of the present invention, after step S14, please refer to FIG. 3E, the top of the polysilicon 304c deposited for the last time can be planarized to form the gate 304, and the top of the polysilicon 304c can be planarized to a hard mask The upper surface or the lower surface of the mold layer 301 .

In another embodiment of the present invention, please refer to FIGS. 3F and 3G, after step S14, all the filled polysilicon (including polysilicon 304a-304c) can be etched back to a certain depth in the trench 302 to form The shielding gate 304', in this process, the selected etching gas has a reduced etching selectivity ratio to the polysilicon and the shielding dielectric layer, thereby simultaneously removing the polysilicon 304c on the upper surface of the hard mask layer 301 and the top of the shielding gate 304' The shielding dielectric layer 303 is formed to expose the sidewall of the trench 302 above the shielding gate 304'; in other embodiments, the filled polysilicon is etched back to form the shielding gate 304', and then the shielding dielectric exposed on the sidewall is removed by etching Layer 303. In addition, when a shielded gate trench power MOSFET device needs to be formed, after the shielded gate 304' is formed, an insulating dielectric layer 306 may be further formed in the trench 302 on the surface of the shielded gate 304' and the trench on the sidewalls of the trench 302 exposed by the shield gate 304 ′, and refill polysilicon or gate metal in the trench 302 , and the refilled polysilicon or gate metal fills the trench to The control gate 307 is formed. At this time, the insulating dielectric layer 306 sandwiched between the control gate 307 and the shielding gate 304' is used to insulate the control gate 307 and the shielding gate 304', and the insulating dielectric layer 306 on the sidewall of the control gate 307 is used for As the gate dielectric layer, the insulating dielectric layer 306 sandwiched between the control gate 307 and the shielding gate 304 ′ and the insulating dielectric layer 306 sandwiched between the sidewall of the control gate 307 and the substrate 300 can be formed using the same film forming process It can also be produced separately by using two different film layer processes. When polysilicon is refilled in the trench area above the shielding gate 304' to form the control gate 307, if the aspect ratio of the trench area above the shielding gate 304' is large and the problem of polysilicon filling is likely to occur, this method can be used again. The inventive polysilicon filling method is used to form the control gate 307 to ensure the electrical performance of the formed control gate 307. If the depth and width of the trench 302 above the shielding gate 304' is relatively small and it is not easy to fill the gap, conventional polysilicon can be used. A filling method is used to form the control gate 307 to simplify the process.

To sum up, in the polysilicon filling method of this embodiment, at least two polysilicon depositions and one polysilicon etching are performed in the same process chamber (that is, polysilicon deposition and polysilicon etching are performed alternately), thereby eliminating the polysilicon filled in the trenches. fill gaps, thereby avoiding trench fill gap defects without increasing the trench size. The polysilicon filling method of this embodiment is applicable to any semiconductor device that needs to fill the trenches with polysilicon and the fabrication method thereof. Taking the fabrication of a shielded gate trench power MOSFET device as an example, the following describes in detail the application of the polysilicon filling method of this embodiment to a semiconductor device and a fabrication method thereof with reference to FIGS. 2 to 5 .

Referring to FIG. 4 , the present embodiment provides a method for fabricating a semiconductor device, including:

S21, using the polysilicon filling method of this embodiment (ie, steps S11 to S14), filling polysilicon in the corresponding trenches of a substrate;

S22, performing well ion implantation on the substrate around the trench to form a well region on top of the substrate;

S23, performing source ion implantation on the well region around the trench to form a source region on the surface of the well region;

S24, forming an interlayer dielectric layer, the interlayer dielectric layer covering the trench region and the surface of the source region;

S25, forming a contact plug passing through the interlayer dielectric layer, and the bottom of the contact plug is in electrical contact with the polysilicon or the source region; and,

S26, performing drain ion implantation on the surface of the substrate facing away from the contact plug to form a drain region.

Please refer to FIG. 2 to FIG. 5 , the specific process of step S21 includes:

First, step S11 is performed, a substrate 300 is provided, and two or more trenches 302 are formed in the substrate 300. The depth and width of the trenches 302 can be set to be the same according to the requirements of the device, or can be set according to the requirements of the device. The settings are not exactly the same. In this embodiment, please refer to FIG. 5 , the formed trenches may include a first-type trench M1 and a second-type trench M2, and the first-type trench M1 is subsequently used to fill the shield gate (polysilicon material) and The control gate (which can be made of polysilicon and/or gate metal material), an insulating dielectric layer is sandwiched between the control gate and the shield gate in the first type trench M1, and the second type trench M2 is used in the subsequent For filling polysilicon to form connection polysilicon, and the bottom of the connection polysilicon in the second type trench M2 is flush with the bottom of the shield gate at the bottom of the first type trench M1, the second type trench M2 The top of the connecting polysilicon in the first type trench M1 is flush with the top of the control gate. In step S11, a thermal oxidation process or a chemical vapor deposition process or the like is further used to form a shielding dielectric layer 303 on the sidewalls and bottom walls of each of the first-type trenches M1 and the second-type trenches M2. The material of the shielding dielectric layer 303 may include at least one of silicon oxide, silicon nitride and silicon oxynitride, and the shielding dielectric layer 303 may be a single-layer structure or a laminated structure, such as an ONO laminated structure ( That is, silicon oxide-silicon nitride-silicon oxide stack structure). It should be noted that the number of the first type of trenches M1 and the second type of trenches M2 depends on the device manufacturing requirements. Generally, the number of the first type of trenches M1 is greater than that of the second type of trenches M2. The technical solution of the present invention is this There is no specific limitation.

Then, steps S12-S14 are performed to fill the first-type trench M1 and the second-type trench M2 with polysilicon 304. The specific process can refer to the description of steps S12-S14 above, which will not be repeated here. The polysilicon formed after step S14 may be further ground by chemical mechanical planarization (CMP), so as to provide a flat process surface and reduce the thickness of the polysilicon etched back later. At this time, the polysilicon 304 filled in the trench M2 of the second type serves as a connecting polysilicon that is electrically connected to the source region formed subsequently through structures such as contact plugs.

Next, by forming a patterned photoresist on the substrate 300 and the polysilicon 304, the region of the first type trench M1 can be exposed, and other regions including the second type trench M2 region can be masked, and then etched back. The polysilicon 304 (including the polysilicon 304a-304c in FIG. 3E) filled in the first type trench M1 is etched to a predetermined depth in the first type trench M1, so as to form a desired height in the first type trench M1. Shield grid 304'.

Then, an insulating dielectric layer 306 is formed on the surface of the first type trench M1 above the shielding gate 304'. In this embodiment, an insulating dielectric layer 306 is formed by a thermal oxidation method or a chemical vapor deposition process, and the insulating dielectric layer 306 covers The upper surface of the shielding gate 304' and the sidewall of the first type trench M1 above the shielding gate 304' are made of an oxide layer, and the insulating dielectric layer 306 is located between the shielding gate 304' and the subsequently filled control gate ( The gate interlayer insulating layer) is used to insulate the shielding gate 304' and the subsequently filled control gate, and the part of the insulating dielectric layer 306 on the sidewall of the trench above the shielding gate 304' serves as the gap between the subsequently filled control gate and the substrate. between the gate oxide layers. In other embodiments of the present invention, different processes may also be used to form the gate interlayer dielectric layer between the shielding gate 304' and the subsequently filled control gate and the gate dielectric layer on the sidewall of the control gate. Specifically, First, silicon oxide is deposited by chemical vapor deposition to fill the first type trench M1 and cover the surface of other areas, and then run the CMP process to smooth the silicon oxide to the upper surface of the hard mask layer 301 above the substrate 300 , and then perform photolithography and dry etching of silicon oxide to a target depth to form a gate interlayer dielectric layer, and then use thermal oxidation to grow gates on the sidewalls of the first type trench M1 above the gate interlayer dielectric layer The oxide layer is used as a gate dielectric layer. At this time, the insulating dielectric layer 306 includes a gate interlayer dielectric layer on the upper surface of the shielding gate 304' and a gate oxide layer on the sidewall of the first type trench M1 above the shielding gate 304'. This process is relatively complicated, but the gate interlayer dielectric layer between the shielding gate 304' and the control gate 307 and the gate oxide layer between the control gate 307 and the substrate 300 can be separately formed, so that the shielding gate 304' can be formed. The thickness of the insulating material between the control gate 307 and the control gate 307 is evenly adjustable and has good consistency, so that the thickness of the gate oxide layer between the control gate 307 and the substrate 300 is uniform and has good consistency, so that the shielding gate 304 ′ and the substrate 300 can have a uniform thickness. The capacitance structure composed of the control gate 307 and the interlayer dielectric layer between them is stable and controllable, and the reliability of the gate oxide layer between the control gate 307 and the substrate 300 is guaranteed, and the gate-source leakage of the device is reduced.

After that, the control gate 307 can be filled in the first type trench M1 by selecting the traditional polysilicon filling method or the metal gate filling method or the polysilicon filling method of this embodiment as required. The specific process is not repeated here.

Finally, the hard mask layer and the like are removed to expose the upper surface of the control gate 307 in the second type trench M2 and the upper surface of the surrounding substrate 300 .

Referring to FIG. 5, in step S22, well ion implantation is performed to form a well region 308 on the surface layer of the substrate 300 around the first type trench M1 and the second type trench M2. A masking structure such as photoresist (ie, a patterned mask layer) masks and protects the regions of each of the first-type trenches M1 and the second-type trenches M2.

Referring to FIG. 5 , in step S23 , source ion implantation is performed by means of heavy doping, and a source region 309 is formed on the surface of the well region 308 . Heavy doping means that the concentration of source ion implantation is greater than that of trap ion implantation. Further, the well region 308 and the source region 309 may be thermally annealed to eliminate ion implantation defects and activate the implanted ions. In addition, it should be noted that, in this embodiment, when the source ion implantation is performed into the well region 308, the surface of the well region 308 between two adjacent trenches can be all formed as the source region 309, but this The technical solution of the invention is not limited to this. In other embodiments of the present invention, a photolithography process can be used to define the surface of a part of the well region 308 as the source region 309, and a blocking photoresist (not shown) can be produced for protection. The first-type trench M1 and the second-type trench M2 regions and other surfaces of the well region 308 are then subjected to source ion implantation to form a source region 309 in a portion of the well region 308 .

Referring to FIG. 5 , in step S24 , an interlayer dielectric layer may be formed on the surface of the source region 309 and the regions of the first type trenches M1 and the second type trenches M2 by coating, chemical vapor deposition, etc. 310. The material of the interlayer dielectric layer 310 may include at least one of silicon oxide, silicon nitride, and a low dielectric constant dielectric (the dielectric constant is less than 3.9), and may be a single-layer structure or a stacked-layer structure.

Please refer to FIG. 5 , in step S25 , a contact hole (not shown) passing through the interlayer dielectric layer 310 is formed by a process of photolithography combined with etching, and a process such as vacuum evaporation, sputtering or electroplating is performed. , and the contact holes are filled with metal to form contact plugs 311 . Further, a metal layer is covered on the surfaces of the interlayer dielectric layer 310 and the contact plug 311, and photolithography and etching are performed on the metal layer to form a source metal layer 312b and a gate metal layer 312a. The layer 312b is electrically connected to the source region 309 and the connecting polysilicon in the second type trench M2 through corresponding contact plugs 311 to draw the source region 309 outward, and the gate metal layer 312a is connected to the source region 309 through corresponding contact plugs. The plug 311 is electrically connected to the control gate 307 in the first-type trench M1 to lead the control gate 307 in the first-type trench M1 to the outside.

Referring to FIG. 5, in step S26, the backside of the substrate 300 is thinned, and drain ion implantation is performed on the backside of the thinned substrate 300 to form a heavily doped drain region 313, and further Ground, a drain metal layer (not shown) for pulling out the drain region 313 is formed on the backside of the drain region 313 .

It should be noted that, in this embodiment, when the semiconductor device to be fabricated is an N-type shielded gate trench MOSFET device, the conductivity type of the substrate 300 is N-type, the conductivity type of the well region 308 is P-type, and the source region 309 and the conductivity type of the drain region 313 is N-type; when the semiconductor device to be fabricated is a P-type shielded gate trench MOSFET device, the conductivity type of the substrate 300 is P-type, the conductivity type of the well region 308 is N-type, and the source region The conductivity type of 309 and drain region 313 is P-type.

Referring to FIG. 5 , this embodiment further provides a semiconductor device fabricated by using the semiconductor device fabrication method of this embodiment, the semiconductor device includes: a substrate 300 having trenches (M1 and/or M2); polysilicon 304' (and/or 304), filled in the trench; source region 309, formed in the surface layer of the substrate 300 on both sides of the trench; and, drain region 313, formed in the liner The backside of base 300 (ie, the surface of substrate 300 facing away from source region 309).

Specifically, the semiconductor device is a shielded gate trench power MOSFET device, and the trench includes a first type of trench M1 and a second type of trench M2. The bottom-filled polysilicon gate of the first-type trench M1 is used as a shield gate 304', the top of the first-type trench M1 is filled with a control gate 307, and the control gate in the first-type trench M1 An insulating dielectric layer 306 is sandwiched between 307 and the shielding gate 304 ′, the insulating dielectric layer 306 surrounds the sidewall of the control gate 307 , and between the shielding gate 304 ′ of the first type trench M1 and the substrate 300 A shielding dielectric layer 303 is also sandwiched, and the shielding dielectric layer 303 surrounds the sidewalls and the bottom wall of the shielding grid 304'. The connection polysilicon 304 of polysilicon material is filled in the second type trench M2, and the bottom of the connection polysilicon 304 in the second type trench M2 and the bottom of the shield gate 304' at the bottom of the first type trench M1 Flush, the top of the connection polysilicon 304 in the second type trench M2 is flush with the top of the control gate 307 in the first type trench M1, and a shield is also formed in the second type trench M2 A dielectric layer 303, the shielding dielectric layer 303 in the second type trench M2 surrounds the sidewalls and bottom walls of the connection polysilicon 304, and is used to isolate the connection polysilicon 304 and the connection polysilicon 304 in the second type trench M2. the substrate 300.

The semiconductor device further includes an interlayer dielectric layer 310, the interlayer dielectric layer 310 is formed on the surface of the source region 309 and each of the trenches M1, M2, and the interlayer dielectric layer 310 is formed through the interlayer dielectric layer. Contact plug 311 of 310 . A source metal layer 312b and a gate metal layer 312a are also formed on the surfaces of the interlayer dielectric layer 310 and the contact plugs 311. The source metal layer 312b passes through the corresponding contact plugs 311 and the source regions 309, second The connection polysilicon 304 in the trench-like M2 is electrically connected to lead the source region 309 outward, and the gate metal layer 312a is electrically connected through the corresponding contact plug 311 and the control gate 307 in the trench M1 of the first type. connected to lead out the control gate 307 in the first type trench M1.

It should be noted that two adjacent first type trenches M1 are used to form two shielded gate trench power MOSFETs, and the device distance L between the two adjacent shielded gate trench power MOSFETs, the first type trenches The depth D1 at which the bottom wall of the trench M1 protrudes into the substrate 300, the depth D3 of the upper surface of the shield gate 304' in the first type trench M1 in the substrate 300, the control gate 307 in the first type trench M1 The key dimension parameters such as the depth D2 of the bottom of the contact plug 311 in the substrate 300 and the depth D4 of the bottom of the contact plug 311 protruding into the substrate 300 all depend on the device performance requirements.

To sum up, in the semiconductor device of the present invention and the manufacturing method thereof, since the corresponding polysilicon gate is formed by the polysilicon filling method of the present invention, it is possible to avoid filling gaps in the process of forming the polysilicon gate, thereby making the semiconductor device provided by the present invention possible. Compared with the prior art, the device has higher yield and better electrical performance. And the trenches allowed to be formed are trenches with upper narrow and lower width or vertical trenches whose sidewalls are perpendicular to the surface of the substrate, thereby avoiding that a single trench caused by the upper wide and lower narrow trenches occupies more. The chip area and the polysilicon filled at the bottom of the trench have the problem of tip, which is conducive to further scaling of the device and avoids the problem of excessive leakage current caused by the electric charge accumulated at the tip.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (13)

1. a polysilicon filling method, is characterized in that, comprises: Step S11, providing a substrate on which trenches are formed; Step S12, depositing polysilicon in the trench, and the deposited polysilicon closes the top opening of the trench; Step S13, using etching gas to etch the polysilicon to open the filling gap in the trench; Step S14, depositing polysilicon in the trench again; Wherein, the steps S12 to S14 are performed in the same process chamber. 2 . The polysilicon filling method according to claim 1 , wherein in the step S14 , after the polysilicon is deposited again, the steps S13 and S12 are performed cyclically until the filling gap of the polysilicon in the trench is eliminated and all the polysilicon is filled. 3 . The trenches are filled with polysilicon. 3 . The polysilicon filling method of claim 2 , wherein the number of cycles in the step S14 is preset according to the aspect ratio of the trench in the step S11 . 4 . 4. The polysilicon filling method according to claim 1, wherein the etching gas _comprises at least one of _ClF3 , _SF6 , _NF6 , _{SF4 , CxFy and CmHnFi} , where x, y, m, n, and i are all integers not less than 1. 5 . The polysilicon filling method according to claim 1 , wherein, in the step S11 , the trench is a trench with a narrow top and a wide bottom or a vertical with sidewalls perpendicular to the surface of the substrate. 6 . Straight groove. 6 . The polysilicon filling method according to claim 1 , wherein in the step S12 , the new trench formed when the filling gap in the trench is opened is a U-shaped trench or a V-shaped trench or a top. 7 . A groove with an opening area smaller than the bottom wall area. 7 . The polysilicon filling method according to claim 1 , wherein after the step S11 is performed and before the step S12 is performed for the first time, the method is still in the trench. 8 . A shielding dielectric layer is formed on the surface. 8 . The method for filling polysilicon according to claim 1 , wherein after step S14 , the method further comprises: planarizing the top of the polysilicon to form a gate, and/or back The polysilicon is etched to a certain depth in the trench to form a shield gate. 9 . A method for manufacturing a semiconductor device, comprising: using the polysilicon filling method according to any one of claims 1 to 8 to fill a corresponding trench of a substrate with polysilicon. 10 . 10. The method for fabricating a semiconductor device according to claim 9, wherein the trenches in the substrate comprise first-type trenches and second-type trenches; The bottom-filled polysilicon of a type of trench is a shield gate located at the bottom of the first type of trench, the top of the first type of trench is also filled with a control gate, and the control gate and the shield gate are sandwiched between There is an insulating dielectric layer; the polysilicon filled in the second type trench by the polysilicon filling method is a connection polysilicon, and the bottom of the connection polysilicon in the second type trench and the bottom of the first type trench are The bottoms of the shield gates are flush, and the tops of the connection polysilicon in the trenches of the second type are flush with the tops of the control gates in the trenches of the first type. 11. The method for fabricating a semiconductor device according to claim 9, further comprising: performing trap ion implantation on the substrate around the trench to form a well region on top of the substrate; performing source ion implantation on the well region around the trench to form a source region on the surface of the well region; forming an interlayer dielectric layer covering the trench region and the surface of the source region; forming a contact plug through the interlayer dielectric layer, the bottom of the contact plug being in electrical contact with the polysilicon or the source region; and, Drain ion implantation is performed on the surface of the substrate facing away from the contact plug to form a drain region. 12 . A semiconductor device, characterized in that it is fabricated by the method for fabricating a semiconductor device according to any one of claims 9 to 11 , the semiconductor device comprising: a substrate having a trench in the substrate; and , polysilicon, filled in the trenches. 13. The semiconductor device of claim 12, wherein the semiconductor device is a shielded gate trench power MOSFET device, the polysilicon is filled at the bottom of the trench and serves as a shielded gate, and the semiconductor device is further include: a control gate, filled on the top of the trench; an insulating dielectric layer, located between the shielding gate and the control gate and surrounding the sidewall of the control gate; a shielding dielectric layer surrounding the sidewalls and bottom walls of the shielding grid; a source region formed in the surface layer of the substrate on both sides of the trench; and, A drain region is formed on the surface of the substrate facing away from the source region.