CN103855017B - The method forming groove type double-layer grid MOS structure two-layer polysilicon lateral isolation - Google Patents

Abstract

The invention discloses a method for forming lateral isolation of two layers of polysilicon in a trench-type double-layer gate MOS structure, comprising: 1) growing a first nitride film; 2) trench etching; 3) growing a dielectric layer; 4) growing The first layer of polysilicon; 5) The first step of reverse etching of the first layer of polysilicon; 6) The photolithography of the first layer of polysilicon and the second step of reverse etching, and removal of the trench sidewall dielectric layer above the first layer of polysilicon; 7 ) Depositing the second nitride film and etching to expose the first layer of polysilicon; 8) Growing a thermal oxide layer; 9) Removing the second nitride film on the side wall of the trench and the first and second nitride films on the surface of the silicon substrate ; 10) Growth of gate oxide layer; 11) Deposition of the second layer of polysilicon, etching; 12) Polysilicon photolithography; 13) Formation of base and source; 14) Formation of isolation dielectric layer; 15) Formation of contact holes, metal , Passivation layer. The working area of the invention is expanded, the process cost and control difficulty are reduced, and the working performance of the device is improved.

Description

Method for forming lateral isolation of two layers of polysilicon in trench-type double-layer gate MOS structure

technical field

The invention relates to a method for lateral isolation of polysilicon in a trench type metal oxide semiconductor field effect transistor (Trench MOSFET), in particular to a method for forming lateral isolation of two layers of polysilicon in a trench type double-layer gate MOS structure.

Background technique

Among power devices, trench double-layer gate power MOS devices have the characteristics of high breakdown voltage, low on-resistance, high conversion efficiency and fast switching speed. Usually, the source polysilicon (the first layer of polysilicon) electrode is used as a shielding electrode to short-circuit the source or lead out separately, and the second layer of polysilicon electrode is used as the gate. Thus within one trench there will be regions where the source polysilicon terminal region is in lateral contact with the gate polysilicon. The thickness of the oxide layer between the two layers of polysilicon electrodes needs to be strictly controlled, otherwise leakage or lower breakdown voltage will result.

The process of the current HDP-grown dielectric layer between double-layer gates is as follows:

1) Groove corrosion;

2) Dielectric layer deposition;

3) Source polysilicon (first polysilicon) gate deposition;

4) The first step of reverse etching of the source polysilicon (first polysilicon) gate;

5) Source polysilicon (first layer polysilicon) gate photolithography, source polysilicon (first layer polysilicon) gate second-step reverse etching;

6) High-density plasma (HDP) oxide film deposition;

7) HDP CMP (chemical mechanical polishing) to the remaining 3000 Angstroms;

8) After P-Cover (POLY COVER) photolithography, wet etching forms a double-layer polysilicon lateral isolation region, and at the same time, a 2500 angstrom HDP oxide film remains on the first layer of polysilicon in the trench of the cell (MOSFET original cell);

9) Growth of gate oxide layer, deposition of the second layer of polysilicon, reverse etching of the second layer of polysilicon;

10) Growth of dielectric layer under metal;

11) Contact hole dielectric layer etching, contact hole silicon etching;

12) Source metal growth and etching.

Among them, the cross-sectional diagram of the cell (the original cell of MOSFET) after the two-step reverse etching of the first layer of polysilicon in the existing process is shown in Figure 1; after the two-step reverse etching of the first layer of polysilicon, the first layer of polysilicon is drawn out The cross-sectional schematic diagram of the area and the cell area along the trench direction is shown in Figure 2; the cross-sectional schematic diagram of the cell area after the growth of the HDP oxide film is shown in Figure 3; The cross-sectional schematic diagram of the groove direction is shown in Figure 4; the cross-sectional schematic diagram of the cell area after the wet etching of the HDP oxide film is shown in Figure 5; The cross-sectional schematic diagram of the groove direction is shown in Figure 6.

The above process method uses the HDP (High Density Plasma) oxide film grown after the source polysilicon (the first layer of polysilicon) is etched back, and adds a layer of photolithography to cover part of the oxide film laterally during HDP wet etching. Without being etched, an HDP oxide film of about 20,000 angstroms is left on the lead-out edge of the source polysilicon as a lateral isolation dielectric layer between two layers of polysilicon. But this method has the following problems:

First of all, it completely relies on the HDP process, which cannot be realized in the process of the dielectric layer between the double-layer gates grown by the improved thermal oxygen method;

Secondly, in the existing double-layer gate power MOS devices, due to the fluctuation of HDP oxide film etching rate and the isotropic characteristics of wet etching, the length of the lateral isolation region needs to be very large (wet vertical etching requires about 12000 Angstroms, so generally leave a distance of about 20,000 Angstroms in the lateral direction), so as to ensure that there will be no lateral penetration between the two layers of polysilicon, which greatly reduces the area of the working area and affects device parameters.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for forming lateral isolation of two layers of polysilicon in a trench-type double-layer gate MOS structure. By using the method, the problem of lateral isolation of two layers of polysilicon in a thermal oxide dielectric layer double-layer gate process can be solved.

In order to solve the above-mentioned technical problems, the method for forming the lateral isolation of two layers of polysilicon in a trench-type double-layer gate MOS structure of the present invention comprises the steps of:

1) On the silicon substrate, grow the first nitride film as a protective layer;

2) On the silicon substrate, perform Trench (trench) etching;

3) Growth medium layer in the trench;

4) On the dielectric layer, grow the first layer of polysilicon (source polysilicon);

5) Perform the first step of reverse etching on the first layer of polysilicon;

6) Perform photolithography and the second step of reverse etching on the first layer of polysilicon, and remove the trench sidewall dielectric layer above the first layer of polysilicon;

7) After depositing the second nitride film on the bottom and side walls of the trench and the surface of the silicon substrate, etch and remove the second nitride film at the bottom of the trench to expose the first layer of polysilicon;

8) On the first layer of polysilicon, grow a thermal oxide layer;

9) removing the second nitride film on the side wall of the trench and the first and second nitride films on the surface of the silicon substrate;

10) Growth of gate oxide layer;

11) Deposit the second layer of polysilicon (gate polysilicon) in the trench and etch to the silicon surface;

12) Polysilicon (Poly Cover layer) photolithography, defining the area of the isolation dielectric layer to be filled near the second layer of polysilicon near the end of the thermal oxide layer, and etching away all the second layer of polysilicon in this area to form an isolation dielectric to be filled layer area;

13) Form the base (BODY) and source (Source);

14) While coating borophosphosilicate glass, borophosphosilicate glass will also naturally flow into the area to be filled with the isolation dielectric layer, thereby forming a lateral isolation dielectric layer;

15) Form contact holes, metal, and passivation layers.

In the step 1), the method for growing the first nitride film includes: low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition; the material of the first nitride film includes: silicon nitride; the thickness of the first nitride film It is 500-3000 Angstroms.

In the step 3), the dielectric layer is an oxide film, including: silicon oxide, with a thickness of 500-3000 angstroms; the growth method of the dielectric layer includes: thermal oxygen or low pressure chemical vapor deposition.

In the step 4), the method for growing the first layer of polysilicon includes: low pressure chemical vapor deposition; the thickness of the first layer of polysilicon is sufficient to fill the inside of the trench.

In the step 5), in the first step of reverse etching, until the silicon surface is etched.

In the step 6) of performing photolithography on the first layer of polysilicon and the second step of reverse etching, photoetching is performed on the first layer of polysilicon to protect the position where the source polysilicon needs to be connected, and the remaining position of the first layer of polysilicon The second step of polysilicon back etching is carried out until the desired depth below the silicon surface is etched.

In the step 7), the second nitride film deposition method includes: low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; the material of the second nitride film includes: silicon nitride; the second nitride film The thickness is 500-3000 Angstroms; the etching method is dry etching.

In the step 8), the method of growing the thermal oxide layer is by thermal oxygen growth; wherein, the process temperature in the thermal oxygen mode is higher than 950° C.; the thickness of the thermal oxide layer is 500-3000 angstroms.

In the step 9), the removal method includes: wet etching.

In the step 12), the width of the region to be filled with the isolation dielectric layer is 1000-10000 angstroms.

In the step 14), the thickness of the borophosphosilicate glass is 5000-10000 angstroms. In this step, the filled borophosphosilicate glass must not only fill up the area to be filled, but also have a certain thickness on the surface to serve as an isolation dielectric layer for CT.

The present invention proposes a method for the process of the dielectric layer between double-layer gates grown by the current improved thermal oxygen method. After the gate polysilicon electrode is etched to the silicon surface, an additional layer of photolithography is added to define the source polysilicon lead-out A region of a specific length on the edge of the terminal region is completely etched away by dry method to remove the gate polysilicon in this region. This area is subsequently filled with an ILD layer of borophosphosilicate glass before contact hole etching. Using borophosphosilicate glass as the isolation medium, the lateral isolation of two layers of polysilicon is realized in the double-layer gate process of thermal oxygen dielectric layer.

Since the present invention uses borophosphosilicate glass as the isolation medium, it is applied to the thermal oxygen dielectric layer double-layer gate process to realize the lateral isolation of two layers of polysilicon. Compared with the HDP oxide film dielectric layer double-layer gate process, not only the HDP oxide film is omitted Deposition, chemical mechanical polishing and other processes, the working area has also been greatly expanded, and on the basis of reducing process costs and control difficulties, it also effectively improves the performance of the device.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

Figure 1 is a schematic cross-sectional view of the cell (the original cell of the MOSFET) after the two-step reverse etching of the first layer of polysilicon in the existing process;

2 is a schematic cross-sectional view of the lead-out region and the cell region of the first layer of polysilicon along the direction of the trench after two-step reverse etching of the first layer of polysilicon in the prior art;

Fig. 3 is a schematic cross-sectional view of the cell area after the growth of the HDP oxide film in the prior art;

Fig. 4 is a schematic cross-sectional view of the lead-out region of the first layer of polysilicon and the cell region along the direction of the trench after the growth of the HDP oxide film in the prior art;

Fig. 5 is a schematic cross-sectional view of the cell area after wet etching of the HDP oxide film in the existing process;

6 is a schematic cross-sectional view of the lead-out region of the first layer of polysilicon and the cell region along the direction of the trench after wet etching of the HDP oxide film in the prior art;

Fig. 7 is a cross-sectional view of a cell region in which a nitride layer is grown as a barrier layer before trench etching in the present invention;

Fig. 8 is a cross-sectional view of the cell area after two-step reverse etching of the first layer of polysilicon and removal of the sidewall oxide layer of the present invention;

9 is a schematic cross-sectional view of the lead-out region and the cell region of the first layer of polysilicon along the trench direction after the first step of reverse etching and removal of the sidewall oxide layer of the first layer of polysilicon according to the present invention;

Fig. 10 is a sectional view of the cell area after growing a layer of nitride film in the present invention;

Fig. 11 is a cross-sectional view of the cell region where the sidewall nitride film protection layer is formed by etching in the present invention;

Fig. 12 is a cross-sectional view of the cell region after growing a thermal oxygen dielectric layer on the first layer of polysilicon in the present invention;

13 is a cross-sectional view of the cell region after removing the trench sidewall and the nitride film on the surface of the silicon substrate according to the present invention.

14 is a schematic cross-sectional view of the cell region after the growth of the thermal oxide layer and the gate oxide layer of the present invention;

15 is a schematic cross-sectional view of the lead-out region of the first layer of polysilicon and the cell region along the direction of the trench after the thermal oxide layer and the gate oxide layer of the present invention are grown;

16 is a schematic cross-sectional view of the cell region after the second polysilicon growth of the present invention;

17 is a schematic cross-sectional view of the lead-out region and the cell region of the first layer of polysilicon along the trench direction after the second polysilicon growth of the present invention;

Fig. 18 is the Poly Cover layer photolithography of the present invention defines the area to be filled with the isolation dielectric layer located at the second layer of polysilicon near the end of the thermal oxide layer, the first layer of polysilicon lead-out area and the first layer of polysilicon that are all etched in the gate polysilicon in this area Schematic cross-sectional view of the cell region along the direction of the trench;

Fig. 19 is a schematic cross-sectional view of the lead-out region and the cell region of the first layer of polysilicon after being filled with borophosphosilicate glass according to the present invention along the trench direction.

The reference signs in the figure are explained as follows:

1 is the silicon substrate, 2 is the trench, 3 is the first nitride film, 4 is the dielectric layer, 5 is the first polysilicon layer, 6 is the second nitride film, 7 is the thermal oxide layer, and 8 is the gate oxide layer , 9 is the second layer of polysilicon.

detailed description

The method for forming the lateral isolation of two layers of polysilicon in a trench-type double-layer gate MOS structure of the present invention has the following steps:

1) On the silicon substrate 1, grow a first nitride film (such as silicon nitride) 2 with a thickness of 500-3000 angstroms by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition (as shown in FIG. 7 ) ;

The first nitride film 2 in this step can be used as a protective layer on the top of the trench in subsequent processes;

2) Etching the groove 2 on the silicon substrate 1;

3) On the sidewall and bottom of the trench 2, grow a dielectric layer (such as silicon oxide) 4 with a thickness of 500-3000 angstroms by means of thermal oxygen or low-pressure chemical vapor deposition;

4) On the dielectric layer 4, a first layer of polysilicon 5 (source polysilicon) is grown by low-pressure chemical vapor deposition, and the thickness of the first layer of polysilicon 5 is sufficient to fill the inside of the trench;

5) Perform the first step of reverse etching on the first layer of polysilicon 5 until it is etched to the silicon surface;

6) Perform photolithography and second step reverse etching on the first layer of polysilicon 5, and remove the trench sidewall dielectric layer 4 above the first layer of polysilicon 5 by wet etching (as shown in Figure 8-9) ;

Among them, the first layer of polysilicon 5 is photolithographically protected to protect the position where the source polysilicon needs to be connected, and the remaining first layer of polysilicon 5 is subjected to the second step of polysilicon reverse etching until the desired depth below the silicon surface is etched. (specific depth).

7) By low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, deposit a second film with a thickness of 500 to 3000 angstroms on the bottom and side walls of the trench 2 and the surface of the silicon substrate 1 (the surface of the first nitride film 3 ). After the nitride film (such as silicon nitride) 6 (as shown in FIG. 10 ), the second nitride film 6 at the bottom of the trench 2 is removed by dry etching, exposing the first layer of polysilicon 5 (as shown in FIG. 11 );

8) On the first layer of polysilicon 5, grow a thermal oxide layer (such as silicon oxide) 7 with a thickness of 500-3000 angstroms by means of thermal oxygen (temperature higher than 950°C) (as shown in Figure 12);

9) Wet etching, removing the second nitride film 6 on the side wall of the trench, as well as the first nitride film 3 and the second nitride film 6 on the surface of the silicon substrate 1, leaving the first nitride film at the bottom of the trench 2 Thermal oxide layer 7 existing on layer polysilicon 5 (as shown in FIG. 13 );

10) According to the existing process, use thermal oxidation to grow gate oxide layer 8 (as shown in Figure 14-15);

11) Deposit the second layer of polysilicon (gate polysilicon) 9 in the trench 2 according to the existing process (such as low-pressure chemical vapor deposition), and etch to the silicon surface (as shown in Figure 16-17);

12) Polysilicon (Poly Cover layer) photolithography, defining the region of the isolation dielectric layer to be filled at the second layer of polysilicon near the end of the thermal oxide layer, and etching away all the second layer of polysilicon in this area to form isolation to be filled Dielectric layer area, that is to define a specific length area (such as 1000-10000 Angstroms) at the second layer of polysilicon next to the lead-out end of the first layer of polysilicon, and etch away all the second layer of polysilicon in this area to form a Fill the isolation dielectric layer area (as shown in Figure 18);

13) According to the existing process, form the base (BODY) and source (Source) by ion implantation;

14) While coating borophosphosilicate glass, borophosphosilicate glass will also naturally flow into the area to be filled with the isolation dielectric layer, thereby forming a lateral isolation dielectric layer, that is, borophosphosilicate glass with a thickness of 5000-10000 angstroms. As the isolation dielectric layer of the contact hole, in the area to be filled with the isolation dielectric layer formed in step 12), the thickness of the borophosphosilicate glass is sufficient to fill the area, forming the isolation dielectric (ILD) layer of the contact hole and also forming a double-layer The lateral isolation region of polysilicon (as shown in Figure 19);

15) According to the existing process, form the contact hole, metal and passivation layer, that is, use a mask plate to etch to form a contact hole, deposit a metal layer and etch to form a contact electrode, and deposit and etch to form a passivation layer.

In the present invention, after the second layer of polysilicon deposition and reverse etching, the Poly Cover layer is photolithographically defined to define a specific length area next to the lead-out end of the source polysilicon, and all the gate polysilicon in this area is etched, and then the subsequent contact hole process is used The pre-coated borophosphosilicate glass fills the area defined by the Poly Cover layer to form lateral isolation, that is, the present invention keeps a groove etched out until the contact hole is formed, and fills it with the borophosphosilicate glass of the ILD layer. Thus, a lateral isolation region between the lead-out end of the source polysilicon and the gate polysilicon is formed, and at the same time, the follow-up is the same as the existing process.

According to the above method, the working area of the present invention is greatly expanded, the process cost and control difficulty can be reduced, and the working performance of the device can be improved.

Claims (11)

1. the method forming groove type double-layer grid MOS structure two-layer polysilicon lateral isolation, it is characterised in that include step:

1) on a silicon substrate, growth is as the first nitride film of protective layer；

2) on a silicon substrate, etching groove is carried out；

3) somatomedin layer in groove；

4) on dielectric layer, ground floor polysilicon is grown；

5) ground floor polysilicon is carried out the first step and anti-carve erosion, until being etched to silicon face；

6) ground floor polysilicon is carried out photoetching and second step anti-carves erosion, and remove the trenched side-wall medium above ground floor polysilicon Layer；

Wherein, ground floor polysilicon is carried out photoetching, protect the position needing to pick out source polysilicon, surplus Remaining ground floor polysilicon position carries out second step polysilicon and anti-carves erosion, until it is required to be etched to below silicon face The degree of depth；

7) after the bottom of groove and sidewall and silicon substrate deposit the second nitride film, etching removes the second nitrogen of channel bottom Change film, expose ground floor polysilicon；

8) on ground floor polysilicon, thermal oxide layer is grown；

9) the second nitride film and first and second nitride film of silicon substrate of trenched side-wall are removed；

10) gate oxidation layer growth；

11) in groove, deposit second layer polysilicon, and be etched to silicon face；

12) polysilicon photoetching, definition spacer medium layer region to be filled at the second layer polysilicon of thermal oxide layer end, and Second layer polysilicon in this region is all etched away, forms spacer medium floor district to be filled；

13) base stage and source electrode are formed；

14) while being coated with boron-phosphorosilicate glass, in spacer medium floor district to be filled, boron-phosphorosilicate glass can flow into, and forms isolation Dielectric layer；

15) contact hole, metal, passivation layer are formed.

2. the method for claim 1, it is characterised in that: described step 1) in, grow the method bag of the first nitride film Include: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition；The material of the first nitride film includes: silicon nitride； The thickness of the first nitride film is 500～3000 angstroms.

3. the method for claim 1, it is characterised in that: described step 3) in, dielectric layer is oxide-film, including: Silicon oxide, thickness is 500～3000 angstroms；The growth pattern of dielectric layer includes: hot oxygen or low-pressure chemical vapor deposition mode.

4. the method for claim 1, it is characterised in that: described step 4) in, the method for growth ground floor polysilicon Including: low-pressure chemical vapor deposition；The thickness of ground floor polysilicon is for being enough to fill up trench interiors.

5. the method for claim 1, it is characterised in that: described step 5) in, when the first step anti-carves erosion, until carving Erosion is to silicon face.

6. the method for claim 1, it is characterised in that: described step 6) ground floor polysilicon is carried out photoetching and Second step anti-carves in erosion, and ground floor polysilicon is carried out photoetching, protects the position needing to pick out source polysilicon, and remaining One layer of polysilicon position carries out second step polysilicon and anti-carves erosion, until being etched to the following desired depth of silicon face.

7. the method for claim 1, it is characterised in that: described step 7) in, the method bag of the second nitride film deposit Include: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition；The material of the second nitride film includes: silicon nitride； The thickness of the second nitride film is 500～3000 angstroms；The method of etching is dry etching.

8. the method for claim 1, it is characterised in that: described step 8) in, the method for growth thermal oxide layer is logical Overheated oxygen mode grows；Wherein, the technological temperature in hot oxygen mode is higher than 950 DEG C；The thickness of thermal oxide layer is 500～3000 Angstrom.

9. the method for claim 1, it is characterised in that: described step 9) in, the mode of removal includes: wet method is carved Erosion.

10. the method for claim 1, it is characterised in that: described step 12) in, spacer medium layer region to be filled Width be 1000～10000 angstroms.

11. the method for claim 1, it is characterised in that: described step 14) in, the thickness of boron-phosphorosilicate glass be 5000～ 10000 angstroms.