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CN108364870B - Fabrication method of shielded gate trench MOSFET with improved gate oxide quality - Google Patents

Fabrication method of shielded gate trench MOSFET with improved gate oxide quality Download PDF

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CN108364870B
CN108364870B CN201810062556.1A CN201810062556A CN108364870B CN 108364870 B CN108364870 B CN 108364870B CN 201810062556 A CN201810062556 A CN 201810062556A CN 108364870 B CN108364870 B CN 108364870B
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oxide layer
polysilicon
gate
deep
etching
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CN108364870A (en
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周宏伟
杨乐
刘挺
岳玲
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Longteng Semiconductor Co.,Ltd.
Xi'an Longxiang Semiconductor Co.,Ltd.
Xusi semiconductor (Shanghai) Co.,Ltd.
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Longteng Semiconductor Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers

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Abstract

The invention relates to a method for manufacturing a shielded gate trench MOSFET (metal-oxide-semiconductor field effect transistor) for improving the quality of a gate oxide layer. The invention adjusts the thickness and the shape of the oxide layer between the grid and the source by the special condition of the anisotropic deposition of the one-time energy oxide layer and the high-density plasma chemical vapor deposition, can form the high-quality oxide layer between the grid and the source, can be realized by the traditional semiconductor manufacturing process, improves the quality of the oxide layer between the polycrystalline silicon of the source and the polycrystalline silicon of the grid under the condition of not increasing the process difficulty, optimizes the parameters of products, improves the yield and the reliability, and finally achieves the aim of reducing the chip cost.

Description

Manufacturing method of shielded gate trench MOSFET (Metal-oxide-semiconductor field Effect transistor) for improving quality of gate oxide layer
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a method for manufacturing a shielded gate trench MOSFET (metal oxide semiconductor field effect transistor) capable of improving the quality of a gate oxide layer.
Background
For a traditional power MOSFET device, a certain compromise relationship (Ron ^ BV 2.5) exists between the on-resistance (Ron) of the device and the source-drain breakdown voltage, and the development of the power MOSFET device is limited for a long time. The shielded gate trench MOSFET utilizes a charge balance principle to enable the N-type drift region to realize higher breakdown voltage of the device even under the condition of higher doping concentration, thereby obtaining low on-resistance and breaking the silicon limit of the traditional power MOSFET. As shown in fig. 21, the quality of the oxide layer formed by the common process flow of highly doped polysilicon is not high, and the thickness of the oxide layer between the gate and source polarities is not uniform, which brings great risk to the parameters and reliability of the device.
Disclosure of Invention
The invention aims to provide a method for manufacturing a shielded gate trench MOSFET (metal-oxide-semiconductor field effect transistor) capable of improving the quality of a gate oxide layer, which can be realized by using a traditional semiconductor manufacturing process on the premise of basically unchanging the process cost, and can generate a gate source oxide layer with adjustable thickness and better quality on the premise of not increasing the process difficulty.
The technical scheme adopted by the invention is as follows:
the manufacturing method of the shielding grid groove MOSFET for improving the quality of the grid oxidation layer is characterized in that:
filling and back-etching polysilicon in the deep grooves to enable mutual charge balance of the two deep grooves to complete a super junction function, depositing an oxide layer above the deep grooves to thicken an oxide layer between a grid electrode and a source electrode, and finally forming a shielded grid groove device through grid thermal oxidation and polysilicon deposition.
The method comprises the following steps:
the method comprises the following steps: providing an n-type heavily doped n + substrate, and forming an n-type epitaxial layer on the n + substrate;
step two: forming a thick oxide layer on the surface of the epitaxial layer to form a hard mask;
step three: forming a deep groove of an active area and a deep groove of a terminal area by photoetching and dry etching, wherein the deep groove of the terminal area surrounds the deep groove of the active area, and finally removing the thick oxide layer;
step four: growing field oxide layers on the bottom and the side wall of the deep groove by utilizing a wet thermal oxidation process;
step five: carrying out first polysilicon deposition by utilizing a polysilicon deposition process;
step six: carrying out polysilicon back etching by a dry etching process to obtain a shallow trench above the active region deep trench, wherein the first polysilicon and the field oxide layer in the terminal region deep trench are not back etched under the protection of the photoresist;
step seven: removing the field oxide layer by photoetching and wet etching;
step eight: continuously etching the polysilicon in the groove by using an etching process;
step nine: adjusting the thickness and the shape of the oxide layer between the grid and the source by utilizing special conditions of anisotropic deposition of the oxide layer, namely high-density plasma chemical vapor deposition (HDP CVD);
step ten: removing the residual field oxide layer on the side wall by utilizing a wet etching process;
step eleven: forming a gate oxide layer by dry oxidation;
step twelve: depositing polysilicon for the second time, and back-etching the polysilicon for the second time by a dry method to form a grid electrode of the shallow trench MOSFET device;
step thirteen: removing the surface oxide layer before well injection;
fourteen steps: injecting P-BODY to form a P well;
step fifteen: manufacturing a device active region by implantation;
sixthly, the steps are as follows: depositing a dielectric layer, and etching a contact hole;
seventeen steps: etching and injecting the contact hole to form ohmic contact;
eighteen steps: completing a surface metal structure;
nineteen steps: and thinning the back and finishing the back metal structure.
The manufacturing method can be used for manufacturing the shielded gate trench MOSFET structure with improved gate oxide quality.
The invention has the following advantages:
the invention can form a high-quality oxide layer between the grid and the source by adjusting the thickness and the shape of the oxide layer between the grid and the source through the special condition high-density plasma chemical vapor deposition (HDP CVD) of the anisotropic deposition of the one-time oxide layer, can be realized by using the traditional semiconductor manufacturing process, improves the quality of the oxide layer between the polycrystalline silicon of the source and the polycrystalline silicon of the grid under the condition of not increasing the process difficulty, optimizes the parameters of the product, improves the yield and the reliability, and finally achieves the aim of reducing the chip cost.
Drawings
FIG. 1 is a schematic diagram of a first step of the present invention;
FIG. 2 is a schematic view of step two of the present invention;
FIG. 3 is a schematic view of step three of the present invention;
FIG. 4 is a schematic view of step four of the present invention;
FIG. 5 is a schematic view of step five of the present invention;
FIG. 6 is a schematic representation of step six of the present invention;
FIG. 7 is a schematic view of step seven of the present invention;
FIG. 8 is a schematic representation of step eight of the present invention;
FIG. 9 is a schematic view of step nine of the present invention;
FIG. 10 is a schematic representation of step ten of the present invention;
FIG. 11 is a schematic representation of step eleven of the present invention;
FIG. 12 is a schematic representation of step twelve of the present invention;
FIG. 13 is a schematic view of step thirteen of the present invention;
FIG. 14 is a schematic representation of step fourteen in accordance with the present invention;
FIG. 15 is a schematic representation of step fifteen of the present invention;
FIG. 16 is a schematic representation of a sixteenth step of the present invention;
FIG. 17 is a schematic representation of step seventeen of the present invention;
FIG. 18 is a schematic representation of step eighteen of the present invention;
FIG. 19 is a schematic diagram of the nineteenth step of the present invention;
fig. 20 is a cross-sectional view of a device of the present invention.
Fig. 21 is a cross-sectional view of a finished device from a prior art process.
Detailed Description
The present invention will be described in detail with reference to specific embodiments.
The invention relates to a method for manufacturing a shielded gate trench MOSFET (metal-oxide-semiconductor field effect transistor) for improving the quality of a gate oxide layer.
The method specifically comprises the following steps:
the method comprises the following steps: providing an n-type heavily doped n + substrate, and forming an n-type epitaxial layer on the n + substrate;
step two: forming a thick oxide layer on the surface of the epitaxial layer to form a hard mask;
step three: forming a deep groove of an active area and a deep groove of a terminal area by photoetching and dry etching, wherein the deep groove of the terminal area surrounds the deep groove of the active area, and finally removing the thick oxide layer;
step four: growing field oxide layers on the bottom and the side wall of the deep groove by utilizing a wet thermal oxidation process;
step five: carrying out first polysilicon deposition by utilizing a polysilicon deposition process;
step six: carrying out polysilicon back etching by a dry etching process to obtain a shallow trench above the active region deep trench, wherein the first polysilicon and the field oxide layer in the terminal region deep trench are not back etched under the protection of the photoresist;
step seven: removing the field oxide layer by photoetching and wet etching;
step eight: continuously etching the polysilicon in the groove by using an etching process;
step nine: adjusting the thickness and the shape of the oxide layer between the grid and the source by utilizing special conditions of anisotropic deposition of the oxide layer, namely high-density plasma chemical vapor deposition (HDP CVD);
step ten: removing the residual field oxide layer on the side wall by utilizing a wet etching process;
step eleven: forming a gate oxide layer by dry oxidation;
step twelve: depositing polysilicon for the second time, and back-etching the polysilicon for the second time by a dry method to form a grid electrode of the shallow trench MOSFET device;
step thirteen: removing the surface oxide layer before well injection;
fourteen steps: injecting P-BODY to form a P well;
step fifteen: manufacturing a device active region by implantation;
sixthly, the steps are as follows: depositing a dielectric layer, and etching a contact hole;
seventeen steps: etching and injecting the contact hole to form ohmic contact;
eighteen steps: completing a surface metal structure;
nineteen steps: and thinning the back and finishing the back metal structure.
According to the invention, the thickness and the appearance of the oxide layer between the grid and the source are adjusted by high-density plasma chemical vapor deposition (HDP CVD) under a special condition, so that the problems of insufficient withstand voltage between the grids and the sources and failure of a device caused by uneven oxide layers between the low-quality oxide layer formed by the oxidation of polysilicon and the root oxide layer between the grids and the sources in the old scheme in figure 21 are avoided.
The method has the following characteristics:
firstly, secondary back etching of primary polysilicon;
II, secondly: the thickness and the shape of the oxide layer between the grid and the source are adjusted by high-density plasma chemical vapor deposition (HDP CVD) under the special condition of anisotropic deposition of the primary oxide layer;
and thirdly, removing the oxide layer on the surface of the device before well injection by utilizing the extremely large corrosion rate difference between the dry-method oxide layer and the deposited oxide layer.
The invention is not limited to the examples, and any equivalent changes to the technical solution of the invention by a person skilled in the art after reading the description of the invention are covered by the claims of the invention.

Claims (2)

1.改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法，其特征在于：1. The manufacturing method of the shielded gate trench MOSFET for improving the quality of gate oxide layer is characterized in that: 通过在深槽内填充并回刻蚀多晶硅，使两个深槽互相电荷平衡完成超结功能，再在深槽上方采用氧化层淀积加厚栅极源极间氧化层，最后通过栅极热氧化和多晶硅淀积，共同构成屏蔽栅沟槽器件；By filling and etching back polysilicon in the deep groove, the two deep grooves are charged with each other to complete the superjunction function, and then an oxide layer is used to deposit the oxide layer on the top of the deep groove to thicken the oxide layer between the gate and the source, and finally heat the gate through the gate heat. Oxidation and polysilicon deposition together form a shielded gate trench device; 包括以下步骤：Include the following steps: 步骤一：提供 n 型重掺杂的 n+ 衬底，并在n+衬底上形成n型外延层；Step 1: provide an n-type heavily doped n+ substrate, and form an n-type epitaxial layer on the n+ substrate; 步骤二：在外延层表面形成厚氧化层，形成硬掩膜；Step 2: forming a thick oxide layer on the surface of the epitaxial layer to form a hard mask; 步骤三：通过光刻、干法腐蚀形成有源区的深沟槽与终端区的深沟槽，终端区深沟槽包围有源区深沟槽，最后去除厚氧化层；Step 3: forming deep trenches in the active area and deep trenches in the terminal area by photolithography and dry etching, the deep trenches in the terminal area surround the deep trenches in the active area, and finally remove the thick oxide layer; 步骤四：利用湿法热氧化工艺在所述深沟槽底部和侧壁生长场氧化层；Step 4: using a wet thermal oxidation process to grow a field oxide layer on the bottom and sidewalls of the deep trench; 步骤五：利用多晶硅淀积工艺，进行第一次多晶硅淀积；Step 5: use the polysilicon deposition process to perform the first polysilicon deposition; 步骤六：通过干法腐蚀工艺进行多晶硅回刻，使有源区深沟槽上方得到一个浅沟槽，终端区深沟槽内的第一多晶硅及场氧化层在光刻胶的保护下不回刻；Step 6: Carry out polysilicon etching back by a dry etching process, so that a shallow trench is obtained above the deep trench in the active area, and the first polysilicon and the field oxide layer in the deep trench in the terminal area are protected by photoresist not engraved; 步骤七：通过光刻、湿法腐蚀对场氧化层进行去除，在多晶硅以上的侧壁区域不全部去除，保留一层薄层；Step 7: The field oxide layer is removed by photolithography and wet etching, and the sidewall area above the polysilicon is not completely removed, but a thin layer is retained; 步骤八：利用刻蚀工艺继续回刻沟槽内的多晶硅，即二次回刻；Step 8: Continue to etch back the polysilicon in the trench by using the etching process, that is, to etch back the second time; 步骤九：采用能使氧化层各向异性淀积的条件进行高密度等离子体化学气相淀积，实现对栅极源极间氧化层厚度和形貌的调整；Step 9: performing high-density plasma chemical vapor deposition under conditions that enable anisotropic deposition of the oxide layer, so as to adjust the thickness and morphology of the oxide layer between the gate and the source; 步骤十：利用湿法刻蚀工艺去除侧壁剩余场氧化层；Step 10: use a wet etching process to remove the remaining field oxide layer on the sidewall; 步骤十一：利用干法氧化形成栅极氧化层；Step eleven: forming a gate oxide layer by dry oxidation; 步骤十二：第二次多晶硅淀积，并对第二次多晶硅干法回刻，形成浅槽MOSFET器件栅极；Step 12: depositing polysilicon for the second time, and dry etching back the polysilicon for the second time to form the gate of the shallow trench MOSFET device; 步骤十三：阱注入前对表面氧化层进行去除；Step 13: remove the surface oxide layer before the well implantation; 步骤十四：P-BODY注入，形成P阱；Step 14: P-BODY implantation to form a P well; 步骤十五：通过注入，制作器件有源区；Step 15: fabricate the active region of the device by implantation; 步骤十六：淀积介质层，接触孔刻蚀；Step 16: depositing a dielectric layer, etching the contact hole; 步骤十七：接触孔刻蚀注入形成欧姆接触；Step seventeen: contact hole etching and implantation to form ohmic contact; 步骤十八：完成表面金属结构；Step 18: Complete the surface metal structure; 步骤十九：背面减薄并完成背面金属结构。Step 19: Thin the backside and complete the backside metal structure. 2.利用权利要求1所述的制造方法制得的改善栅极氧化层质量的屏蔽栅沟槽MOSFET结构。2 . The shielded gate trench MOSFET structure with improved gate oxide quality obtained by the manufacturing method according to claim 1 .
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