CN110429134B - IGBT device with asymmetric primitive cells and preparation method - Google Patents

Abstract

The invention discloses an IGBT device with asymmetric primitive cells and a preparation method thereof, the IGBT device comprises a P-type collector, wherein an N-type substrate is arranged at the top of the P-type collector, a plurality of grooves are arranged on the N-type substrate, gate oxide layers are respectively arranged on the side walls and the bottom of the grooves, one half part of each groove belongs to an effective primitive cell, the other half part of each groove belongs to a virtual primitive cell, the thickness of the gate oxide layer at the bottom of each groove and the thickness of the gate oxide layer on the side wall of each groove in the virtual primitive cell are both larger than those of the gate oxide layers on the side walls of the grooves in the effective primitive cells, a polycrystalline silicon layer is arranged in each groove, a P-type well is arranged between every two adjacent grooves, a heavily doped P-type region and a heavily doped N-type region are arranged in each P-type well, the heavily doped N-type region belongs to an effective primitive cell, one half of the heavily doped P-type region belongs to an effective primitive cell, an interlayer isolation layer is arranged at the top of each groove, a contact hole is arranged on the interlayer isolation layer, and a collector metal layer is covered outside the interlayer isolation layer. The invention can reduce the Miller capacitance and keep the conduction voltage drop of the device unchanged.

Description

A kind of IGBT device with asymmetric primary cell and its preparation method

technical field

The invention relates to an IGBT device, in particular to an IGBT device with an asymmetric primary cell and a preparation method.

Background technique

The structure of the IGBT device in the prior art is shown in Figure 1, the effective primary cell and the dummy primary cell (dummy primary cell) are symmetrically distributed, the thickness of the gate oxide layer at the bottom of the trench, the thickness of the trench sidewall in the dummy primary cell The thickness of the gate oxide layer and the thickness of the gate oxide layer on the trench sidewalls in the effective cells are the same. The part of the groove beyond the P-type well is used as the device accumulation area. The length of the device accumulation area is closely related to the device on-voltage drop and Miller capacitance. If the length of the device accumulation area decreases, the Miller capacitance will decrease, and the device on-voltage drop will decrease. decrease will increase. However, from an application point of view, it is desirable that the device conduction voltage drop and Miller capacitance be as small as possible. Therefore, the IGBT device in the prior art cannot reduce the Miller capacitance while keeping the turn-on voltage drop of the device constant.

Contents of the invention

Purpose of the invention: The purpose of the invention is to provide an IGBT device with an asymmetric primary cell and its preparation method, which can reduce the Miller capacitance while keeping the on-voltage drop of the device constant.

Technical solution: The IGBT device with asymmetric primary cells according to the present invention includes a P-type collector, an N-type substrate is arranged on the top of the P-type collector, and a plurality of grooves are arranged on the N-type substrate. Both the sidewall and the bottom are provided with a gate oxide layer. Half of a trench belongs to the effective cell, and the other half belongs to the dummy cell. The thickness of the gate oxide layer at the bottom of the trench and the gate thickness of the trench sidewall in the dummy cell The thickness of the oxide layer is greater than the thickness of the gate oxide layer on the side wall of the trench in the effective cell. There is a polysilicon layer in the trench, a P-type well is set between two adjacent trenches, and a heavily doped well is set in the P-type well. Miscellaneous P-type region and heavily doped N-type region, the heavily doped N-type region is an effective cell, half of the heavily doped P-type region is an effective cell, and the other half is a virtual cell, and the top of the trench is provided with interlayer isolation layer, the interlayer isolation layer is provided with a contact hole, and the interlayer isolation layer is covered with a collector metal layer.

Further, all grooves have the same size.

Further, the thickness of the gate oxide layer at the bottom of the trench and the thickness of the gate oxide layer on the sidewall of the trench in the dummy cell are greater than the thickness of the gate oxide layer on the sidewall of the trench in the effective cell by the following method: Nitrogen is injected into the side wall of the trench in the effective cell, and no nitrogen is injected into the bottom of the trench and the side wall of the trench in the dummy cell, and then the side wall of the trench in the effective cell, the bottom of the trench and the dummy cell A gate oxide layer is formed on the sidewall of the trench in the cell.

The method for preparing the IGBT device with an asymmetric primary cell of the present invention comprises the following steps:

S1: Perform ring implantation, field oxide growth and etching in the termination area;

S2: generating an N-type substrate in the original cell region;

S3: Etching multiple grooves on the N-type substrate;

S4: Nitrogen element implantation is performed on the side wall of the trench in the effective cell;

S5: growing a gate oxide layer on the sidewalls of the trenches in the effective cells, the bottom of the trenches, and the sidewalls of the trenches in the virtual cells;

S6: performing polysilicon layer deposition, and then etching the polysilicon layer outside the trench;

S7: performing injection and annealing of a P-type well between two adjacent trenches;

S8: Form a heavily doped P-type region and a heavily doped N-type region in the P-type well, the heavily doped N-type region belongs to the effective original cell, half of the heavily doped P-type region belongs to the effective original cell, and the other half belongs to the virtual original cell ;

S9: Depositing an interlayer isolation layer on top of the trench;

S10: Etching a contact hole on the interlayer isolation layer, and there is a contact hole between two adjacent trenches;

S11: Depositing a collector metal layer on the surface of the interlayer isolation layer;

S12: depositing a passivation layer on both the surface of the collector metal layer and the terminal area, and then removing the passivation layer on the surface of the collector metal layer, leaving only the passivation layer in the terminal area;

S13: generating a P-type collector at the bottom of the N-type substrate.

Further, in the step S4, the included angle between the direction of nitrogen implantation and the symmetry axis of the trench is 20°-75°.

Further, in the step S4, the concentration of the nitrogen element is 2×10 ¹³ -1×10 ¹⁵ atom/cm ² , and the energy is 30KeV-60KeV.

Beneficial effects: the invention discloses an IGBT device with an asymmetric primary cell and its preparation method, by setting the thickness of the gate oxide layer at the bottom of the trench and the thickness of the gate oxide layer on the sidewall of the trench in the dummy cell to be uniform If the thickness of the gate oxide layer is greater than that of the sidewall of the trench in the effective cell, the Miller capacitance can be greatly reduced without changing the length of the accumulation region of the device, while the conduction voltage drop of the device remains unchanged.

Description of drawings

Fig. 1 is the schematic diagram of IGBT device in the prior art;

Fig. 2 is the schematic diagram of IGBT device in the specific embodiment of the present invention;

Fig. 3 is the schematic diagram of nitrogen element injection in the specific embodiment of the present invention;

4 is a schematic diagram after the gate oxide layer is formed in a specific embodiment of the present invention;

FIG. 5 is a schematic diagram after forming a polysilicon layer in a specific embodiment of the present invention.

Detailed ways

The IGBT device structure in the prior art is shown in Figure 1, including a collector metal layer 11, a trench 12, an N-type substrate 13, a P-type collector 14, an interlayer isolation layer 15, a P-type well 16, a heavily doped Miscellaneous N-type region 17 , heavily doped P-type region 18 , effective primitive cell 101 , dummy primitive cell 102 and contact hole 19 . It can be seen that the effective primary cell 101 and the virtual primary cell 102 are symmetrical, the thickness of the gate oxide layer at the bottom of the trench 12, the thickness of the gate oxide layer on the sidewall of the trench 12 in the virtual primary cell 102, and the thickness of the trench in the effective primary cell 101 The thicknesses of the gate oxide layers on the 12 sidewalls are all the same.

This specific embodiment discloses an IGBT device with an asymmetric primary cell, as shown in FIG. A plurality of trenches 22 are provided, and gate oxide layers are provided on the sidewalls and bottoms of the trenches 22. Half of one trench 22 belongs to the effective original cell 201, and the other half belongs to the virtual original cell 202. The bottom of the trench 22 The thickness of the gate oxide layer 221 and the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the dummy cell 202 are greater than the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the effective cell 201, and the trench 22 is provided with A polysilicon layer 222, a P-type well 26 is arranged between two adjacent trenches 22, a heavily doped P-type region 28 and a heavily doped N-type region 27 are arranged in the P-type well 26, and the heavily doped N-type region 27 Belonging to the effective original cell 201, half of the heavily doped P-type region 28 belongs to the effective original cell 201, and the other half belongs to the virtual original cell 202. The top of the trench 22 is provided with an interlayer isolation layer 25, and a contact hole is provided on the interlayer isolation layer 25. 29. The collector metal layer 21 is covered outside the interlayer isolation layer 25 . All grooves 22 are of the same size.

The thickness of the gate oxide layer 221 at the bottom of the trench 22 and the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the dummy cell 202 are greater than the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the effective cell 201 by the following Implementation method: Nitrogen is injected into the sidewall of the groove 22 in the effective primitive cell 201, and nitrogen is not injected into the bottom of the groove 22 and the sidewall of the groove 22 in the virtual primitive cell 202, and then the groove in the effective primitive cell 201 A gate oxide layer 221 is formed on the sidewall of the trench 22 , the bottom of the trench 22 and the sidewall of the trench 22 in the dummy cell 202 .

This specific embodiment also discloses a method for preparing an IGBT device with an asymmetric primary cell, including the following steps:

S1: Perform ring implantation, field oxide growth and etching in the termination area;

S2: generating an N-type substrate 23 in the primary cell region;

S3: Etching a plurality of trenches 22 on the N-type substrate 23;

S4: Nitrogen element is implanted into the side wall of the trench 22 in the effective primary cell 201, as shown in FIG. The concentration is 2×10 ¹³ ～1×10 ¹⁵ atom/cm ² , and the energy is 30KeV～60KeV;

S5: growing a gate oxide layer 221 on the sidewall of the trench 22 in the effective cell 201, the bottom of the trench 22, and the sidewall of the trench 22 in the dummy cell 202, as shown in FIG. 4;

S6: Deposit the polysilicon layer 222, and then etch the polysilicon layer 222 outside the trench 22, as shown in FIG. 5;

S7: performing injection and annealing of the P-type well 26 between two adjacent trenches 22;

S8: Form a heavily doped P-type region 28 and a heavily doped N-type region 27 in the P-type well 26, the heavily doped N-type region 27 belongs to the effective primary cell 201, and half of the heavily doped P-type region 28 belongs to the effective primary cell 201, the other half belongs to the virtual primitive cell 202;

S9: Depositing an interlayer isolation layer 25 on top of the trench 22;

S10: etching a contact hole 29 on the interlayer isolation layer 25, and there is a contact hole 29 between two adjacent trenches 22;

S11: depositing the collector metal layer 21 on the surface of the interlayer isolation layer 25;

S12: Deposit a passivation layer on both the surface of the collector metal layer 21 and the terminal area, and then remove the passivation layer on the surface of the collector metal layer 21, leaving only the passivation layer in the terminal area;

S13: forming a P-type collector 24 at the bottom of the N-type substrate 23 .

The reason why the nitrogen element is implanted on the sidewall of the trench 22 in the effective cell 201 is because the growth rate of the gate oxide layer 221 will slow down after the nitrogen element implantation, so that the thickness of the gate oxide layer 221 at the bottom of the trench 22 and the virtual The thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the primary cell 202 is greater than the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the active cell 201 .

Claims (4)

1. An IGBT device with an asymmetric primary cell, comprising a P-type collector (24), an N-type substrate (23) is provided on the top of the P-type collector (24), and an N-type substrate (23) is provided on the N-type substrate (23). A plurality of trenches (22), the sidewalls and bottoms of the trenches (22) are provided with a gate oxide layer, which is characterized in that: half of a trench (22) belongs to the effective cell (201), and the other half belongs to The dummy cell (202), the thickness of the gate oxide layer (221) at the bottom of the trench (22) and the thickness of the gate oxide layer (221) on the sidewall of the trench (22) in the dummy cell (202) are all larger than the effective original cell (202). The thickness of the gate oxide layer (221) on the sidewall of the trench (22) in the cell (201), the polysilicon layer (222) is provided in the trench (22), and the P Well (26), the P-type well (26) is provided with a heavily doped P-type region (28) and a heavily doped N-type region (27), and the heavily doped N-type region (27) belongs to the effective primary cell (201 ), half of the heavily doped P-type region (28) belongs to the effective cell (201), and the other half belongs to the dummy cell (202). (25) is provided with a contact hole (29), and the interlayer isolation layer (25) is covered with a collector metal layer (21); All grooves (22) are of the same size; The thickness of the gate oxide layer (221) at the bottom of the trench (22) and the thickness of the gate oxide layer (221) on the sidewall of the trench (22) in the dummy cell (202) are greater than those in the effective cell (201) The thickness of the gate oxide layer (221) on the sidewall of the trench (22) is realized in the following manner: nitrogen element implantation is performed on the sidewall of the trench (22) in the effective cell (201), and the bottom of the trench (22) and the virtual The side wall of the groove (22) in the original cell (202) is not implanted with nitrogen element, and then the side wall of the groove (22), the bottom of the groove (22) and the virtual original cell (202) in the effective original cell (201) A gate oxide layer (221) is formed on the sidewall of the middle trench (22). 2. the method for preparing the IGBT device with asymmetric primary cell described in claim 1, is characterized in that: comprise the following steps: S1: Perform ring implantation, field oxide growth and etching in the termination area; S2: generating an N-type substrate in the primary cell region (23); S3: Etching a plurality of trenches (22) on the N-type substrate (23); S4: Implanting nitrogen element into the sidewall of the trench (22) in the effective primary cell (201); S5: growing a gate oxide layer (221) on the sidewall of the trench (22) in the effective cell (201), the bottom of the trench (22) and the sidewall of the trench (22) in the dummy cell (202); S6: depositing the polysilicon layer (222), and then etching the polysilicon layer (222) outside the trench (22); S7: performing injection and annealing of a P-type well (26) between two adjacent trenches (22); S8: Form a heavily doped P-type region (28) and a heavily doped N-type region (27) in the P-type well (26), the heavily doped N-type region (27) belongs to the effective cell (201), and the heavily doped Half of the hybrid P-type region (28) belongs to the effective primitive cell (201), and the other half belongs to the virtual primitive cell (202); S9: Depositing an interlayer isolation layer (25) on top of the trench (22); S10: Etching a contact hole (29) on the interlayer isolation layer (25), and there is a contact hole (29) between two adjacent trenches (22); S11: Depositing a collector metal layer (21) on the surface of the interlayer isolation layer (25); S12: Depositing a passivation layer on both the surface of the collector metal layer (21) and the termination region, and then removing the passivation layer on the surface of the collector metal layer (21), leaving only the passivation layer in the termination region; S13: forming a P-type collector (24) at the bottom of the N-type substrate (23). 3. The method for preparing an IGBT device with an asymmetric primary cell according to claim 2, characterized in that: in the step S4, the angle between the direction of nitrogen implantation and the symmetry axis of the trench (22) is 20°~75°. 4. The method for preparing an IGBT device with an asymmetric primary cell according to claim 2, characterized in that: in the step S4, the concentration of nitrogen element is 2×10 ¹³ ~1×10 ¹⁵ atom/cm ² , The energy is 30KeV~60KeV.

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