CN110164967A - Semiconductor device and its manufacturing method - Google Patents

Abstract

The present invention provides a kind of manufacturing method of semiconductor device, comprising: provides a substrate；Multiple grooves are formed in substrate；A layer of isolation oxide is formed in groove and above substrate；It deposits in layer of isolation oxide of the mask polysilicon in groove and on substrate；One first etching technics is carried out to remove a first part of mask polysilicon, and exposes a part of surface of the isolating oxide layer in groove；One first removal technique is carried out to remove a first part of layer of isolation oxide；One second etching technics is carried out to remove a second part of mask polysilicon, and exposes another part surface of the isolating oxide layer in groove；One second removal technique is carried out to remove a second part of layer of isolation oxide；And a polysilicon interlevel oxide layer (inter poly oxide layer) is formed on remaining mask polysilicon and remaining layer of isolation oxide, wherein polysilicon interlevel oxide layer has a concave upper surface.The present invention also provides a kind of semiconductor device.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device capable of reducing gate-drain capacitance (Cgd) and suppressing gate leakage current and a manufacturing method thereof.

Background technique

The semiconductor integrated circuit (IC) industry has gone through a stage of rapid development. Technological advances in integrated circuit materials and design have produced many generations of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation of integrated circuits.

In split gate trench metal oxide semiconductor field effect transistor (Metal-Oxide-SemiconductorField-Effect Transistor; MOSFET) components, the gate- Drain capacitance (Cgd) to increase the switching speed of the device. The mask polysilicon in the mask gate trench is electrically connected to the source, so that the trench gate polysilicon is electrically insulated from the drain. The gate polysilicon and the shield polysilicon are electrically insulated from each other by an inter-poly oxide (IPO) therebetween.

However, as device dimensions continue to shrink, backfill oxide is used as an interpoly oxide (IPO) to insulate the gate polysilicon and shielding in the process of split gate trench MOSFET devices. The technology of covering polysilicon is limited by the aspect ratio of the trench when backfilling the oxide, which limits the ability to control the thickness and quality of the oxide between polysilicon layers, resulting in gate-source leakage current ( gate to sourceleakage current) is too high. In addition, the ability of the shielded gate trench (SGT) structure to reduce the gate-drain capacitance (Cgd) is also limited.

Therefore, there is a need in the art for an improved split-gate trench MOSFET device and method of manufacturing the same.

Contents of the invention

An embodiment of the invention provides a method for manufacturing a semiconductor device. The method includes: providing a substrate; forming a plurality of trenches in the substrate; forming an isolation oxide layer in the trenches and above the substrate; depositing a shield polysilicon (shield polysilicon) in the trenches and isolation oxide on the substrate on the object layer; perform a first etching process to remove a first portion of the mask polysilicon, and expose a part of the surface of the isolation oxide layer in the trench; perform a first removal process to remove the isolation oxide layer a first part of a first part; perform a second etching process to remove a second part of the mask polysilicon, and expose another part of the surface of the isolation oxide layer in the trench; perform a second removal process to remove the isolation a second portion of the oxide layer; and forming an inter-poly oxide layer on the remaining mask polysilicon and the remaining isolation oxide layer. Wherein, the interpolysilicon oxide layer has a concave top surface.

Another embodiment of the present invention provides a semiconductor device. The above semiconductor device includes: a substrate including a plurality of trenches; an isolation oxide layer located in the trenches; a mask polysilicon located in the trenches and surrounded by the isolation oxide layer; and an interpolysilicon oxide layer located in the isolation oxide layer and mask polysilicon. Wherein, the interpolysilicon oxide layer has a concave top surface.

The beneficial effect of the present invention is that, the semiconductor device manufacturing method of the present invention performs a two-stage etching process on the mask oxide layer and a two-stage removal process on the isolation oxide layer, so as to slow down the process on the trench side in the past process. The recessed degree of the isolation oxide generated between the wall and the sidewall of the mask oxide allows the interlayer polysilicon oxide filled in the subsequent process to be well deposited on the mask polysilicon and the isolation oxide layer without creating pores ( void). Moreover, the degree of depression generated by the isolation oxide layer between the sidewall of the trench and the sidewall of the mask polysilicon is reduced, and the interpolysilicon oxide layer (IPO) filled in the subsequent process has no void. Good electrical insulation effect is provided between the gate polysilicon and the mask polysilicon. Moreover, since there are no pores, the inter-polysilicon oxide layer (IPO) can provide a good isolation effect for suppressing leakage current from the gate to the source, thereby improving the performance of the semiconductor device. In addition, the concave top surface of the interpolysilicon oxide layer (IPO) presents an upwardly curved arc near the sidewall of the trench, which is equivalent to increasing the thickness of the oxide layer between the gate polysilicon and the drain, thus reducing the The gate-drain capacitance (Cgd) of a semiconductor device.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are specifically listed below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are only some embodiments of the present invention, and those skilled in the art can also obtain other drawings based on these drawings without any creative effort.

1 to 10 are schematic cross-sectional views showing various stages in the process of a semiconductor device according to some embodiments of the present invention.

Figure number:

10 ~ device;

100～substrate;

102～groove;

104, 104'～isolation oxide layer

104"～remaining isolation oxide layer;

104a, 104b ~ surface portion;

104S-1 ~ first top surface portion

104S-2 ~ second top surface portion;

106, 106'～mask polysilicon;

106" ~ remaining mask polysilicon;

106’S, 106”S～side wall;

108～polysilicon interlayer oxide;

108'～polysilicon interlayer oxide layer;

106S, 108S～top surface;

110～gate oxide layer;

112～gate polysilicon;

D1, D2 ~ depth;

H～height difference;

P1, P2～contour;

T1, T2, T3 ~ thickness;

W1, W2 ~ concave part.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. The specific components and configurations in the present invention are for simplicity, but the present invention is not limited by these embodiments. For example, a description of forming a first element on a second element may include embodiments in which the first element is in direct contact with the second element, as well as embodiments having additional elements formed between the first element and the second element such that the second element An embodiment in which one element is not in direct contact with a second element. In addition, for the sake of brevity, the present invention is represented by repeated element symbols and/or letters in different examples, but it does not mean that there is a specific relationship between the various embodiments and/or structures. It is emphasized that, in accordance with the standard practice in the industry, various elements have not necessarily been drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of discussion.

As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly dictates otherwise. It can be further understood that when terms such as "comprising" are used in the specification, they are intended to indicate the existence of the stated features, steps, operations, elements, and/or components, but do not exclude the addition of one or more other features, steps, and operations. , elements, components and/or the presence of combinations of the above.

"An embodiment" or "an embodiment" referred to throughout the specification means that the specific features, structures, or characteristics described in the embodiment are included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Some embodiments of the present invention are described below. 1-10 are schematic cross-sectional views showing various stages in the process of a semiconductor device 10 according to some embodiments of the present invention. Additional operations may be provided before, during, and/or after the stages described in FIGS. 1-10 . In various embodiments, some of the aforementioned operations may be moved, deleted or replaced. Additional features may be added to the semiconductor device. In various embodiments, some of the features described below may be removed, deleted or substituted.

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. In some embodiments of the present invention, the aforementioned semiconductor device is a split gate trench metal oxide semiconductor field effect transistor (MOSFET) device. The present invention improves the process by performing a two-stage etching process on the mask polysilicon (shield polysilicon) and a two-stage removal process on the isolation oxide layer, so as to slow down the damage to the sidewall of the trench and the mask polysilicon in the past process. The degree of depression of the isolation oxide generated between the sidewalls makes the polysilicon interlayer oxide (inter-polyoxide) filled in the subsequent process not generate (or substantially generate) voids (void), thereby improving the protection of the polysilicon layer. The ability to control the thickness and quality of the intermediate oxide layer achieves the purpose of suppressing gate leakage current.

An embodiment of the invention provides a method for manufacturing a semiconductor device. As shown in FIG. 1 , according to some embodiments, a substrate 100 is provided. In some embodiments, the substrate 100 may be a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate 100 is a silicon wafer. Substrate 100 may comprise silicon or other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 100 may include a sapphire substrate, a silicon substrate, or a silicon carbide substrate. In some embodiments, the substrate 100 may include a semiconductor material, an insulator material, a conductor material, or a one-layer or multi-layer structure composed of a combination thereof. For example, the substrate 100 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In another embodiment, the substrate 100 may also include a silicon on insulator (SOI). The SOI substrate can be formed using a isolation implantation of oxygen (SIMOX) process, a wafer bonding process, other applicable methods, or a combination of the foregoing. In another embodiment, the substrate 100 may also be composed of multiple layers of materials, such as Si/SiGe, Si/SiC. In another embodiment, the substrate 100 may include an insulator material, such as an organic insulator, an inorganic insulator, or a one-layer or multi-layer structure formed by a combination thereof. In another embodiment, the substrate 100 may also include a conductive material, such as polysilicon, metal, alloy, or a one-layer or multi-layer structure formed by a combination thereof.

As shown in FIG. 1 , a plurality of trenches (or grooves) 102 are formed in a substrate 100 according to some embodiments. In some embodiments, trenches 102 may be formed using, for example, one or more photolithography and etching processes. It should be understood that the size, shape, and position of the trench 102 shown in FIG. 1 are for illustration only, rather than limiting the present invention.

Next, as shown in FIG. 2 , according to some embodiments, an isolation oxide layer 104 is formed in the trench 102 and on the substrate 100 . In some embodiments, the isolation oxide layer 104 can be conformally formed on the sidewalls and bottom of the trench 102 and the top surface of the substrate 100 by using, for example, thermal oxidation, or other suitable deposition processes. The thickness T1 of the isolation oxide layer 104 can be adjusted according to the device size and design requirements of the semiconductor device. In some embodiments, the thickness T1 of the isolation oxide layer 104 on the sidewalls and bottom of the trench 102 and on the top surface of the substrate 100 may be, for example, 70 nm to 150 nm.

As shown in FIG. 2 , a mask polysilicon 106 is deposited in the trench 102 and on the isolation oxide layer 104 on the substrate 100 in accordance with some embodiments. In some embodiments, the mask polysilicon 106 can be filled in the trench 102 and deposited on the isolation oxide layer 104 on the substrate 100 using, for example, chemical vapor deposition (CVD) or other suitable polysilicon deposition techniques. superior. In some embodiments, the mask polysilicon 106 may be formed of undoped polysilicon or in-situ doped polysilicon.

As shown in FIG. 3 , according to some embodiments, a first etching process is performed to remove a first portion of the mask polysilicon 106 and expose a portion of the surface 104 a of the isolation oxide layer 104 in the trench 102 . In some embodiments, the first etching process may include, for example, an etch-back process. In some embodiments, the mask polysilicon 106 may be recessed into the trench 102 by removing a first portion of the mask polysilicon 106 until a desired depth is reached. For example, as shown in FIG. 3 , in one embodiment, the top surface of the mask polysilicon 106 ′ may be lower than the top surface of the substrate 100 . The surface 104 a is a portion of the surface of the isolation oxide layer 104 formed on the sidewalls of the trench 102 and exposed by removing the first portion of the mask polysilicon 106 . In some embodiments, the mask polysilicon 106' having the first portion removed has a depth D1 in the trench 102, as shown in FIG. 3 . It should be noted that, in some embodiments, the depth D1 of the mask polysilicon 106' is not the desired depth of the mask polysilicon in the final semiconductor device. In some embodiments, the depth D1 of the mask polysilicon 106' is greater than the desired depth of the mask polysilicon in the final semiconductor device.

In some embodiments, a chemical planarization process such as a chemical mechanical planarization polishing (CMP) process may be performed on the mask polysilicon 106 before performing the first etching process to remove the first portion of the mask polysilicon 106. until the isolation oxide layer 104 is exposed. Alternatively, in some embodiments, the step of the above chemical mechanical planarization polishing (CMP) process can be omitted, and the above first etching process can be performed directly, so that the mask polysilicon 106 is recessed into the trench 102 until the desired depth.

As shown in FIG. 4 , according to some embodiments, a first removal process is performed to remove a first portion of the isolation oxide layer 104 . In some embodiments, the first removal process may include, for example, a wet etching process, an oxidation etching process, or other suitable processes. In some embodiments, after the first removal process, the portion of the removed first portion of the isolation oxide layer 104 ′ exposed to the trench 102 (corresponding to the portion with the surface 104 a in FIG. 3 ) has a thinner thickness. T2, as shown in Figure 4. In some embodiments, after the first removal process, the isolation oxide layer 104' on the substrate 100 also has a thinner thickness T2. In some embodiments, thickness T2 is less than thickness T1. In some embodiments, after the first removal process, the first portion of the isolation oxide layer 104' is removed to form a recessed portion W1 adjacent to the mask polysilicon 106', exposing the mask polysilicon 106'. A portion of the sidewall 106'S. As shown in FIG. 4 , in some embodiments, the recessed portion W1 extends between the sidewall of the mask polysilicon 106' and the isolation oxide layer 104' having a thickness T2.

Although the concave portion W1 drawn in FIG. 4 has a flat upper surface, it is understood that the diagram drawn in FIG. 4 is only an example. In some embodiments, the depression of the isolation oxide layer 104' The upper surface of the portion W1 may have a concave curvature.

As shown in FIG. 5 , according to some embodiments, a second etching process is performed to remove a second portion of the mask polysilicon 106 and expose another portion of the surface 104 b of the isolation oxide layer 104 in the trench 102 . In some embodiments, the first etching process may include, for example, an etch-back process. In some embodiments, the mask polysilicon 106 can be further recessed into the trench 102 by removing the second portion of the mask polysilicon 106 until a desired depth is reached. For example, as shown in FIG. 5 , in one embodiment, the top surface of the mask polysilicon 106 ″ may be lower than the upper surface of the recessed portion W1 of the isolation oxide layer 104 ′. The surface 104 b is formed on the sidewall of the trench 102 Another part of the surface of the isolation oxide layer 104 is exposed by removing the second part of the mask polysilicon 106. In some embodiments, the mask polysilicon 106" after removing the second part is in the trench 102 There is a depth D2 in it, as shown in FIG. 5 . It should be noted that, in some embodiments, the depth D2 of the mask polysilicon 106 ″ is the desired depth of the mask polysilicon in the final semiconductor device. In some embodiments, the depth D2 is smaller than the depth D1 .

As shown in FIG. 5 , since the portion of the isolation oxide layer 104 exposed in the trench 102 through the second etching process (ie, the portion having the surface 104 b ) is protected by the mask polysilicon 106 ′ during the first removal process. is not removed, therefore, after the second etching process, the part of the isolation oxide layer 104″ having the surface 104b still has the same thickness as the thickness T1. That is, since the embodiment of the present invention performs Two-stage etching process (the first etching process and the second etching process), during the first removal process on the isolation oxide 104, a part of the isolation oxide layer 104 can have The protection of the mask oxide 106' of the depth D1, so the original thickness T1 is retained. Therefore, after the second etching process, the isolation oxide layer 104' exposed in the trench 102 has different thicknesses (T1 and T2 ), and in such a state (as shown in FIG. 5 ), a subsequent second removal process is performed.

As shown in FIG. 6 , according to some embodiments, a second removal process is performed to remove the second portion of the isolation oxide layer 104 . In some embodiments, the second removal process may include, for example, a wet etching process, an oxidation etching process, or other suitable processes. In some embodiments, the second removal process may be the same as the first removal process. In some embodiments, the second removal process may be different from the first removal process. The first removal process and the second removal process can be selected and adjusted according to the different process conditions such as the element size of the semiconductor device and the depth of the mask polysilicon in the two-stage etching process. 2. Process conditions of the removal process. It should be noted that the final top surface profile of the isolation oxide layer can be determined by controlling the conditions of the first removal process and the second removal process, thereby affecting the top surface of the interpolysilicon oxide layer 108 ′ in the final semiconductor device 10 contour.

As shown in FIG. 6 , in some embodiments, after the second removal process, a second portion of the isolation oxide layer 104 ″ (also sometimes referred to herein as the remaining isolation oxide layer 104 ″) is removed. The portion exposed to the trench 102 (roughly corresponding to the portion with the surface 104a in FIG. 3 ) has a thinner thickness T3. In some embodiments, after the second removal process, the remaining isolation oxide layer 104″ on the substrate 100 also has a thinner thickness T3. In some embodiments, the thickness T3 is less than the thickness T2. In other In an embodiment, after the second removal process, the isolation oxide layer 104' may also be completely removed at a portion substantially corresponding to the surface 104a in FIG. can be completely removed.

As shown in FIG. 6 , in some embodiments, after the second removal process, the second portion of the isolation oxide layer 104 ″ is removed to further form another recessed portion W2 in a region adjacent to the mask polysilicon 106 ″, A part of the sidewall 106"S of the mask polysilicon 106" is exposed. As shown in FIG. 6 , in some embodiments, the recessed portion W2 extends between the sidewall of the mask polysilicon 106 ″ and the isolation oxide layer 104 ″ having a thickness T3 .

It should be noted that during the second removal process, since the protected isolation oxide layer 104" (the portion having the surface 104b) in FIG. 5 still has the same thickness as the thickness T1, the second removal process The degree of depression caused by the part of the isolation oxide layer 104" will be relatively slow. As shown in FIG. 6 , in some embodiments, after performing the second removal process to remove the second portion of the isolation oxide layer 104 , the top surface of the remaining isolation oxide layer 104 ″ is substantially removed from the mask polysilicon 106 . The sidewall of the trench 102 gently extends upward toward the sidewall of the trench 102. In some embodiments, the recessed portion W2 formed after the second removal process has an uneven (or discontinuous) top surface.

As shown in FIG. 6 , in some embodiments, the top surface 104S of the recessed portion W2 formed after the second removal process may consist of a first top surface portion 104S- 1 and a second top surface portion 104S- 2 . Although the first top surface portion 104S-1 and the second top surface portion 104S-2 of the concave portion W2 drawn in FIG. 6 are flat surfaces, it is understood that the drawing in FIG. 6 is only For example, in some embodiments, the first top surface portion 104S-1 and the second top surface portion 104S-2 of the recessed portion W2 of the isolation oxide layer 104″ may respectively have a concave curvature.

More specifically, as shown in FIG. 6, in some embodiments, after the second removal process is performed to remove the second portion of the isolation oxide layer 104, the remaining isolation oxide layer 104″ and the mask polysilicon 106 The first top surface portion 104S-1 adjacent to the sidewall of the trench 102 has a first curvature, while the remaining second top surface portion 104S-2 of the isolation oxide layer 104" adjacent to the sidewall of the trench 102 has a first curvature. Two curvatures. In some embodiments, the first curvature is different from the second curvature. In some embodiments, the first curvature is greater than the second curvature. In some embodiments, the first curvature can be, for example, 0.06 to 0.1 nm ⁻¹ In some embodiments, the second curvature may be, for example, 0.02 to 0.025 nm ⁻¹ .

As shown in FIG. 6 , in some embodiments, after performing the second removal process to remove the second portion of the isolation oxide layer 104 , the remaining isolation oxide layer 104 ″ is adjacent to the first portion of the mask polysilicon 106 ″. The height difference H between the lowest point of the top surface portion 104S- 1 and the remaining top surface 106S of the mask polysilicon 106 ″ may be smaller than the thickness T1 of the isolation oxide layer 104 above the substrate 100 as shown in FIG. 2 .

It is worth mentioning that such a small height difference is the result of the improvement of the process of the present invention. In the past, in order to remove the isolation oxide layer located on the sidewall of the trench and on the substrate, the previous process usually over-etched the isolation oxide layer, resulting in the isolation oxide layer on the sidewall of the mask polysilicon and the sidewall of the trench. A distinct recess is formed between them, resulting in a significant height difference between the isolation oxide layer and the top surface of the mask polysilicon. However, since the embodiment of the present invention performs a two-stage etching process on the mask polysilicon and a two-stage removal process on the isolation oxide layer, the isolation oxide is between the sidewall of the mask polysilicon and the sidewall of the trench. The resulting level of dishing is mitigated, while also reducing the height difference between the isolation oxide layer and the top surface of the mask polysilicon. As a result, there is no (or substantially no) void in the interpolysilicon layer oxide filled into the trench 102 in subsequent processes. Since the IPO can be well deposited, the formation of the IPO layer can be better controlled, improving the performance of the final semiconductor device.

As shown in FIG. 6, in some embodiments, after performing a second removal process to remove the second portion of the isolation oxide layer 104, the remaining first top surface portion 104S-1 of the isolation oxide layer 104″ and the second top surface portion 104S-2 and the top surface 106S of the mask polysilicon 106″ form a profile P1. In some embodiments, the profile P1 can be generally regarded as a concave curve.

As shown in FIG. 7 , an IPO 108 is deposited in the trench 102 and above the substrate 100 in accordance with some embodiments. In some embodiments, the polysilicon interlayer oxide 108 may be deposited by, for example, high density plasma chemical vapor deposition (HDPCVD), or other suitable deposition processes. As mentioned above, in some embodiments, the interpoly oxide 108 may completely cover the isolation oxide layer 104 and the mask poly 106 without (or substantially without) voids. Such a result is beneficial to improve the control of the thickness and quality of the interpoly oxide layer, improve the performance of the final semiconductor device, for example, reduce the gate-drain capacitance (Cgd) and suppress the gate-to-source leakage current (gate to source leakage current).

As shown in FIG. 8 , according to some embodiments, a third etch process is performed to remove a portion of the IPO 108 and expose a portion of the sidewall of the trench 102 . In some embodiments, the third etching process may include, for example, a dry etching process, a wet etching process, an etching back process, other suitable etching processes, or a combination thereof. As shown in FIG. 8 , in some embodiments, the interpolysilicon layer oxide 108 can be etched to a target depth by using, for example, an etch-back process to form an interpolysilicon layer oxide layer 108 ′ on the remaining mask polysilicon 106 ″ and on the remaining isolation oxide layer 104". For example, as shown in FIG. 8 , in one embodiment, the top surface 108S of the interpolysilicon oxide layer 108 ′ may be lower than the top surface of the substrate 100 . In some embodiments, after the third etching process, the remaining isolation oxide layer 104" located on the sidewall of the trench 102 and on the substrate 100 can be completely removed together. In some embodiments, the interpolysilicon oxide layer 108' may be used to electrically insulate the mask polysilicon 106" from the subsequently formed overlying gate polysilicon. In some embodiments, the average thickness of the interpolysilicon oxide layer 108' may be, for example, 90 nm to 170 nm.

According to some embodiments, FIG. 8 shows the portion of the isolation oxide layer 104' exposed to the trench 102 (roughly corresponding to the portion with the surface 104a in FIG. A schematic cross-sectional view of a semiconductor device with the isolation oxide layer 104 ′ on 100 completely removed. In other embodiments, FIG. 8 also shows that after the second removal process described in FIG. Part) a schematic cross-sectional view of a semiconductor device with a thinner thickness T3 (as shown by the dotted line). However, for the sake of simplicity, the dotted line part is omitted in the description below and in relation to FIGS. 9 and 10 .

It should be noted that, as shown in FIG. 8 , according to some embodiments, the top surface of the interpolysilicon oxide layer 108' is a concave top surface 108S. The concave top surface 108S has a profile P2. In some embodiments, the profile P2 can be regarded as having a concave curve, and a portion close to the sidewall of the trench 102 presents an upwardly curved arc. As shown in FIG. 8, in some embodiments, the profile P2 of the concave top surface 108S of the interpolysilicon oxide layer 108' is consistent with the first top surface portion 104S-1, the second top surface portion 104S-1, and the remaining isolation oxide layer 104". Profile P1 formed by portion 104S-2, and top surface 106S of the remaining mask polysilicon 106″ is substantially the same. That is, in some embodiments, profile P2 and profile P1 are substantially the same, and may be considered to have substantially the same concave curve.

In some embodiments, the angle between the concave top surface 108S of the interpoly oxide layer 108 ′ and the sidewalls of the trench 102 may be, for example, 110° to 120°. In some embodiments, the curvature of the concave top surface 108S of the interpolysilicon oxide layer 108 ′ may be, for example, 0.045 to 0.055 nm ⁻¹ . In some embodiments, the curvature of the concave top surface 108S is the curvature of the profile P2. In some embodiments, the curvature of profile P2 is approximately equal to the curvature of profile P1. In some embodiments, the greater the angle between the concave top surface 108S of the interpolysilicon oxide layer 108 ′ and the sidewall of the trench 102 is, the greater the curvature of the concave top surface 108S of the interpolysilicon oxide layer 108 ′ is. The larger the value, the greater the decrease in the gate-drain capacitance (Cgd) of the final semiconductor device.

According to an embodiment, the angle between the concave top surface 108S of the interpolysilicon oxide layer 108 ′ and the sidewall of the trench 102 in the semiconductor device 10 provided by the embodiment of the present invention is 120°, and the interpolysilicon oxide layer 108 When the curvature of the concave top surface 108S of '' (ie the curvature of the profile P2) is 120°, the gate-drain capacitance (Cgd) of the semiconductor device 10 is 2.5E-9 to 3E-9 coulombs.

It is worth mentioning that since the concave top surface 108S of the interpolysilicon oxide layer 108 ′ presents an upwardly curved arc near the sidewall of the trench 102 , it is equivalent to adding an oxide layer (for example, the interpolysilicon oxide layer 108 ' and the remaining isolation oxide layer 104") between the subsequently formed gate polysilicon and the drain, thereby reducing the gate-drain capacitance (Cgd) of the final semiconductor device.

In some embodiments, the remaining isolation oxide layer 104" extends from the highest point of the second top surface portion 104S-2 adjacent to the trench 102 to the lowest point of the first top surface portion 104S-1 adjacent to the mask polysilicon 106". The height difference of the dots may be, for example, 30 nm to 40 nm. In some embodiments, the height difference from the highest point of the concave top surface 108S to the lowest point of the concave top surface 108S of the interpolysilicon oxide layer 108' may be, for example, 32 nm to 38 nm.

As shown in FIG. 9, according to some embodiments, a gate oxide layer 110 is formed on the interpolysilicon oxide layer 108'. In some embodiments, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, thermal oxidation process, physical vapor deposition (PVD) process, photolithographic patterning process, etching process, other possible The gate oxide layer 110 is formed by an applied process, or a combination of the foregoing. In some embodiments, the gate oxide layer 110 can be made of silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon hafnium oxide, silicon hafnium oxynitride, tantalum hafnium oxide, titanium hafnium oxide, zirconium oxide Hafnium, other suitable high-k dielectric materials, or combinations thereof.

As shown in FIG. 10 , according to some embodiments, a gate polysilicon 112 is formed on the gate oxide layer 110 . In some embodiments, gate polysilicon 112 may be formed using, for example, chemical vapor deposition (CVD), or other suitable polysilicon deposition techniques. So far, the semiconductor device 10 provided by the embodiment of the present invention is completed.

Next, follow-up steps can be performed according to techniques well known to those skilled in the art, for example, borophosphosilicate glass (BPSG), phosphosilicate An insulating layer such as sodium silicate glass (PSG) or borosilicate glass (BSG) is placed on the semiconductor device 10, and a metal layer is formed. For the purpose of brevity, it is not repeated here.

Another embodiment of the present invention provides a semiconductor device formed by the above-mentioned semiconductor manufacturing method. As shown in FIG. 10, the semiconductor device 10 includes a substrate 100 having a plurality of trenches 102, and an isolation oxide layer 104" is located in the trenches 102. The material of the substrate 100 can refer to the aforementioned relevant paragraphs, and will not be repeated here. In some In an embodiment, the isolation oxide layer 104 ″ may be conformably formed on the sidewalls and bottom of the trench 102 and on the top surface of the substrate 100 .

In some embodiments, the semiconductor device 10 further includes a mask polysilicon 106 ″. In some embodiments, the mask polysilicon 106 ″ may be formed of undoped polysilicon or in-situ doped polysilicon. In some embodiments, mask polysilicon 106" is located in trench 102 and is partially surrounded by isolation oxide 104".

In some embodiments, a top surface of the isolation oxide layer 104" extends upward from the sidewall 106"S of the mask polysilicon 106" toward the sidewall of the trench 102. In some embodiments, the isolation oxide layer 104" A top surface of has two different curvatures. In some embodiments, the first top surface portion 104S-1 of the isolation oxide layer 104" adjacent to the sidewall 106"S of the mask polysilicon 106" has a first curvature, and the isolation oxide layer 104" is separated from the sides of the trench 102. The wall adjacent second top surface portion 104S- 2 has a second curvature. In some embodiments, the first curvature is greater than the second curvature. In some embodiments, the isolation oxide layer 104" has an uneven (or discontinuous) top surface.

In some embodiments, the isolation oxide layer 104" is adjacent to the first top surface portion 104S-1 of the mask polysilicon 106" and the height difference between the first top surface 106S of the mask polysilicon 106" is less than 50nm. Such a result makes subsequent The process fills the IPO into the trenches 102 without (or substantially without) voids. Since the IPO can be deposited well, the IPO can be better controlled. The formation of layers improves the performance of the final semiconductor device, eg, reduces gate-drain capacitance (Cgd) and suppresses gate-to-source leakage current.

In some embodiments, the isolation oxide layer 104" extends from the highest point of the second top surface portion 104S-2 adjacent to the trench 102 to the lowest point of the first top surface portion 104S-1 adjacent to the mask polysilicon 106". The height difference may be, for example, 30nm to 40nm.

In some embodiments, the semiconductor device 10 further includes an interpolysilicon oxide layer 108'. In some embodiments, the interpoly oxide layer 108' may be, for example, a high density plasma chemical vapor deposition (HDPCVD) oxide. An interpoly oxide 108' overlies the isolation oxide 104" and the mask poly 106". In some embodiments, the interpoly oxide layer 108' completely covers the isolation oxide layer 104" and the mask polysilicon 106" without (or substantially without) voids. The interpoly oxide layer 108' has a concave top surface 108S.

In some embodiments, the profile of the concave top surface 108S of the interpolysilicon oxide layer 108' is consistent with the top surface of the isolation oxide layer 104" (the first top surface portion 104S-1 and the second top surface portion 104S-2) and The profile P1 formed by a top surface 106S of the mask polysilicon 106" is substantially the same.

It should be noted that since the concave top surface 108S of the interpolysilicon oxide layer 108' presents an upward curved arc near the sidewall of the trench 102, it is equivalent to adding an oxide layer (for example, the interpolysilicon oxide layer 108' and the remaining isolation oxide layer 104") between the subsequently formed gate polysilicon and the drain, thereby reducing the gate-drain capacitance (Cgd) of the final semiconductor device. In some embodiments, the polysilicon layer The average thickness of the inter-oxide layer 108' may be, for example, 90 nm to 170 nm.

In some embodiments, the angle between the concave top surface 108S of the interpoly oxide layer 108 ′ and the sidewalls of the trench 102 may be, for example, 110° to 120°. In some embodiments, the curvature of the concave top surface 108S of the interpolysilicon oxide layer 108 ′ may be, for example, 0.045 to 0.055 nm ⁻¹ . In some embodiments, the greater the angle between the concave top surface 108S of the interpolysilicon oxide layer 108 ′ and the sidewall of the trench 102 is, the greater the curvature of the concave top surface 108S of the interpolysilicon oxide layer 108 ′ is. The larger the value, the greater the decrease in the gate-drain capacitance (Cgd) of the final semiconductor device.

In some embodiments, the semiconductor device 10 further includes a gate oxide layer 110 on the interpolysilicon oxide layer 108', and a gate polysilicon 112 on the gate oxide layer 110. The materials of the gate oxide layer 110 and the gate polysilicon 112 can refer to the relevant paragraphs above, so the description will not be repeated here. It can be understood that the semiconductor device 10 may also include other elements not shown in the drawings, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borophosilicate glass (PSG) located above the semiconductor device 10 Structures such as insulating layers such as silicate glass (BSG), and metal layers. Since the above structure is well known to those skilled in the art, for the sake of brevity, it is not repeated here.

The semiconductor device manufacturing method provided by the embodiment of the present invention performs a two-stage etching process on the mask oxide layer and a two-stage removal process on the isolation oxide layer, so as to slow down the damage caused by the trench sidewall and masking process in the past process. The degree of recessing of the isolation oxide formed between the sidewalls of the mask oxide enables the interlayer polysilicon oxide filled in the subsequent process to be well deposited on the mask polysilicon and the isolation oxide layer without creating voids.

The semiconductor device obtained according to the semiconductor device manufacturing method provided by the embodiment of the present invention has the following advantages. Compared with the semiconductor device provided by the past process, the semiconductor device provided by the embodiment of the present invention has a reduced degree of depression caused by the isolation oxide layer between the sidewall of the trench and the sidewall of the mask polysilicon, and the subsequent process fills The interpoly oxide layer (IPO) does not have voids. Therefore, the interpolysilicon oxide layer (IPO) of the semiconductor device according to the embodiment of the present invention can provide a good electrical insulation effect between the gate polysilicon and the mask polysilicon. Moreover, since there are no pores, the inter-polysilicon oxide layer (IPO) can provide a good isolation effect for suppressing leakage current from the gate to the source, thereby improving the performance of the semiconductor device.

In addition, due to the two-stage etching process on the mask oxide and the two-stage removal process on the isolation oxide layer, the isolation oxide layer of the semiconductor device provided by the embodiment of the present invention is formed on the trench sidewall and the mask polysilicon layer. The recessed portion between the side walls has a modified profile. Furthermore, since the outline of the inter-polysilicon oxide layer (IPO) of the semiconductor device provided by the embodiment of the present invention is substantially the same as that of the recessed portion of the isolation oxide layer, the inter-polysilicon oxide layer (IPO) of the semiconductor device provided by the embodiment of the present invention ) has a concave top surface. The concave top surface of the interpolysilicon oxide layer (IPO) presents an upwardly curved arc near the sidewall of the trench, which is equivalent to increasing the thickness of the oxide layer between the gate polysilicon and the drain, thus reducing the semiconductor device. of gate-drain capacitance (Cgd).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (20)

1. a kind of manufacturing method of semiconductor device characterized by comprising

One substrate is provided；

Multiple grooves are formed in the substrate；

A layer of isolation oxide is formed in those grooves and on the substrate；

It deposits in the layer of isolation oxide of a mask polysilicon in those grooves and on the substrate；

One first etching technics is carried out to remove a first part of the mask polysilicon, and expose in those grooves should be every A part of surface from oxide layer；

One first removal technique is carried out to remove a first part of the layer of isolation oxide；

One second etching technics is carried out to remove a second part of the mask polysilicon, and expose in those grooves should be every Another part surface from oxide layer；

One second removal technique is carried out to remove a second part of the layer of isolation oxide；And

A polysilicon interlevel oxide layer is formed on the remaining mask polysilicon and the remaining layer of isolation oxide；

Wherein the polysilicon interlevel oxide layer has a concave upper surface.

2. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that further include:

A grid oxic horizon is formed on the polysilicon interlevel oxide layer；And

A grid polycrystalline silicon is formed on the grid oxic horizon.

3. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that form the polysilicon interlevel oxide layer In including: on the remaining mask polysilicon and the remaining layer of isolation oxide

Oxide is in those grooves and above the substrate between depositing a polysilicon layer；

A third etching technics is carried out to remove a part of oxide between the polysilicon layer, and exposes the side wall of those grooves A part.

4. the manufacturing method of semiconductor device as claimed in claim 3, which is characterized in that oxide is complete between the polysilicon layer Ground covers the isolating oxide layer and the mask polysilicon.

5. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that further include:

Before carrying out the first part of first etching technics to remove the mask polysilicon, which is carried out One chemical-mechanical planarization grinding technics is until exposing the layer of isolation oxide.

6. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that carry out this second remove technique with After the second part for removing the layer of isolation oxide, a top surface of the remaining isolating oxide layer is from the mask polysilicon Side wall up extend to the sidewall direction of the groove.

7. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that carry out this second remove technique with After the second part for removing the layer of isolation oxide, the remaining isolating oxide layer is adjacent with the side wall of the mask polysilicon The first top surface portion have a first curvature, the remaining isolating oxide layer it is adjacent with the side wall of the groove second push up table Face part has a torsion, and wherein the first curvature is greater than the torsion.

8. such as the manufacturing method of semiconductor device according to any one of claims 1 to 7, which is characterized in that the polysilicon layer Between oxide layer the profile of the concave upper surface and the top surface of the remaining isolating oxide layer and the remaining mask polysilicon The profile that is constituted of top surface it is roughly the same.

9. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that the remaining isolating oxide layer is adjacent In the height of a top surface of the minimum point and remaining mask polysilicon of one first top surface portion of the mask polysilicon Difference is less than the isolating oxide layer in the thickness on the substrate.

10. the manufacturing method of semiconductor device as described in claim 1, which is characterized in that the polysilicon interlevel oxide layer Angle between the concave upper surface and the side wall of the groove be 110 ° to 120 ° and/or the polysilicon interlevel oxide layer this is recessed The curvature of shape top surface is 0.045 to 0.055nm^-1。

11. a kind of semiconductor device characterized by comprising

One substrate, including multiple grooves；

One isolating oxide layer is located in those grooves；

One mask polysilicon, surrounds in those grooves and partly by the isolating oxide layer；And

One polysilicon interlevel oxide layer is located on the isolating oxide layer and the mask polysilicon；

Wherein the polysilicon interlevel oxide layer has a concave upper surface.

12. semiconductor device as claimed in claim 11, which is characterized in that further include:

One grid oxic horizon is located on the polysilicon interlevel oxide layer；And

One grid polycrystalline silicon is located on the grid oxic horizon.

13. semiconductor device as claimed in claim 11, which is characterized in that the polysilicon interlevel oxide layer fully covers should Isolating oxide layer and the mask polysilicon.

14. semiconductor device as claimed in claim 11, which is characterized in that a top surface of the isolating oxide layer is from the mask The side wall of polysilicon up extends to the sidewall direction of the groove.

15. semiconductor device as claimed in claim 11, which is characterized in that there are two the top surface tools of the isolating oxide layer Different curvature.

16. semiconductor device as claimed in claim 11, which is characterized in that the side of the isolating oxide layer and the mask polysilicon One first adjacent top surface portion of wall have a first curvature, the isolating oxide layer it is adjacent with the side wall of the groove one second Top surface portion has a torsion, and wherein the first curvature is greater than the torsion.

17. the semiconductor device as described in any one of claim 11~16, which is characterized in that the polysilicon interlevel oxide layer The profile of the concave upper surface and the top surface of the isolating oxide layer and the mask polysilicon the profile that is constituted of top surface It is roughly the same.

18. semiconductor device as claimed in claim 11, which is characterized in that the isolating oxide layer is adjacent to the mask polysilicon One first top surface portion and the mask polysilicon a top surface difference in height be less than 50nm.

19. semiconductor device as claimed in claim 11, which is characterized in that the isolating oxide layer is from being adjacent to the one of the groove The difference in height of minimum point of the highest point of second top surface portion to the first top surface portion for being adjacent to the mask polysilicon is The average thickness of 30nm to 40nm and/or the polysilicon interlevel oxide layer is 90nm to 170nm.

20. semiconductor device as claimed in claim 11, which is characterized in that the spill top table of the polysilicon interlevel oxide layer Angle between face and the side wall of the groove is 110 ° to 120 ° and/or the concave upper surface of the polysilicon interlevel oxide layer Curvature is 0.045 to 0.055nm^-1。