CN104112654A - Process method for reducing floating gate holes - Google Patents
Process method for reducing floating gate holes Download PDFInfo
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- CN104112654A CN104112654A CN201310136075.8A CN201310136075A CN104112654A CN 104112654 A CN104112654 A CN 104112654A CN 201310136075 A CN201310136075 A CN 201310136075A CN 104112654 A CN104112654 A CN 104112654A
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- floating boom
- silicon nitride
- nitride layer
- trench isolation
- shallow trench
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 53
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 53
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000002360 preparation method Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 32
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 32
- 239000003989 dielectric material Substances 0.000 claims description 20
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000003795 chemical substances by application Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 241000826860 Trapezium Species 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention provides a process method for reducing floating gate holes. The process method at least comprises the following steps: at first, a liner oxide layer and a silicon nitride layer are deposited successively on an active region of a semiconductor substrate; secondly, the liner oxide layer, the silicon nitride layer and the active region are etched to form at least two inverted trapezoidal trenches, wherein the trenches do not penetrate through the active region; then, the trenches are filled with an insulating medium material to form shallow trench isolation regions; then, the selective etching process is adopted to etch the silicon nitride layer located between the shallow trench isolation regions, and at the same time, partial shallow trench isolation regions are etched to acquire a rectangular or inverted trapezoidal floating gate preparation region; and finally, a floating gate is prepared and formed in the floating gate preparation prepare. Thus, no hole will occur in the floating gate prepared and formed in the rectangular or inverted trapezoidal floating gate preparation region to avoid the floating gate from being failed, so the device reliability can be enhanced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of process that reduces floating boom hole.
Background technology
Flash memory (Flash) is as a kind of main non-effumability memory device, the various portable type electronic products such as USB flash disk driver, MP3 player, digital camera, personal digital assistant, mobile phone and laptop computer are widely used in, wherein, the memory of high storage capacity, low cost and low-power consumption has become the development trend of non-volatility memorizer.NOR type flash device is the one that belongs to nonvolatile flash memory, and at present, what NOR type flash device adopted is autoregistration floating boom technique, its preparation flow as depicted in figs. 1 and 2:
The first step, deposit liner oxide skin(coating) 2A and silicon nitride layer 3A successively on the 1A of the active area of Semiconductor substrate;
Second step, pad oxide layer 2A, silicon nitride layer 3A and active area 1A described in etching, form the groove of multiple inverted trapezoidals;
The 3rd step, fills dielectric material to described groove, forms shallow trench isolation regions 5A;
The 4th step, adopts wet-etching technology, and the silicon nitride layer 3A between the 5A of etching shallow trench isolation regions obtains floating boom district 6A to be prepared;
Finally, form floating boom 7A in the 6A preparation in district to be prepared of described floating boom.
Due in step 2) in described in etching after pad oxide layer 2A, silicon nitride layer 3A and active area 1A, remaining silicon nitride layer 3A is trapezium structure, therefore the silicon nitride layer 3A between the 5A of etching shallow trench isolation regions in step 4), the floating boom district 6A to be prepared obtaining is also trapezium structure, the floating boom district 6A to be prepared of this trapezium structure will cause producing hole among the floating boom 7A of subsequent deposition, make device open circuit even invalid, like this, the reliability of device can be had a strong impact on.
Therefore, providing a kind of process that reduces floating boom hole is that those skilled in the art need to solve problem.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of process that reduces floating boom hole, for solving pertusate problem in floating boom prepared by prior art.
For achieving the above object and other relevant objects, the invention provides a kind of process that reduces floating boom hole,
1) deposit liner oxide skin(coating) and silicon nitride layer successively on the active area of Semiconductor substrate;
2) pad oxide layer, silicon nitride layer and active area described in etching, the groove of at least two inverted trapezoidals of formation, described groove does not penetrate active area;
3) fill dielectric material to described groove, form shallow trench isolation regions;
4) adopt selective etch technique, etch away the silicon nitride layer between shallow trench isolation regions, eating away part shallow trench isolation regions in the same time, the floating boom district to be prepared of acquisition rectangle or inverted trapezoidal;
5) in described floating boom district to be prepared, preparation forms floating boom.
Preferably, adopt high-density plasma deposition process preparation to form shallow trench isolation regions in described step 3), the dielectric material that is filled to described groove is silicon dioxide.
Preferably, in described step 3), form shallow trench isolation regions and also comprise the step that adopts CMP (Chemical Mechanical Polishing) process to make described shallow trench isolation regions flattening surface afterwards.
Preferably, what in described step 4), adopt is selective wet etching technique, and etching agent is the mixed solution of hydrofluoric acid and phosphoric acid, wherein, and the dielectric material of described hydrofluoric acid lateral etching shallow trench isolation regions, the longitudinal etch silicon nitride layer of described phosphoric acid.
Preferably, the dose ratio scope of hydrofluoric acid and phosphoric acid is 1:1～1:100.
Preferably, the speed of hydrofluoric acid lateral etching shallow trench isolation regions dielectric material equals b:a with the ratio of the speed of the longitudinal etch silicon nitride layer of phosphoric acid, wherein, b is silicon nitride layer sidewall projected length in the horizontal direction, a is the thickness of silicon nitride layer, the floating boom district to be prepared obtaining is rectangle, and the scope of described b:a is 1:2～1:4.
Preferably, the speed of hydrofluoric acid lateral etching shallow trench isolation regions dielectric material is greater than b:a with the ratio of the speed of the longitudinal etch silicon nitride layer of phosphoric acid, wherein, b is silicon nitride layer sidewall projected length in the horizontal direction, a is the thickness of silicon nitride layer, the floating boom district to be prepared obtaining is inverted trapezoidal, and the scope of described b:a is 1:2～1:4.
Preferably, described floating boom is polysilicon gate, amorphous silicon grid or metal gates.
As mentioned above, the process of minimizing floating boom hole of the present invention, has following beneficial effect: by selective etch technique, and the silicon nitride layer between etching shallow trench isolation regions, eating away part shallow trench isolation regions in the same time, the floating boom district to be prepared of acquisition rectangle or inverted trapezoidal.Like this, prepare at the floating boom of rectangle or inverted trapezoidal the phenomenon that just there will not be hole in the floating boom of preparing formation in district, the reliability of device is enhanced.
Brief description of the drawings
Fig. 1 is that in prior art, to prepare floating boom be trapezoidal structural representation.
Fig. 2 is the Structure and Process schematic diagram that in prior art, etch silicon nitride floor obtains trapezoidal floating boom district to be prepared.
The floating boom that prepare for the present invention Fig. 3～6 is rectangular structure preparation flow figure.
Fig. 7 is the Structure and Process schematic diagram that etch silicon nitride floor of the present invention obtains rectangle floating boom district to be prepared.
Fig. 8 is the structural representation that floating boom of the present invention district to be prepared is inverted trapezoidal.
Element numbers explanation
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
The invention provides a kind of process that reduces floating boom cavity, this process at least comprises the following steps:
(1) deposit liner oxide skin(coating) 2 and silicon nitride layer 3 successively on the active area of Semiconductor substrate (Active Area, AA) 1, as shown in Figure 3.
Described Semiconductor substrate can be that monocrystalline, polycrystalline are crossed the non-silicon through structure or SiGe, can be also silicon-on-insulator SOI.In the present embodiment, described Semiconductor substrate is silicon substrate.In Semiconductor substrate, by doping process, for example ion implantation technology, is formed with source region 1.
Adopt chemical vapour deposition (CVD) or high-temperature thermal oxidation method on the active area 1 of Semiconductor substrate, to form pad oxide layer 2 and silicon nitride layer 3, certainly, also can deposit by other applicable technique.In the present embodiment, adopt the method preparation of chemical vapour deposition (CVD) to form described pad oxide layer 2 and silicon nitride layer 3, the silicon nitride layer 3 of formation covers the surface of described pad oxide layer 2.
Described pad oxide layer 2 includes, but are not limited to as silicon dioxide.
(2) pad oxide layer 2, silicon nitride layer 3 and active area 1 described in etching, the groove 4 of at least two inverted trapezoidals of formation, described groove 4 does not penetrate active area 1.
As shown in Figure 3, described etching technics can make to utilize method well known to those skilled in the art to be carried out, for example utilize plasma etching or reactive ion etching process, can be on silicon nitride layer 3 before etching spin coating photoresist layer (diagram), patterning photoresist layer afterwards, formation has the mask pattern of opening, utilize mask pattern in described pad oxide layer 2, silicon nitride layer 3 and active area 1, to etch groove 4 as mask, this groove 4 is inverted trapezoidal shape, and sidewall has certain gradient.After the groove of formation inverted trapezoidal, wash photoresist layer.
(3) fill dielectric material to described groove 4, form shallow trench isolation regions 5.
The described dielectric material that is filled to described groove 4 is silicon dioxide, but is not limited to this, also can be other insulating material.
Conventionally adopt high density plasma deposition mode to fill dielectric material to groove 4, certainly, also can adopt additive method, such as low-pressure chemical vapor deposition (LPCVD) or enhancing plasma activated chemical vapour deposition (PECVD) etc.After depositing operation completes, described dielectric material covers the surface of sidewall and bottom and the described silicon nitride layer 3 of described groove 4.Further, adopt CMP (Chemical Mechanical Polishing) process to throw and remove the dielectric on silicon nitride layer 3 surfaces until expose the top of shallow trench isolation regions 5, and make described shallow trench isolation regions 5 flattening surfaces, the shallow trench isolation regions 5 of formation as shown in Figure 4.
(4) adopt selective etch technique, etch away the silicon nitride layer 3 between shallow trench isolation regions 5, eating away part shallow trench isolation regions 5 in the same time, the floating boom district 6 to be prepared of acquisition rectangle or inverted trapezoidal.
Selective etch technique is to utilize two or more etching agents different materials to be carried out respectively to the technique of etching.In the present embodiment, utilize two kinds of etching agents to remove the silicon nitride layer 3 between shallow trench isolation regions 5, remove the dielectric material of part shallow trench isolation regions 5, to form the floating boom district 6 to be prepared of given shape simultaneously.In one embodiment, what adopt is selective wet etching technique, and etching agent is the mixed solution of hydrofluoric acid and phosphoric acid, wherein, the dielectric material of described hydrofluoric acid lateral etching shallow trench isolation regions 5, for optionally removing part shallow trench isolation regions 5; The longitudinal etch silicon nitride layer 3 of described phosphoric acid, for optionally removing silicon nitride layer 3.Preferably, the dose ratio scope of hydrofluoric acid and phosphoric acid is 1:1～1:100.
The shape in the floating boom district 6 to be prepared forming depends on the ratio of speed with the speed of the longitudinal etch silicon nitride floor 3 of phosphoric acid of hydrofluoric acid lateral etching shallow trench isolation regions 5 dielectric materials, if the speed of hydrofluoric acid lateral etching shallow trench isolation regions 5 dielectric materials equals b:a with the ratio of the speed of the longitudinal etch silicon nitride layer 3 of phosphoric acid, wherein, b is silicon nitride layer 3 sidewalls projected lengths in the horizontal direction, a is the thickness of silicon nitride layer 3, the floating boom district 6 to be prepared obtaining is rectangle, as shown in Fig. 5 and Fig. 7; If the speed of hydrofluoric acid lateral etching shallow trench isolation regions 5 dielectric materials is greater than b:a with the ratio of the speed of the longitudinal etch silicon nitride layer 3 of phosphoric acid, wherein, b is silicon nitride layer 3 sidewalls projected lengths in the horizontal direction, a is the thickness of silicon nitride layer 3, the floating boom district 6 to be prepared obtaining is inverted trapezoidal, as shown in Figure 8.Further, the scope of described b:a is 1:2～1:4.In the present embodiment, b:a equals 1:3.
(5) in described floating boom district 6 to be prepared, preparation forms floating boom 7, as shown in Figure 6.
Described floating boom 7 materials can be polysilicon gate, amorphous silicon grid or metal gates.In the present embodiment, described floating boom 7 materials are preferably polysilicon gate.
Due to floating boom district 6 to be prepared be shaped as rectangle or inverted trapezoidal, therefore, can avoid the situation that occurs hole in the floating boom that causes preparation that stops due to shallow trench isolation regions 5 sidewalls.
In sum, the invention provides a kind of process that reduces floating boom hole, by selective etch technique, the silicon nitride layer between etching shallow trench isolation regions, eating away part shallow trench isolation regions in the same time, the floating boom district to be prepared of acquisition rectangle or inverted trapezoidal.Like this, prepare in the floating boom of preparing formation in district and just there will not be hole at the floating boom of rectangle or inverted trapezoidal, avoided floating boom to occur invalid, the reliability of device is enhanced.
So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (8)
1. a process that reduces floating boom hole, is characterized in that, described process at least comprises step:
1) deposit liner oxide skin(coating) and silicon nitride layer successively on the active area of Semiconductor substrate;
2) pad oxide layer, silicon nitride layer and active area described in etching, the groove of at least two inverted trapezoidals of formation, described groove does not penetrate active area;
3) fill dielectric material to described groove, form shallow trench isolation regions;
4) adopt selective etch technique, etch away the silicon nitride layer between shallow trench isolation regions, eating away part shallow trench isolation regions in the same time, the floating boom district to be prepared of acquisition rectangle or inverted trapezoidal;
5) in described floating boom district to be prepared, preparation forms floating boom.
2. the process of minimizing floating boom hole according to claim 1, is characterized in that: in described step 3), adopt high-density plasma deposition process preparation to form shallow trench isolation regions, the dielectric material that is filled to described groove is silicon dioxide.
3. the process of minimizing floating boom hole according to claim 2, is characterized in that: after forming shallow trench isolation regions in described step 3), also comprise the step that adopts CMP (Chemical Mechanical Polishing) process to make described shallow trench isolation regions flattening surface.
4. the process of minimizing floating boom hole according to claim 1, it is characterized in that: what in described step 4), adopt is selective wet etching technique, etching agent is the mixed solution of hydrofluoric acid and phosphoric acid, wherein, the dielectric material of described hydrofluoric acid lateral etching shallow trench isolation regions, the longitudinal etch silicon nitride layer of described phosphoric acid.
5. the process of minimizing floating boom hole according to claim 4, is characterized in that: the dose ratio scope of hydrofluoric acid and phosphoric acid is 1:1～1:100.
6. the process of minimizing floating boom hole according to claim 5, it is characterized in that: the speed of hydrofluoric acid lateral etching shallow trench isolation regions dielectric material equals b:a with the ratio of the speed of the longitudinal etch silicon nitride layer of phosphoric acid, wherein, b is silicon nitride layer sidewall projected length in the horizontal direction, a is the thickness of silicon nitride layer, the floating boom district to be prepared obtaining is rectangle, and the scope of described b:a is 1:2～1:4.
7. the process of minimizing floating boom hole according to claim 5, it is characterized in that: the speed of hydrofluoric acid lateral etching shallow trench isolation regions dielectric material with the ratio of the speed of the longitudinal etch silicon nitride layer of phosphoric acid for being greater than b:a, wherein, b is silicon nitride layer sidewall projected length in the horizontal direction, a is the thickness of silicon nitride layer, the floating boom district to be prepared obtaining is inverted trapezoidal, and the scope of described b:a is 1:2～1:4.
8. the process of minimizing floating boom hole according to claim 1, is characterized in that: described floating boom is polysilicon gate, amorphous silicon grid or metal gates.
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| CN201310136075.8A CN104112654A (en) | 2013-04-18 | 2013-04-18 | Process method for reducing floating gate holes |
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| CN201310136075.8A CN104112654A (en) | 2013-04-18 | 2013-04-18 | Process method for reducing floating gate holes |
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| CN105826270A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of flash |
| CN107863382A (en) * | 2017-11-09 | 2018-03-30 | 上海华力微电子有限公司 | Floating boom, the flush memory device and its manufacture method with the floating boom |
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| CN109616409A (en) * | 2018-12-04 | 2019-04-12 | 武汉新芯集成电路制造有限公司 | A kind of polysilicon deposition method, flash memory and manufacturing method thereof |
| CN110289260A (en) * | 2019-06-21 | 2019-09-27 | 上海华力微电子有限公司 | Manufacturing method, flash memory and the light shield mask plate of flash memory |
| CN110379714A (en) * | 2019-07-15 | 2019-10-25 | 武汉新芯集成电路制造有限公司 | The forming method and semiconductor structure of semiconductor structure |
| CN113690336A (en) * | 2021-09-13 | 2021-11-23 | 武汉新芯集成电路制造有限公司 | Single photon avalanche diode and manufacturing method thereof |
| CN113808930A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
| CN114203545A (en) * | 2020-09-18 | 2022-03-18 | 长鑫存储技术有限公司 | Method of making a semiconductor structure |
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| CN105826270B (en) * | 2015-01-07 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of flash memory |
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| CN110379714B (en) * | 2019-07-15 | 2022-08-05 | 武汉新芯集成电路制造有限公司 | Semiconductor structure forming method and semiconductor structure |
| CN114203545A (en) * | 2020-09-18 | 2022-03-18 | 长鑫存储技术有限公司 | Method of making a semiconductor structure |
| CN114203545B (en) * | 2020-09-18 | 2024-06-07 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN113690336A (en) * | 2021-09-13 | 2021-11-23 | 武汉新芯集成电路制造有限公司 | Single photon avalanche diode and manufacturing method thereof |
| CN113690336B (en) * | 2021-09-13 | 2024-02-27 | 武汉新芯集成电路制造有限公司 | Single photon avalanche diode and manufacturing method thereof |
| CN113808930A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
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