CN113808930A - Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate - Google Patents
Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate Download PDFInfo
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- CN113808930A CN113808930A CN202111092574.2A CN202111092574A CN113808930A CN 113808930 A CN113808930 A CN 113808930A CN 202111092574 A CN202111092574 A CN 202111092574A CN 113808930 A CN113808930 A CN 113808930A
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- 238000007667 floating Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 78
- 238000005530 etching Methods 0.000 claims abstract description 66
- 238000002955 isolation Methods 0.000 claims abstract description 46
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 44
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 38
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000001039 wet etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000011049 filling Methods 0.000 claims abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 24
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 18
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000001035 drying Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
本发明涉及半导体制造技术领域，公开了一种Nor闪存的浮栅制作方法、电路以及其应用，所述方法包括在硅衬底上依次沉积生成二氧化硅层和氮化硅层，刻蚀形成浅沟槽隔离沟道、填充隔离介质、执行两次氮化硅去除的湿法刻蚀操作形成沟槽，去除位于沟槽底部硅衬底上的二氧化硅层，重新沉积形成栅极氧化层、填充多晶硅，并使其表面与所述隔离介质的上表面齐平形成浮栅多晶硅层，本发明能够得到相对垂直的沟槽侧面，便于后续的多晶硅层的填充，从而形成电学性能良好的浮栅存储单元，具有切实意义上的实用价值。
The invention relates to the technical field of semiconductor manufacturing, and discloses a floating gate fabrication method, circuit and application of a Nor flash memory. The method includes sequentially depositing a silicon dioxide layer and a silicon nitride layer on a silicon substrate, and etching to form Shallow trench isolation trench, fill isolation dielectric, perform two wet etching operations of silicon nitride removal to form trench, remove silicon dioxide layer located on the silicon substrate at the bottom of trench, redeposit to form gate oxide layer , Fill polysilicon, and make its surface flush with the upper surface of the isolation medium to form a floating gate polysilicon layer, the invention can obtain relatively vertical trench sides, which is convenient for subsequent filling of the polysilicon layer, thereby forming a floating gate with good electrical performance. The grid storage unit has practical value in a practical sense.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a floating gate manufacturing method of a Nor flash memory, a floating gate circuit and application of the Nor flash memory.
Background
With the development of semiconductor technology, flash memory has been widely used as a non-volatile memory. The floating gate and the tunneling oxide layer are added on the basis of the traditional MOS transistor structure, and the floating gate is used for storing charges, so that the non-volatility of the stored content is realized.
NAND flash and NOR flash are the two most important non-volatile flash technologies on the market today. The NOR flash memory can perform independent read-write operation on each memory cell, provides complete random read function, and can be used for nonvolatile storage of executable programs, while the NAND flash memory cannot provide complete random read function to independently read each memory cell, and memory cell erasure can only operate according to blocks and cannot independently operate according to a single memory cell. Compared to NAND flash memory, NOR flash memory can provide a general purpose type of non-volatile memory, with full random access functionality, available for data storage as well as executable program code storage.
In the existing NOR flash memory floating gate manufacturing process, the inclination angle of the side surface of the trench of the isolation medium formed after removing the silicon nitride is large, and a cavity is easily generated in the subsequent polysilicon filling process, so that the electrical performance of a memory cell is influenced, and improvement is needed.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a floating gate manufacturing method of a Nor flash memory, a circuit and application thereof, and a method for removing silicon nitride by two-step etching is adopted, so that the stability and reliability of a NOR flash memory storage unit are effectively improved.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a method for manufacturing a floating gate of a Nor flash memory comprises the following steps:
sequentially depositing a silicon dioxide layer and a silicon nitride layer on a silicon substrate in sequence;
performing photoetching by adopting a prefabricated storage unit silicon substrate photomask, and etching to form a shallow trench isolation channel;
filling an isolation medium into the shallow trench isolation channel, and enabling the surface of the shallow trench isolation channel to be flush with the silicon nitride layer;
performing wet etching operation of removing silicon nitride twice to form a groove, wherein each operation comprises isolation medium quantitative etching and silicon nitride quantitative etching which are performed in sequence;
removing the silicon dioxide layer on the silicon substrate at the bottom of the groove by wet etching;
depositing silicon dioxide again at the bottom of the groove to form a grid oxide layer;
and filling polysilicon into the trench, and making the surface of the trench flush with the upper surface of the isolation medium to form a floating gate polysilicon layer.
Preferably, the thickness of the silicon dioxide layer is
The thickness of the silicon nitride layer is
The depth of the shallow trench isolation channel is
And forming a shallow trench isolation channel by dry etching, wherein the size of the top of the active region of the flash memory unit remained on the etched silicon substrate is 50-100 nanometers.
Preferably, the isolation medium is silicon dioxide, and the redundant silicon dioxide layer is removed through a chemical mechanical polishing process to enable the surface of the redundant silicon dioxide layer to be flush with the silicon nitride layer.
Preferably, the isolation medium quantitative etching is hydrofluoric acid etching, and the silicon nitride quantitative etching is phosphoric acid etching.
Preferably, when performing the wet etching operation of the first silicon nitride removal, the method adopts
Performing isolation medium quantitative etching by using hydrofluoric acid with silicon dioxide etching amount
Performing silicon nitride quantitative etching by phosphoric acid with silicon nitride etching amount;
when performing the wet etching operation of the second silicon nitride removal, adopting
Performing isolation medium quantitative etching by using hydrofluoric acid with silicon dioxide etching amount
The phosphoric acid of the silicon nitride etching amount performs silicon nitride quantitative etching.
Preferably, the wet etching for removing the silicon dioxide layer on the silicon substrate at the bottom of the trench is specifically adopted
The hydrofluoric acid etching amount of the silicon dioxide etching amount leaves the silicon dioxide layer on the surface of the silicon substrate.
Preferably, the redeposited silicon dioxide forms a gate oxide layer thickness of
The thickness of the floating gate polysilicon layer is
The width is 60-100 nanometers.
The invention also provides a Nor flash memory circuit which comprises the floating gate prepared by the method.
The invention also provides a chip comprising the NOR flash memory circuit.
The invention also provides an electronic device, which comprises the chip.
Compared with the prior art, the invention has the following beneficial effects:
the method can generate the relatively vertical side surface of the groove of the isolation medium, so that the subsequent filling of a polycrystalline silicon layer is facilitated, meanwhile, a grid oxide layer is formed by generating silicon dioxide layers twice, the bottom of the groove can be well matched, so that a floating gate polycrystalline silicon layer with excellent electrical property is obtained, and a Nor flash memory circuit with high stability and reliability is formed.
Further salient features and significant advances with respect to the present invention over the prior art are described in further detail in the examples section.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic structural diagram of a floating gate polysilicon layer manufactured in the present embodiment;
FIG. 2 is a schematic view of a wafer structure for depositing a silicon dioxide layer and a silicon nitride layer;
FIG. 3 is a schematic diagram of a wafer structure after etching to form shallow trench isolation trenches;
FIG. 4 is a schematic view of a wafer structure after being filled with an isolation medium;
FIG. 5 is a schematic view of a wafer structure after a first silicon nitride removal wet etching operation;
FIG. 6 is a schematic view of the wafer structure after the second silicon nitride removal wet etching operation;
FIG. 7 is a schematic view of a wafer structure after etching a silicon dioxide layer remaining on the surface of a silicon substrate;
fig. 8 is a diagram illustrating a wafer structure after forming a gate oxide layer of a NOR flash memory.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that certain names are used throughout the specification and claims to refer to particular components. It will be understood that one of ordinary skill in the art may refer to the same component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. As used in the specification and claims of this application, the terms "comprises" and "comprising" are intended to be open-ended terms that should be interpreted as "including, but not limited to," or "including, but not limited to. The embodiments described in the detailed description are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.
Example 1
As shown in fig. 1 to 8, in the floating gate manufacturing method of Nor flash memory provided in this embodiment, the same steps and parameters as those in the prior art are not described much, and those skilled in the art can select the steps and parameters as needed, and only the content of the innovative design of the invention is described in detail in this embodiment;
the preparation method of this example includes:
referring to fig. 2, a silicon dioxide layer 2 is deposited on a silicon substrate 1, wherein the thickness of the silicon dioxide layer 2 is
Wherein
Is equal to 10-10Rice, one tenth of a nanometer;
the deposition is continued outside the silicon dioxide layer 2 to a thickness of
A silicon nitride layer 3;
referring to fig. 3, photolithography is performed on the wafer using a memory cell silicon substrate mask, where photolithography is a process of removing a specific portion of a thin film on the surface of the wafer through a series of manufacturing steps, after which the wafer surface is left with a micro-patterned structure. Through the photoetching process, the characteristic pattern part is finally reserved on the wafer, and the general photoetching process needs to go through the procedures of cleaning and drying the surface of the silicon wafer, coating a bottom, spin-coating a photoresist, soft drying, aligning exposure, post-drying, developing, hard drying, etching, detecting and the like, and is not described in detail herein;
referring to fig. 3, a shallow trench isolation trench 4(STI) is formed by etching, the depth of the shallow trench isolation trench 4 being
Etching the top size of the flash memory unit active area 9 remained on the silicon substrate 1 to be 50-100 nanometers; here, the etching is dry etching, which mainly refers to exposing the surface of a silicon wafer to plasma generated in a gas state, and the plasma reacts with the silicon wafer (or both) through a window opened in the photoresist, thereby removing exposed surface materials, and has very good directionality, and a nearly vertical etching profile can be obtained, and the dry etching is mainly divided into three types: metal etching, dielectric etching and silicon etching, wherein the dielectric etching is used for etching dielectric materials, such as silicon dioxide, and etching media are needed for manufacturing contact holes and through hole structures, and window etching with high depth-to-width ratio (ratio of depth to width of a window) has certain challenge; silicon etching (including polysilicon) is applied to occasions needing to remove silicon, such as etching polysilicon transistor gates and silicon groove capacitors; the metal etching mainly comprises the steps of removing an aluminum alloy composite layer on a metal layer to manufacture an interconnection line; the dry etching mainly comprises medium etching and silicon etching, and specific etching gas parameters are proportioned as required by people in the field, and are not described in detail;
referring to fig. 4, an isolation medium 5, silicon dioxide, is filled into the shallow trench isolation channel 4, and the surface of the isolation medium is flush with the silicon nitride layer 3, and the excess isolation medium 5 is removed mainly by a chemical mechanical polishing process, so that the surface of the isolation medium is flush with the silicon nitride layer 3;
referring to fig. 5, a wet etching operation of removing silicon nitride is performed twice to form a trench 6, and each operation includes isolation medium quantitative etching and silicon nitride quantitative etching which are performed in sequence;
in this embodiment, the isolation medium is etched by hydrofluoric acid, and the silicon nitride is etched by phosphoric acid, specifically
When the wet etching operation of the first silicon nitride removal is carried out, the method adopts
Performing isolation medium quantitative etching by using hydrofluoric acid with silicon dioxide etching amount
Performing silicon nitride quantitative etching by phosphoric acid with silicon nitride etching amount;
when performing the wet etching operation of the second silicon nitride removal, adopting
Performing isolation medium quantitative etching by using hydrofluoric acid with silicon dioxide etching amount
Phosphoric acid of silicon nitride etching amount performs silicon nitride quantitative etching
Referring to fig. 6, the silicon dioxide layer 2 on the silicon substrate at the bottom of the trench 6 is removed by wet etching, specifically, the wet etching is performed
The hydrofluoric acid with the silicon dioxide etching amount is used for etching the silicon dioxide layer 2 remained on the surface of the silicon substrate 1, and meanwhile, the height of the isolation medium 5 and the width of the groove 6 formed between the isolation medium 5 are also increased;
referring to FIG. 7, the re-deposition is performed at the bottom of the trench 6
Form of silicon dioxideThe gate oxide layer 7 of the NOR flash memory is formed by, for example, high-density plasma chemical vapor deposition (hdp-cvd) silicon oxide to form the gate oxide layer 7;
referring to fig. 8, polysilicon is filled into the trench 6, and the surface of the polysilicon is flush with the upper surface of the isolation medium 5 to form a floating gate polysilicon layer 8, specifically, polysilicon is filled into the trench and the upper surfaces of the polysilicon and the isolation medium 5 are flush with each other by using chemical mechanical polishing to form the floating gate polysilicon layer 8, and the thickness of the formed floating gate polysilicon layer 8 is equal to that of the floating gate polysilicon layer 8
The floating gate polysilicon layer 8 is formed to have a width dimension of 60-100 nm.
Example 2
Referring to fig. 1, the present embodiment provides a memory circuit including a floating gate prepared by the method of embodiment 1.
Example 3
The embodiment provides a chip comprising the Nor flash memory circuit according to embodiment 2.
Example 4
The present embodiment provides an electronic device including the chip according to embodiment 3.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111092574.2A CN113808930A (en) | 2021-09-17 | 2021-09-17 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
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| CN202111092574.2A CN113808930A (en) | 2021-09-17 | 2021-09-17 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
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| WO2015149670A1 (en) * | 2014-04-04 | 2015-10-08 | 武汉新芯集成电路制造有限公司 | Manufacturing method for nor flash memory |
| US20190362982A1 (en) * | 2018-05-23 | 2019-11-28 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Defect relieving method for floating gate, and semiconductor structure |
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2021
- 2021-09-17 CN CN202111092574.2A patent/CN113808930A/en active Pending
Patent Citations (8)
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|---|---|---|---|---|
| JP2004172567A (en) * | 2002-11-18 | 2004-06-17 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device |
| KR20050009513A (en) * | 2003-07-16 | 2005-01-25 | 매그나칩 반도체 유한회사 | Method for manufacturing flash memory cell by using trench method |
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Application publication date: 20211217 |