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WO2024245148A1 - 一种显示基板和显示装置 - Google Patents

一种显示基板和显示装置 Download PDF

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Publication number
WO2024245148A1
WO2024245148A1 PCT/CN2024/095268 CN2024095268W WO2024245148A1 WO 2024245148 A1 WO2024245148 A1 WO 2024245148A1 CN 2024095268 W CN2024095268 W CN 2024095268W WO 2024245148 A1 WO2024245148 A1 WO 2024245148A1
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WO
WIPO (PCT)
Prior art keywords
substrate
light
emitting device
orthographic projection
electrode
Prior art date
Application number
PCT/CN2024/095268
Other languages
English (en)
French (fr)
Inventor
袁长龙
王晓宵
朱莉
冯靖伊
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024245148A1 publication Critical patent/WO2024245148A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, comprising: a substrate and a plurality of rows and columns of pixel driving circuits, a plurality of rows and columns of light-emitting devices, a plurality of data signal lines and a plurality of anode connection lines arranged on the substrate, wherein the substrate comprises: a first driving area, the pixel driving circuit and the data signal line are located in the first driving area, and the light-emitting device and the anode connection line are at least partially located in the first driving area; the pixel driving circuit is connected to the data signal line and the light-emitting device, respectively, the light-emitting device comprises: a first light-emitting device, a second light-emitting device and a third light-emitting device, a plurality of first light-emitting devices and a plurality of second light-emitting devices are alternately arranged along a column direction, a plurality of third light-emitting devices are arranged along a column direction, and the
  • the light-emitting device in the 4a-3th column of the nth row is a first light-emitting device
  • the light-emitting device in the 4a-1th column of the nth row is a second light-emitting device
  • the light-emitting device in the 4a-3th column of the n+1th row is a second light-emitting device
  • the light-emitting device in the 4a-1th column of the n+1th row is a first light-emitting device
  • the light-emitting device in the even-numbered column is a third light-emitting device, 1 ⁇ a ⁇ M/4, 1 ⁇ n ⁇ N-1
  • M is the total number of columns of the light-emitting devices or pixel driving circuits in the first driving area, and is an even number
  • N is the total number of rows of the light-emitting devices or pixel driving circuits in the first driving area
  • the pixel driving circuit of one of the odd-numbered columns or the even-numbered columns is electrically connected to the first electrode of the first light-emitting device or the second light-emitting device through the anode connection line, and the pixel driving circuit of the other of the odd-numbered columns or the even-numbered columns is electrically connected to the first electrode of the third light-emitting device;
  • the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the 2f-1th column on the substrate partially overlaps with the orthographic projection of the area where the pixel driving circuit of the nth row and the 2f+1th column is located on the substrate, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the 2f+1th column on the substrate partially overlaps with the orthographic projection of the area where the pixel driving circuit of the nth row and the 2f-1th column is located on the substrate, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the even-numbered column on the substrate partially overlaps with the orthographic projection of the area where the pixel driving circuit of the nth row and the even-numbered column is located on the substrate, 1 ⁇ f ⁇ M/2, and is an odd number.
  • the pixel driving circuit is provided with an anode connection via hole, and the first electrode of the light emitting device is electrically connected to the pixel driving circuit through the anode connection via hole.
  • the pixel driving circuit includes: a first pixel driving circuit a circuit, a second pixel driving circuit and a third pixel driving circuit, wherein the first pixel driving circuit is configured to drive the first light emitting device to emit light, the second pixel driving circuit is configured to drive the second light emitting device to emit light, and the third pixel driving circuit is configured to drive the third light emitting device to emit light;
  • the pixel driving circuit of the odd-numbered columns is the first pixel driving circuit or the second pixel driving circuit, the pixel driving circuits of adjacent odd-numbered columns are different, and the pixel driving circuit of the even-numbered columns is the third pixel driving circuit;
  • the orthographic projection of the first electrode of at least one first light-emitting device on the substrate partially overlaps with the orthographic projection of the anode connection line connected to the first light-emitting device on the substrate;
  • the orthographic projection of the first electrode of at least one first light-emitting device on the substrate does not overlap with the orthographic projection of the anode connection via hole of the first pixel driving circuit connected to the first light-emitting device on the substrate;
  • the orthographic projection of the first electrode of at least one second light-emitting device on the substrate partially overlaps with the orthographic projection of the anode connection line connected to the second light-emitting device on the substrate;
  • the orthographic projection of the first electrode of at least one second light-emitting device on the substrate does not overlap with the orthographic projection of the anode connection via hole of the second pixel driving circuit connected to the second light-emitting device on the substrate;
  • the orthographic projection of the first electrode of the third light emitting device on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the third pixel driving circuit connected to the third light emitting device on the substrate.
  • the anode connection wire includes: a first anode connection wire and a second anode connection wire;
  • the first anode connection line is electrically connected to part of the first pixel driving circuit and part of the first electrode of the first light-emitting device connected to the first pixel driving circuit, respectively, and the orthographic projection of the first anode connection line on the substrate overlaps with the orthographic projection of the anode connection via hole of the connected first pixel driving circuit on the substrate, and overlaps with the orthographic projection of the first electrode of the connected first light-emitting device on the substrate;
  • the second anode connecting line is electrically connected to part of the second pixel driving circuit and part of the first electrode of the second light-emitting device connected to the second pixel driving circuit, respectively.
  • the orthographic projection of the second anode connecting line on the substrate overlaps with the orthographic projection of the anode connecting via of the connected second pixel driving circuit on the substrate, and overlaps with the orthographic projection of the first electrode of the connected second light-emitting device on the substrate.
  • an orthographic projection of the first anode connecting line on the substrate at least partially overlaps an orthographic projection of the second anode connecting line on the substrate.
  • first anode connection line and the second anode connection line are straight lines, the extension direction of the first anode connection line and the extension direction of the second anode connection line intersect, and the extension direction of the first anode connection line and the extension direction of the second anode connection line are different from the row direction and the column direction;
  • the orthographic projection of the first anode connecting line on the substrate does not overlap with the orthographic projection of the first electrode of the second light-emitting device and the first electrode of the third light-emitting device on the substrate
  • the orthographic projection of the second anode connecting line on the substrate does not overlap with the orthographic projection of the first electrode of the first light-emitting device and the first electrode of the third light-emitting device on the substrate
  • the first anode connecting line and the second anode connecting line are located on the same side of the anode connection via of the third pixel driving circuit.
  • the first anode connection line and the second anode connection line include: a first connection segment and a second connection segment, the first connection segment and the second connection segment located on the same anode connection line are connected, and the first connection segment and the second connection segment are arranged at a right angle, the first connection segment extends in a column direction, and the second connection segment extends in a row direction;
  • the orthographic projection of the first connection segment of the first anode connection line on the substrate overlaps with the orthographic projection of the anode connection via of the first pixel driving circuit and the first electrode of the second light-emitting device on the substrate;
  • the orthographic projection of the second connection segment of the first anode connection line on the substrate overlaps with the orthographic projection of the second connection segment of the second anode connection line, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device on the substrate;
  • the first connection segment of the second anode connection line on the substrate overlaps with the orthographic projection of the first electrode of the first light-emitting device and the first electrode of the second light-emitting device on the substrate;
  • the orthographic projection of the connecting segment on the substrate overlaps with the orthographic projection of the anode connecting via of the second pixel driving circuit and the first electrode of the first light-emitting device on the substrate, and the orthographic projection of the second connecting segment of the second anode connecting wire on
  • the orthographic projections of the first anode connection line and the second anode connection line on the substrate do not overlap with the orthographic projection of the first electrode of the third light emitting device on the substrate, and are located on the same side of the anode connection via hole of the third pixel driving circuit.
  • the first anode connection line includes: a first connection segment, a second connection segment, and a third connection segment, the first connection segment and the third connection segment extend in a column direction, the second connection segment extends in a row direction, the first connection segment and the third connection segment are located on the same side of the second connection segment, and are electrically connected to the second connection segment respectively, and the second anode connection line includes: a fourth connection segment and a fifth connection segment, the fourth connection segment and the fifth connection segment are connected and arranged at a right angle, the fourth connection segment extends in a column direction, and the fifth connection segment extends in a row direction;
  • the orthographic projection of the first connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the first pixel driving circuit on the substrate, the orthographic projection of the second connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the first electrode of the third light-emitting device on the substrate, the orthographic projection of the third connection segment of the first anode connection line on the substrate partially overlaps with the first electrode of the first light-emitting device and the orthographic projection of the fifth connection segment of the second anode connection line on the substrate, the orthographic projection of the fourth connection segment of the second anode connection line on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the second pixel driving circuit and the first electrode of the first light-emitting device on the substrate, and the orthographic projection of the fifth connection segment of the second anode connection line on the substrate partially overlaps with the first electrode of the first light-emitting device and the first electrode of the second
  • the orthographic projection of the second anode connection line on the substrate does not overlap with the orthographic projection of the first electrode of the third light-emitting device on the substrate, and the first anode connection line and the second anode connection line are respectively located on different sides of the anode connection via hole of the third pixel driving circuit.
  • the second anode connection line includes: a first connection segment, a second connection segment, and a third connection segment, the first connection segment and the third connection segment extend in a column direction, the second connection segment extends in a row direction, the first connection segment and the third connection segment are located on the same side of the second connection segment, and are electrically connected to the second connection segment respectively,
  • the first anode connection line includes: a fourth connection segment and a fifth connection segment, the fourth connection segment and the fifth connection segment are connected and arranged at a right angle, the fourth connection segment extends in a column direction, and the fifth connection segment extends in a row direction;
  • the orthographic projection of the fourth connection segment of the first anode connection line on the substrate overlaps with the orthographic projection of the anode connection via hole of the first pixel driving circuit and the first electrode of the second light-emitting device on the substrate
  • the orthographic projection of the fifth connection segment of the first anode connection line on the substrate overlaps with the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, and the orthographic projection of the third connection segment of the second anode connection line on the substrate
  • the orthographic projection of the first connection segment of the second anode connection line on the substrate overlaps with the orthographic projection of the anode connection via hole of the second pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment of the second anode connection line on the substrate overlaps with the orthographic projection of the first electrode of the third light-emitting device on the substrate
  • the orthographic projection of the third connection segment of the second anode connection line on the substrate overlaps with the orthographic projection of the first
  • the orthographic projection of the first anode connection line on the substrate does not overlap with the orthographic projection of the first electrode of the third light-emitting device on the substrate, and the first anode connection line and the second anode connection line are respectively located on different sides of the anode connection via hole of the third pixel driving circuit.
  • an orthographic projection of the first anode connecting line on the substrate does not overlap with an orthographic projection of the second anode connecting line on the substrate.
  • the first anode connection line and the second anode connection line each include: a first connection The first connecting segment and the third connecting segment extend in a column direction, the second connecting segment extends in a row direction, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment and are electrically connected to the second connecting segment respectively;
  • the orthographic projection of the first connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the first pixel driving circuit on the substrate, the orthographic projection of the second connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the first electrode of the third light-emitting device on the substrate, the orthographic projection of the third connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate, the orthographic projection of the first connection segment of the second anode connection line on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the second pixel driving circuit on the substrate, the orthographic projection of the second connection segment of the second anode connection line on the substrate partially overlaps with the orthographic projection of the first electrode of the third light-emitting device on the substrate, and the orthographic projection of the third connection segment of the second anode connection line on the substrate partially overlaps with
  • the first anode connection line and the second anode connection line are respectively located on the same side of the anode connection via hole of the third pixel driving circuit.
  • the first anode connection line includes: a first connection segment, a second connection segment, and a third connection segment, the first connection segment and the third connection segment extend in a column direction, the second connection segment extends in a row direction, the first connection segment and the third connection segment are located on the same side of the second connection segment, and are electrically connected to the second connection segment respectively, the second anode connection line includes: a fourth connection segment and a fifth connection segment, the fourth connection segment and the fifth connection segment are connected and arranged at an acute angle, and the fourth connection segment extends in a column direction;
  • the orthographic projection of the first connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the first pixel driving circuit on the substrate, the orthographic projection of the second connection segment of the first anode connection line on the substrate partially overlaps or does not overlap with the orthographic projection of the first electrode of the third light-emitting device on the substrate, the orthographic projection of the third connection segment of the first anode connection line on the substrate partially overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate, the orthographic projection of the fourth connection segment of the second anode connection line on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the second pixel driving circuit and the first electrode of the first light-emitting device on the substrate, and the orthographic projection of the fifth connection segment of the second anode connection line on the substrate partially overlaps with the first electrode of the second light-emitting device;
  • the orthographic projection of the second anode connection line on the substrate does not overlap with the orthographic projection of the first electrode of the third light-emitting device on the substrate, and the first anode connection line and the second anode connection line are respectively located on different sides of the anode connection via hole of the third pixel driving circuit.
  • the second anode connection line includes: a first connection segment, a second connection segment, and a third connection segment, the first connection segment and the third connection segment extend in a column direction, the second connection segment extends in a row direction, the first connection segment and the third connection segment are located on the same side of the second connection segment, and are electrically connected to the second connection segment respectively, the first anode connection line includes: a fourth connection segment and a fifth connection segment, the fourth connection segment and the fifth connection segment are connected and arranged at an acute angle, and the fourth connection segment extends in a column direction;
  • the orthographic projection of the fourth connection segment of the first anode connection line on the substrate overlaps with the orthographic projection of the anode connection via of the first pixel driving circuit and the first electrode of the second light-emitting device on the substrate
  • the orthographic projection of the fifth connection segment of the first anode connection line on the substrate overlaps with the orthographic projection of the first electrode of the first light-emitting device on the substrate
  • the orthographic projection of the first connection segment of the second anode connection line on the substrate overlaps with the orthographic projection of the anode connection via of the second pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment of the second anode connection line on the substrate overlaps or does not overlap with the orthographic projection of the first electrode of the third light-emitting device on the substrate
  • the orthographic projection of the third connection segment of the second anode connection line on the substrate overlaps with the orthographic projection of the first electrode of the second light-emitting device on the substrate;
  • the orthographic projection of the first anode connecting line on the substrate does not overlap with the orthographic projection of the first electrode of the third light-emitting device on the substrate, and the first anode connecting line and the second anode connecting line are respectively connected to the anode of the third pixel driving circuit. Connect different sides of the via.
  • the pixel driving circuit in column 4a-3 is a first pixel driving circuit
  • the pixel driving circuit in column 4a-1 is a second pixel driving circuit
  • the orthographic projection of the anode connection via of the pixel driving circuit in the bth row and the dth column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the bth row and the dth column on the substrate, the orthographic projection of the anode connection via of the pixel driving circuit in the cth row and the dth column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the cth row and the dth column on the substrate,
  • the first anode connection line is electrically connected to the first electrode of the pixel driving circuit in the cth row and the 4a-3 column and the light-emitting device in the cth row and the 4a-1 column respectively
  • the second anode connection line is electrically connected to the first electrode of the pixel driving circuit in the cth row and the 4a-1 column and the light-emitting device in the cth row and the 4a-3 column respectively, wherein 1 ⁇ b
  • the area of the first electrode of the first light emitting device in the odd rows is larger than that of the first electrode of the first light emitting device in the even rows
  • the area of the first electrode of the second light emitting device in the odd rows is larger than that of the first electrode of the second light emitting device in the even rows.
  • the pixel driving circuit in column 4a-3 is a second pixel driving circuit, and the pixel driving circuit in column 4a-1 is a first pixel driving circuit;
  • the orthographic projection of the anode connection via of the pixel driving circuit in the cth row and the dth column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the cth row and the dth column on the substrate, the orthographic projection of the anode connection via of the pixel driving circuit in the bth row and the dth column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the bth row and the dth column on the substrate,
  • the first anode connection line is electrically connected to the first electrode of the pixel driving circuit in the bth row and the 4a-1 column and the light-emitting device in the bth row and the 4a-3 column, respectively
  • the second anode connection line is electrically connected to the first electrode of the pixel driving circuit in the bth row and the 4a-3 column and the light-emitting device in the bth row and the 4a-1 column, respectively, wherein 1
  • the area of the first electrode of the first light emitting device located in the even-numbered rows is larger than the area of the first electrode of the first light emitting device located in the odd-numbered rows
  • the area of the first electrode of the second light emitting device located in the even-numbered rows is larger than the area of the first electrode of the second light emitting device located in the odd-numbered rows.
  • the substrate further includes: a second driving area
  • the first driving area includes: a first side and a second side arranged opposite to each other, the second driving area is located on at least one of the first side and the second side of the first driving area, and the second driving area is further provided with a gate driving circuit and a light-emitting device, and the gate driving circuit is configured to provide a control signal to the pixel driving circuit;
  • At least one first anode connection line is electrically connected to a first pixel driving circuit located in the first driving area and a first electrode of at least one first light-emitting device located in the second driving area
  • at least one second anode connection line is electrically connected to a second pixel driving circuit located in the first driving area and a first electrode of at least one second light-emitting device located in the second driving area.
  • the first anode connecting wire and the second anode connecting wire are arranged in different layers, and when the orthographic projection of the first anode connecting wire on the substrate does not overlap with the orthographic projection of the second anode connecting wire on the substrate, the first anode connecting wire and the second anode connecting wire are arranged in different layers or in the same layer;
  • the first anode connection line includes: a metal line or a transparent conductive line
  • the second anode connection line includes: a metal line or a transparent conductive layer.
  • the display substrate includes: a driving structure layer and a light emitting structure layer disposed on the substrate, the driving structure layer being provided with a pixel driving circuit, a gate driving circuit and a data signal line, and the light emitting structure layer being provided with a pixel driving circuit, a gate driving circuit and a data signal line.
  • the layer is provided with a light-emitting device;
  • the driving structure layer comprises: a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate, and the light-emitting structure layer comprises: a fourth conductive layer, an organic light-emitting layer and a fifth conductive layer;
  • the third conductive layer at least includes: source and drain electrodes of a plurality of transistors and a data signal line;
  • the fourth conductive layer at least includes: a first electrode of the light emitting device
  • the first anode connection line is located in the third conductive layer or the fourth conductive layer, and the second anode connection line is located in the third conductive layer or the fourth conductive layer.
  • the third conductive layer is a single-layer structure or a multi-layer structure
  • the third conductive layer includes: a first sub-conductive layer and a second sub-conductive layer, or the third conductive layer includes: a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, wherein the first sub-conductive layer and the second sub-conductive layer are metal conductive layers, and the third sub-conductive layer includes: a metal conductive layer or a transparent conductive layer;
  • the number of the third sub-conductive layer is at least one;
  • the first anode connecting line and the second anode connecting line are located in at least one film layer of the third conductive layer.
  • the first light emitting device emits light of one color of red or blue
  • the second light emitting device emits light of the other color of red or blue
  • the third light emitting device emits green light.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3A is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG3B is a working timing diagram of the pixel driving circuit provided in FIG3A ;
  • FIG4A is a schematic diagram of an equivalent circuit of another pixel driving circuit
  • FIG4B is a working timing diagram of the pixel driving circuit provided in FIG4A ;
  • FIG5 is a first structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG6 is a second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG7 is a cross-sectional schematic diagram of a display substrate
  • FIG8 is a second cross-sectional schematic diagram of a display substrate
  • FIG9 is a third cross-sectional schematic diagram of a display substrate
  • FIG10 is a fourth cross-sectional schematic diagram of a display substrate
  • FIG. 11 is a cross-sectional schematic diagram of a display substrate.
  • FIG12 is a sixth cross-sectional schematic diagram of a display substrate
  • FIG13 is a cross-sectional schematic diagram showing a seventh substrate
  • FIG14 is a cross-sectional schematic diagram showing a substrate
  • FIG15 is a schematic cross-sectional view showing a substrate 9
  • FIG16 is a schematic cross-sectional view of another display substrate
  • Fig. 17 is a schematic cross-sectional view along the A-A line of Fig. 7;
  • Fig. 18 is a schematic cross-sectional view of Fig. 7 along the B-B direction.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the situation where the components are connected together through an element having some electrical function.
  • element having some kind of electrical function includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • Fig. 1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data signal driver, a scan signal driver and a pixel array
  • the pixel array may include a plurality of scan signal lines (Gate1 to GateN), a plurality of data signal lines (Data1 to DataL) and a plurality of pixel driving circuits Pxij.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the scan signal driver.
  • the data signal driver may generate a data voltage to be provided to the data signal lines Data1, Data2, Data3, ... and DataL using the grayscale value and the control signal received from the timing controller.
  • the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines Data1, Data2, Data3, ... and DataL in units of sub-pixel rows, where L may be a natural number.
  • the scan signal driver may generate a scan signal to be provided to the scan signal lines Gate1, Gate2, Gate3, ... and GateN by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines Gate1 to GateN.
  • the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that a scan start signal provided in the form of an on-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal, and N may be a natural number.
  • Each pixel driving circuit Pxij may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of circuit units P and a plurality of light-emitting units arranged in a matrix manner
  • the circuit unit includes: a pixel driving circuit, at least one of the plurality of light-emitting units includes a first light-emitting device emitting a first color light, a second light-emitting device emitting a second color light, and a third light-emitting device emitting a third color light
  • the pixel driving circuit is respectively connected to the scanning signal line and the data signal line
  • the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line, and output a corresponding current to the connected light-emitting device.
  • the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the first light emitting device may emit red light
  • the second light emitting device may emit blue light
  • the third light emitting device may emit green light
  • one light emitting unit may include four light emitting devices, and the four light emitting devices may be one first light emitting device, one second light emitting device, and two third light emitting devices.
  • the arrangement can be horizontally parallel, vertically parallel or in a square, etc., which is not limited in the present disclosure.
  • FIG2 is an example of four light emitting devices arranged in a square. The arrangement of the four light emitting devices in FIG2 is called a Bayer arrangement.
  • the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
  • OLED organic light emitting diode
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all light-emitting devices may be a common layer connected together
  • the electron injection layers of all light-emitting devices may be a common layer connected together
  • the hole transport layers of all light-emitting devices may be a common layer connected together
  • the electron transport layers of all light-emitting devices may be a common layer connected together
  • the hole blocking layers of all light-emitting devices may be a common layer connected together
  • the light-emitting layers of adjacent light-emitting devices may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent light-emitting devices may have a small amount of overlap, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
  • FIG3A is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (first transistor M1 to seventh transistor M7), 1 capacitor C and 8 signal lines (data signal line Data, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD and low level power line VSS).
  • a first electrode of the capacitor C is connected to a high-level power supply line VDD, and a second electrode of the capacitor C is connected to a first node N1.
  • a control electrode of the first transistor M1 is connected to a reset signal line Reset, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a first node N1;
  • a control electrode of the second transistor M2 is connected to a scan signal line Gate, a first electrode of the second transistor M2 is connected to a first node N1, and a second electrode of the second transistor M2 is connected to a second node N2.
  • a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3.
  • a control electrode of the fourth transistor M4 is connected to a scan signal line GATE, a first electrode of the fourth transistor M4 is connected to a data signal line Data, and a second electrode of the fourth transistor M4 is connected to a second node N2.
  • the control electrode of the fifth transistor M5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the high level power line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2; the control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L.
  • the control electrode of the seventh transistor M7 is connected to the reset signal line Reset or the scanning signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device is connected to the low level power line VSS.
  • FIG. 3A is described by taking the control electrode of the seventh transistor M7 and the reset signal line Reset as an example.
  • the signal of the high-level power line VDD is a continuously provided high-level signal
  • the signal of the low-level power line VSS is a low-level signal
  • transistors can be divided into N-type transistors and P-type transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage. (eg, 0V, -5V, -10V, or other suitable voltage).
  • the first transistor M1 to the seventh transistor M7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor M1 to the seventh transistor M7 may include a P-type transistor and an N-type transistor.
  • the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the first transistor T1 and the second transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors.
  • the first transistor M1 to the seventh transistor M7 may be P-type transistors.
  • FIG3B is a timing diagram of the operation of the pixel driving circuit provided in FIG3A, and FIG3B is illustrated by taking the transistors in FIG3A as an example that all are P-type transistors.
  • the following is an exemplary embodiment of the present disclosure described by the operation process of the pixel driving circuit illustrated in FIG3B.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are both high-level signals, and the signal of the reset signal line Reset is a low-level signal.
  • the signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the first node N1, the capacitor C is initialized, and the original data voltage in the capacitor C is cleared, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light-emitting device L, the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, and the light-emitting device L does not emit light in this stage.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the scanning signal line Gate is a low-level signal
  • the signals of the light-emitting signal line EM and the reset signal line Reset are high-level signals
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the scanning signal line Gate is a low-level signal, the second transistor T2 and the fourth transistor M4 are turned on, and the second transistor M2 and the fourth transistor M4 are turned on so that the data voltage output by the data signal line Data passes through the second node N, the turned-on third transistor M3, the third node N3 and the turned-on second transistor M2 to provide to the first node N1, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the signal of the reset signal line Reset is a high-level signal, and the first transistor M1 is turned off.
  • the signal of the light emitting signal line EM is a high level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off
  • the third stage A3 is called the light-emitting stage, the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, and the signal of the light-emitting signal line EM is a low-level signal.
  • the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth] 2 K*(Vdd-Vd) 2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply line VDD.
  • FIG4A is a schematic diagram of an equivalent circuit of another pixel driving circuit.
  • the pixel driving circuit may include 8 transistors (first transistor M1 to eighth transistor M8), 1 capacitor C and 9 signal lines (data signal line Data, control signal line Scan, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD and low level power line VSS).
  • the pixel driving circuit provided in FIG. 4A is suitable for use in an LTPO display substrate.
  • a first electrode of the capacitor C is connected to a high-level power supply line VDD, and a second electrode of the capacitor C is connected to a first node N1.
  • a control electrode of the first transistor M1 is connected to a reset signal line Reset, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a fourth node N4.
  • a control electrode of the second transistor M2 is connected to a scan signal line Gate, a first electrode of the second transistor M2 is connected to a fourth node N4, and a second electrode of the second transistor M2 is connected to a second node N2.
  • a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3.
  • a control electrode of the fourth transistor M4 is connected to a scan signal line Gate, a first electrode of the fourth transistor M4 is connected to a data signal line Data, and a second electrode of the fourth transistor M4 is connected to a third node N3.
  • a control electrode of the fifth transistor M5 is connected to a light-emitting signal line EM, a first electrode of the fifth transistor M5 is connected to a high-level power supply line VDD, and a second electrode of the fifth transistor M5 is connected to a third node N3.
  • the control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L.
  • the control electrode of the seventh transistor M7 is connected to the reset signal line Reset, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS.
  • the control electrode of the eighth transistor M8 is connected to the control signal line SCAN, the first electrode of the eighth transistor M8 is connected to the first node N1, and the second electrode of the eighth transistor M8 is connected to the fourth node N4.
  • control electrode of the seventh transistor M7 can also be connected to the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS.
  • the signal of the high-level power line VDD is a continuously provided high-level signal
  • the signal of the low-level power line VSS is a low-level signal
  • the eighth transistor M8 is a metal oxide transistor and is an N-type transistor
  • the first to seventh transistors M1 to M7 are low temperature polysilicon transistors and are P-type transistors.
  • the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.
  • FIG4B is a timing diagram of the operation of the pixel driving circuit provided in FIG4A.
  • the following describes an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG4B.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the control signal line Scan, the light emitting signal line EM and the scanning signal line Gate are all high-level signals, and the signal of the reset signal line Reset is a low-level signal.
  • the signal of the reset signal line Reset is a low-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the fourth node N4, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light emitting device L, and the first electrode of the light emitting device L is initialized (reset), for example: the pre-stored voltage inside it is cleared, the initialization is completed, and the light emitting device L is ensured not to emit light.
  • the signal of the control signal line Scan is a high-level signal
  • the eighth transistor M8 is turned on
  • the signal of the fourth node N4 is provided to the first node N1
  • the capacitor C is initialized
  • the original data voltage in the capacitor C is cleared.
  • the signals of the scanning signal line Gate and the light emitting signal line EM are high-level signals
  • the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and in this stage, the light emitting device L does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scanning signal line Gate is a low level signal
  • the signals of the reset signal line Reset, the luminous signal line EM and the control signal line Scan are high level signals
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the scanning signal line Gate is a low level signal
  • the second transistor M2 and the fourth transistor M4 are turned on
  • the signal of the control signal line Scan is a high level signal
  • the eighth transistor M8 is turned on.
  • the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned on so that the data voltage output by the data signal line Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4 and the turned-on eighth transistor M8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off.
  • the signal of the luminous signal line EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signals of the control signal line Scan and the light-emitting signal line EM are both low-level signals, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals.
  • the signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off.
  • the control signal line Scan is a low-level signal, the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, and the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned off.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor M5 and the sixth transistor M6 are turned on
  • the power supply voltage output by the high-level power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth]2 K*(Vdd-Vd)2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply terminal VDD.
  • the odd-numbered data signal lines are electrically connected to the pixel driving circuit driving the first light-emitting device and the pixel driving circuit driving the second light-emitting device, so that when the display product displays a red and blue pure color picture, the driver that provides signals to the data signal line will switch between the first color data signal and the second color data signal at a high frequency, resulting in high power consumption of the display product.
  • FIG5 is a schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure
  • FIG6 is a schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure.
  • the display substrate provided in the embodiment of the present disclosure may include: a substrate and a plurality of rows and columns of pixel driving circuits, a plurality of rows and columns of light-emitting devices, a plurality of data signal lines Data and a plurality of anode connection lines arranged on the substrate
  • the pixel driving circuit is connected to the data signal lines and the light-emitting devices respectively
  • the light-emitting devices include: a first light-emitting device L1, a second light-emitting device L2 and a third light-emitting device L3, a plurality of first light-emitting devices L1 and a plurality of second light-emitting devices L2 are arranged alternately along the column direction, a plurality of third light-emitting devices L3 are arranged along the column direction
  • the light emitting device in the 4a-3th column of the nth row is a first light emitting device
  • the light emitting device in the 4a-1th column of the nth row is a second light emitting device
  • the light emitting device in the 4a-3th column of the n+1th row is a second light emitting device
  • the light emitting device in the 4a-1th column of the n+1th row is a first light emitting device
  • the light emitting device in the even-numbered column is a third light emitting device, 1 ⁇ a ⁇ M/4, 1 ⁇ n ⁇ N-1
  • M is the total number of columns of the light emitting devices or pixel driving circuits in the first driving area, and is an even number
  • N is the total number of rows of the light emitting devices or pixel driving circuits in the first driving area.
  • the pixel driving circuit of one of the odd-numbered columns or the even-numbered columns is electrically connected to the first electrode of the first light-emitting device or the second light-emitting device through the anode connection line, and the pixel driving circuit of the other of the odd-numbered columns or the even-numbered columns is electrically connected to the first electrode of the third light-emitting device.
  • the pixel driving circuit of the odd-numbered columns is electrically connected to the first electrode of the first light-emitting device or the second light-emitting device through the anode connection line, and the pixel driving circuit of the other of the even-numbered columns is electrically connected to the first electrode of the third light-emitting device.
  • the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the 2f-1 column on the substrate partially overlaps with the orthographic projection of the region where the pixel driving circuit of the nth row and the 2f+1 column is located on the substrate
  • the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the 2f+1 column on the substrate partially overlaps with the orthographic projection of the region where the pixel driving circuit of the nth row and the 2f-1 column is located on the substrate
  • the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the even column on the substrate partially overlaps with the orthographic projection of the region where the pixel driving circuit of the nth row and the even column is located on the substrate, and 1 ⁇ f ⁇ M/2, which is an odd number.
  • the orthographic projection of the first electrode of the light-emitting device connected to the first row and first column of the pixel driving circuit partially overlaps with the orthographic projection of the area where the first row and third column of the pixel driving circuit is located on the substrate
  • the orthographic projection of the first electrode of the light-emitting device connected to the first row and third column of the pixel driving circuit partially overlaps with the orthographic projection of the area where the first row and first column of the pixel driving circuit is located on the substrate
  • the orthographic projection of the first electrode of the light-emitting device connected to the first row and fifth column of the pixel driving circuit partially overlaps with the orthographic projection of the area where the first row and seventh column of the pixel driving circuit is located on the substrate.
  • the orthographic projections on the substrate partially overlap, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit in the first row and seventh column on the substrate partially overlaps with the orthographic projection of the area where the pixel driving circuit in the first row and fifth column is located on the substrate, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit in the first row and second column on the substrate partially overlaps with the orthographic projection of the area where the pixel driving circuit in the first row and second column is located on the substrate, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit in the first row and fourth column on the substrate partially overlaps with the orthographic projection of the area where the pixel driving circuit in the first row and fourth column is located on the substrate, and so on.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the light emitting device in the 4a-3th column of the odd row is the first light emitting device L1
  • the light emitting device in the 4a-1th column of the odd row is the second light emitting device L2
  • the light emitting device in the 4a-3th column of the even row is the second light emitting device L2
  • the light emitting device in the 4a-1th column of the odd row is the first light emitting device L1
  • the light emitting device in the even column is the third light emitting device L3, 1 ⁇ a ⁇ M/4
  • M is the total number of columns of the light emitting devices, and is an even number.
  • the arrangement of the light-emitting devices in all odd-numbered rows is the same.
  • the light-emitting devices in the first row and the first column, the light-emitting devices in the first row and the fifth column, and the light-emitting devices in the first row and the ninth column are all first light-emitting devices
  • the light-emitting devices in the first row and the third column, the light-emitting devices in the first row and the seventh column, and the light-emitting devices in the first row and the eleventh column are all second light-emitting devices.
  • the arrangement of the light-emitting devices in all even-numbered rows is the same.
  • the light-emitting devices in the first row and the second row and the fifth column, and the light-emitting devices in the second row and the ninth column are all second light-emitting devices
  • the light-emitting devices in the second row and the third column, the light-emitting devices in the second row and the seventh column, and the light-emitting devices in the second row and the eleventh column are all first light-emitting devices.
  • a column of pixel driving circuits may be electrically connected to at least one data signal line.
  • FIGS. 5 and 6 show that a column of pixel driving circuits is electrically connected to one data signal line, and only show the first to eighth data signal lines Data1 to Data8.
  • the pixel driving circuit of one of the odd columns or even columns is electrically connected to the first light emitting device or the second light emitting device through the anode connection line, so that the data signal line connected to the pixel driving circuit of one of the odd columns or even columns only provides the first color data signal or the second color data signal.
  • the data signal line connected to the pixel driving circuit of one of the odd columns or even columns provides the first color data signal
  • the pixel driving circuit of one of the odd columns or even columns is electrically connected to the second light emitting device
  • the data signal line connected to the pixel driving circuit of one of the odd columns or even columns provides the second color data signal.
  • the pixel driving circuit of the other of the odd columns or even columns is electrically connected to the third light emitting device, so that the data signal line connected to the pixel driving circuit of the other of the odd columns or even columns only provides the third color data signal.
  • the display substrate is further electrically connected to a data driver, and the data driver is configured to provide a signal to the data signal line. Since the pixel driving circuit of one of the odd columns or the even columns is electrically connected to the first light emitting device or the second light emitting device through the anode connection line, and the pixel driving circuit of the other of the odd columns or the even columns is electrically connected to the third light emitting device, no matter what picture is displayed on the display substrate, the data signal line continuously provides the same color data signal, that is, the data driver that provides the signal to the data signal line does not need to perform high-frequency switching between different color data signals.
  • the display substrate includes: a substrate and a plurality of rows and columns of pixel driving circuits, a plurality of rows and columns of light-emitting devices, a plurality of data signal lines and a plurality of anode connection lines arranged on the substrate, the substrate includes: a first driving area, the pixel driving circuit and the data signal line are located in the first driving area, the light-emitting device and the anode connection line are at least partially located in the first driving area; the pixel driving circuit is connected to the data signal line and the light-emitting device respectively, the light-emitting device includes: a first light-emitting device, a second light-emitting device and a third light-emitting device, a plurality of first light-emitting devices and a plurality of second light-emitting devices are arranged alternately along the column direction, and a plurality of third light-emitting devices are arranged along the column direction; the light-emitting device includes: a first light-emitting device,
  • the projection overlaps with the orthographic projection of the area where the pixel driving circuit of the nth row and the 2f+1th column is located on the substrate, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the 2f+1th column on the substrate overlaps with the orthographic projection of the area where the pixel driving circuit of the nth row and the 2f-1th column is located on the substrate, the orthographic projection of the first electrode of the light-emitting device connected to the pixel driving circuit of the nth row and the even-numbered column on the substrate overlaps with the orthographic projection of the area where the pixel driving circuit of the nth row and the even-numbered column is located on the substrate, 1 ⁇ f ⁇ M/2, and is an odd number.
  • the present disclosure connects the pixel driving circuit of one of the odd-numbered columns or the even-numbered columns through the anode connecting line
  • the pixel driving circuit of the first light-emitting device or the second light-emitting device is electrically connected to the first electrode of the third light-emitting device
  • the pixel driving circuit of the other one of the odd columns or the even columns is electrically connected to the first electrode of the third light-emitting device.
  • the first light emitting device emits light of one color of red or blue
  • the second light emitting device emits light of the other color of red or blue
  • the third light emitting device emits green light.
  • the pixel driving circuit is provided with an anode connection via hole V, and the first electrode of the light emitting device is electrically connected to the pixel driving circuit through the anode connection via hole.
  • the anode connection hole is configured as a via hole exposing the second electrode of the sixth transistor (also the second electrode of the seventh transistor) in the pixel driving circuit provided in FIG. 3A and FIG. 4A. At least one anode connection line is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) in the pixel driving circuit through the anode connection hole.
  • the display substrate further comprises: a via hole configured to expose the anode connection line.
  • the first electrode of at least one light emitting device is electrically connected to the anode connection line through the via hole.
  • the pixel driving circuit includes: a first pixel driving circuit P1, a second pixel driving circuit P2, and a third pixel driving circuit P3, wherein the first pixel driving circuit P1 is configured to drive the first light emitting device L1 to emit light, the second pixel driving circuit P2 is configured to drive the second light emitting device L2 to emit light, and the third pixel driving circuit P3 is configured to drive the third light emitting device L3 to emit light.
  • the pixel driving circuits in odd columns are the first pixel driving circuit or the second pixel driving circuit, and the pixel driving circuits in even columns are the third pixel driving circuit.
  • the pixel driving circuit in the dth column is one of the first pixel driving circuit and the second pixel driving circuit
  • the pixel driving circuit in the d+2th column is the other of the first pixel driving circuit and the second pixel driving circuit, 1 ⁇ d ⁇ M
  • d is an odd number.
  • the pixel driving circuit in the first column is the first pixel driving circuit
  • the pixel driving circuit in the third column is the second pixel driving circuit
  • the pixel driving circuit in the fifth column is the first pixel driving circuit
  • the pixel driving circuit in the seventh column is the second pixel driving circuit, and so on.
  • the pixel driving circuit in the first column is the second pixel driving circuit
  • the pixel driving circuit in the third column is the first pixel driving circuit
  • the pixel driving circuit in the fifth column is the second pixel driving circuit
  • the pixel driving circuit in the seventh column is the first pixel driving circuit, and so on.
  • the orthographic projection of the first electrode of at least one first light-emitting device L1 on the substrate partially overlaps with the orthographic projection of the anode connection line connected to the first light-emitting device L1 on the substrate, and the orthographic projection of the first electrode of at least one first light-emitting device L1 on the substrate does not overlap with the orthographic projection of the anode connection via V of the first pixel driving circuit P1 connected to the first light-emitting device L1 on the substrate.
  • the orthographic projection of the first electrode of at least one second light-emitting device L2 on the substrate partially overlaps with the orthographic projection of the anode connection line connected to the second light-emitting device L2 on the substrate, and the orthographic projection of the first electrode of at least one second light-emitting device L2 on the substrate does not overlap with the orthographic projection of the anode connection via V of the second pixel driving circuit P2 connected to the second light-emitting device L2 on the substrate.
  • an orthographic projection of the first electrode of the third light emitting device L3 on the substrate partially overlaps an orthographic projection of the anode connection via hole V of the third pixel driving circuit P3 to which the third light emitting device L3 is connected on the substrate.
  • the anode connection line may include a first anode connection line CL1 and a second anode connection line CL2 .
  • the first anode connection line CL1 is electrically connected to a portion of the first pixel driving circuit and a portion of the first electrode of the first light-emitting device connected to the first pixel driving circuit, respectively, and the orthographic projection of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via hole of the connected first pixel driving circuit on the substrate, and The orthographic projection of the first electrode of the connected first light emitting device on the substrate partially overlaps.
  • the second anode connecting line CL2 is electrically connected to a portion of the second pixel driving circuit and a portion of the first electrode of the second light-emitting device connected to the second pixel driving circuit, respectively, and the orthographic projection of the second anode connecting line CL2 on the substrate partially overlaps with the orthographic projection of the anode connecting via of the connected second pixel driving circuit on the substrate, and overlaps with the orthographic projection of the first electrode of the connected second light-emitting device on the substrate.
  • the pixel driving circuit in the 4a-3 column is the first pixel driving circuit P1
  • the pixel driving circuit in the 4a-1 column is the second pixel driving circuit P2.
  • the pixel driving circuit in the first column, the pixel driving circuit in the fifth column, and the pixel driving circuit in the ninth column are sequentially referred to as the first pixel driving circuit P1
  • the pixel driving circuit in the second column, the pixel driving circuit in the fifth column, and the pixel driving circuit in the ninth column are sequentially referred to as the second pixel driving circuit P2.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the b-th row and the d-th column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the b-th row and the d-th column on the substrate, wherein 1 ⁇ b ⁇ N and is an odd number, 1 ⁇ d ⁇ M and d is an odd number, and N is the total number of columns of the pixel driving circuit, that is, the orthographic projection of the anode connection via V of the pixel driving circuit in any odd row and any odd column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in any odd row and any odd column on the substrate.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the first row and the first column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the first row and the first column on the substrate
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the first row and the third column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the first row and the third column on the substrate, and so on.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the cth row and the dth column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the cth row and the dth column on the substrate, wherein 1 ⁇ c ⁇ N, and is an even number, that is, the orthographic projection of the anode connection via V of the pixel driving circuit in any even row and any odd column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in any even row and any odd column on the substrate.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the second row and the first column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the second row and the first column on the substrate
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the second row and the third column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the second row and the third column on the substrate, and so on.
  • the first anode connection line CL1 is electrically connected to the first electrode of the pixel driving circuit of the c-th row, 4a-3 column and the light emitting device of the c-th row, 4a-1 column.
  • the first anode connection line CL1 is electrically connected to the first electrode of the pixel driving circuit of the second row, the first column and the light emitting device of the second row, the third column, the first anode connection line CL1 is electrically connected to the first electrode of the pixel driving circuit of the second row, the fifth column and the light emitting device of the second row, the seventh column, the first anode connection line CL1 is electrically connected to the first electrode of the pixel driving circuit of the second row, the ninth column and the light emitting device of the second row, and so on.
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the c-th row and the 4a-1 column and the light emitting device of the c-th row and the 4a-3 column.
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the second row and the third column and the light emitting device of the second row and the first column
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the second row and the seventh column and the light emitting device of the second row and the fifth column
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the second row and the eleventh column and the light emitting device of the second row and the ninth column, and so on.
  • the area of the first electrode of the first light emitting device in the odd rows is larger than that of the first electrode of the first light emitting device in the even rows
  • the area of the first electrode of the second light emitting device in the odd rows is larger than that of the first electrode of the second light emitting device in the even rows.
  • the first electrode of the first light emitting device located in the odd-numbered rows includes: a first electrode main body portion and a first electrode connecting portion, and the first electrode connecting portion is connected to the pixel driving circuit connected to the first light emitting device.
  • the first electrodes of the rows of first light emitting devices include only a first electrode main body portion.
  • the first electrode of the second light emitting device located in odd rows includes: a second electrode main body and a second electrode connecting portion, the second electrode connecting portion is connected to the pixel driving circuit connected to the second light emitting device.
  • the first electrode of the second light emitting device located in even rows includes only the second electrode main body.
  • the first electrode of the third light emitting device includes a third electrode body part and a third electrode connection part.
  • the pixel driving circuit in the 4a-3 column is the second pixel driving circuit P2, and the pixel driving circuit in the 4a-1 column is the first pixel driving circuit P1.
  • the pixel driving circuit in the first column, the pixel driving circuit in the fifth column, and the pixel driving circuit in the ninth column are sequentially and analogously the second pixel driving circuit P2, and the pixel driving circuit in the second column, the pixel driving circuit in the fifth column, and the pixel driving circuit in the ninth column are sequentially and analogously the first pixel driving circuit P1.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the cth row and the dth column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the cth row and the dth column on the substrate, wherein 1 ⁇ c ⁇ N, and is an even number, 1 ⁇ d ⁇ M, and d is an odd number, and N is the total number of columns of the pixel driving circuit, that is, the orthographic projection of the anode connection via V of the pixel driving circuit in any even row and any odd column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in any even row and any odd column on the substrate.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the second row and the first column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the second row and the first column on the substrate
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the second row and the third column on the substrate partially overlaps with the orthographic projection of the first electrode of the light-emitting device in the second row and the third column on the substrate, and so on.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the b-th row and the d-th column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the b-th row and the d-th column on the substrate, wherein 1 ⁇ b ⁇ N, and is an odd number, that is, the orthographic projection of the anode connection via V of the pixel driving circuit in any odd row and any odd column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in any odd row and any odd column on the substrate.
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the first row and the first column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the first row and the first column on the substrate
  • the orthographic projection of the anode connection via V of the pixel driving circuit in the first row and the third column on the substrate does not overlap with the orthographic projection of the first electrode of the light-emitting device in the first row and the third column on the substrate, and so on.
  • the first anode connection line CL1 is electrically connected to the pixel driving circuit of the b-th row and the 4a-1 column and the first electrode of the light emitting device of the b-th row and the 4a-3 column.
  • the first anode connection line CL1 is electrically connected to the pixel driving circuit of the first row and the third column and the first electrode of the light emitting device of the first row and the first column
  • the first anode connection line CL1 is electrically connected to the pixel driving circuit of the first row and the seventh column and the first electrode of the light emitting device of the first row and the ninth column
  • the first anode connection line CL1 is electrically connected to the pixel driving circuit of the second row and the eleventh column and the first electrode of the light emitting device of the second row and the ninth column, and so on.
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the b-th row and the 4a-3 column and the light emitting device of the b-th row and the 4a-1 column.
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the first row and the first column and the first electrode of the light emitting device of the first row and the third column
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the first row and the fifth column and the first electrode of the light emitting device of the second row and the seventh column
  • the second anode connection line CL2 is electrically connected to the first electrode of the pixel driving circuit of the first row and the ninth column and the first electrode of the light emitting device of the second row and the eleventh column, and so on.
  • the area of the first electrode of the first light emitting device located in the even-numbered rows is larger than the area of the first electrode of the first light emitting device located in the odd-numbered rows
  • the area of the first electrode of the second light emitting device located in the even-numbered rows is larger than the area of the first electrode of the second light emitting device located in the odd-numbered rows.
  • the first electrode of the first light emitting device located in the even-numbered rows includes: a first electrode main body and a first electrode connecting portion, the first electrode connecting portion is connected to the pixel driving circuit connected to the first light emitting device.
  • the first electrode of the first light emitting device located in the odd-numbered rows includes only the first electrode main body.
  • the first electrode of the second light emitting device located in the even-numbered rows includes: a second electrode main body and a second electrode connecting portion, the second electrode connecting portion is connected to the pixel driving circuit connected to the second light emitting device.
  • the first electrode of the second light emitting device located in the odd-numbered rows includes only the second electrode main body.
  • the first electrode of the third light emitting device includes a third electrode body part and a third electrode connection part.
  • the first electrode of the first light-emitting device may further include: at least one first protrusion, and at least one first protrusion is disposed on the first electrode main body.
  • the first electrode of the second light-emitting device may further include: at least one second protrusion, and at least one second protrusion is disposed on the second electrode main body.
  • the first electrode in the third light-emitting device may further include: at least one third protrusion, and at least one third protrusion is disposed on the third electrode main body.
  • the first protrusion, the second protrusion, and the third protrusion are configured to block light.
  • an orthographic projection of the first anode connecting line on the substrate partially overlaps an orthographic projection of at least one of the first protrusion, the second protrusion, and the third protrusion on the substrate.
  • an orthographic projection of the second anode connecting line on the substrate partially overlaps an orthographic projection of at least one of the first protrusion, the second protrusion, and the third protrusion on the substrate.
  • FIG. 7 is a cross-sectional schematic diagram of a display substrate 1
  • FIG. 8 is a cross-sectional schematic diagram of a display substrate 2
  • FIG. 9 is a cross-sectional schematic diagram of a display substrate 3
  • FIG. 10 is a cross-sectional schematic diagram of a display substrate 4.
  • the orthographic projection of the first anode connection line CL1 on the substrate at least partially overlaps with the orthographic projection of the second anode connection line CL2 on the substrate.
  • FIGS. 7 to 9 are illustrated by taking the 4a-3 column pixel driving circuit as the first pixel driving circuit and the 4a-1 column pixel driving circuit as the second pixel driving circuit as an example.
  • CV is a transfer hole that exposes the first anode connection line or the second anode connection line.
  • the first anode connection line CL1 and the second anode connection line CL2 are straight lines, the extension direction of the first anode connection line CL1 and the extension direction of the second anode connection line CL2 intersect, and the extension direction of the first anode connection line CL1 and the extension direction of the second anode connection line CL2 are different from the row direction and the column direction.
  • the orthographic projection of the first anode connecting line CL1 on the substrate does not overlap with the orthographic projection of the first electrode AL2 of the second light-emitting device and the first electrode AL3 of the third light-emitting device on the substrate
  • the orthographic projection of the second anode connecting line CL2 on the substrate does not overlap with the orthographic projection of the first electrode AL1 of the first light-emitting device and the first electrode AL3 of the third light-emitting device on the substrate
  • the first anode connecting line CL1 and the second anode connecting line CL2 are located on the same side of the anode connection via of the third pixel driving circuit.
  • the first anode connecting line CL1 and the second anode connecting line CL2 include: a first connecting segment and a second connecting segment, the first connecting segment and the second connecting segment located on the same anode connecting line are connected, and the first connecting segment and the second connecting segment are arranged at right angles, the first connecting segment extends in the column direction, and the second connecting segment extends in the row direction.
  • the orthographic projection of the first connection segment CL11 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via VV of the first pixel driving circuit P1 and the first electrode AL2 of the second light-emitting device on the substrate, and the orthographic projection of the second connection segment CL12 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the second connection segment CL22 of the second anode connection line CL2, the first electrode AL1 of the first light-emitting device, and the first electrode AL2 of the second light-emitting device on the substrate.
  • the orthographic projection of the first connection segment CL21 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the second pixel driving circuit and the first electrode AL1 of the first light-emitting device on the substrate, and the orthographic projection of the second connection segment CL22 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the first electrode AL1 of the first light-emitting device and the first electrode AL2 of the second light-emitting device on the substrate.
  • the orthographic projections of the first anode connection line CL1 and the second anode connection line CL2 on the substrate do not overlap with the orthographic projection of the first electrode AL3 of the third light emitting device on the substrate and are located on the same side of the anode connection via V of the third pixel driving circuit P3 .
  • the first anode connection line CL1 includes: a first connection segment CL11, a second connection segment CL12 and a third connection segment CL13, the first connection segment CL11 and the third connection segment CL13 extend in the column direction, the second connection segment CL12 extends in the row direction, the first connection segment CL11 and the third connection segment CL13 are located on the same side of the second connection segment CL12, and are electrically connected to the second connection segment CL12 respectively,
  • the second anode connection line CL2 includes: a fourth connection segment CL21 and a fifth connection segment CL22, the fourth connection segment CL21 and the fifth connection segment CL22 are connected and arranged at right angles, the fourth connection segment CL21 extends in the column direction, and the fifth connection segment CL22 extends in the row direction.
  • the orthographic projection of the first connection segment CL11 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the first pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment CL12 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the first electrode AL3 of the third light-emitting device on the substrate
  • the orthographic projection of the third connection segment CL13 of the first anode connection line CL1 on the substrate partially overlaps with the first electrode AL1 of the first light-emitting device and the orthographic projection of the fifth connection segment CL22 of the second anode connection line CL2 on the substrate
  • the orthographic projection of the fourth connection segment CL21 of the second anode connection line CL2 on the substrate partially overlaps with the anode connection via V of the second pixel driving circuit and the orthographic projection of the first electrode AL1 of the first light-emitting device on the substrate
  • the orthographic projection of the second anode connection line CL2 on the substrate does not overlap with the orthographic projection of the first electrode AL3 of the third light emitting device on the substrate, and the first anode connection line CL1 and the second anode connection line CL2 are respectively located on different sides of the anode connection via V of the third pixel driving circuit.
  • the second anode connection line CL2 includes: a first connection segment CL21, a second connection segment CL22 and a third connection segment CL23, the first connection segment CL21 and the third connection segment CL23 extend in the column direction, the second connection segment CL22 extends in the row direction, the first connection segment CL21 and the third connection segment CL23 are located on the same side of the second connection segment CL22, and are electrically connected to the second connection segment CL22 respectively,
  • the first anode connection line CL1 includes: a fourth connection segment CL11 and a fifth connection segment CL12, the fourth connection segment CL11 and the fifth connection segment CL12 are connected and arranged at a right angle, the fourth connection segment CL11 extends in the column direction, and the fifth connection segment CL12 extends in the row direction.
  • the orthographic projection of the fourth connection segment CL11 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the first pixel driving circuit and the first electrode AL2 of the second light-emitting device on the substrate, and the orthographic projection of the fifth connection segment CL12 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the first electrode AL1 of the first light-emitting device, the first electrode AL2 of the second light-emitting device, and the third connection segment CL23 of the second anode connection line CL2 on the substrate.
  • the orthographic projection of the first connection segment CL21 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the second pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment CL22 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the first electrode AL3 of the third light emitting device on the substrate
  • the orthographic projection of the third connection segment CL23 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the first electrode AL2 of the second light emitting device on the substrate
  • the orthographic projection of the first anode connection line CL1 on the substrate does not overlap with the orthographic projection of the first electrode AL3 of the third light emitting device on the substrate, and the first anode connection line CL1 and the second anode connection line CL2 are respectively located on different sides of the anode connection via V of the third pixel driving circuit.
  • FIG. 11 is a cross-sectional schematic diagram of a display substrate five
  • FIG. 12 is a cross-sectional schematic diagram of a display substrate six
  • FIG. 13 is a cross-sectional schematic diagram of a display substrate seven
  • FIG. 14 is a cross-sectional schematic diagram of a display substrate eight
  • FIG. 15 is a cross-sectional schematic diagram of a display substrate nine.
  • the orthographic projection of the first anode connection line CL1 on the substrate does not overlap with the orthographic projection of the second anode connection line CL2 on the substrate.
  • FIGS. 11 to 15 are explained by taking the pixel driving circuit of the 4a-3 column as the first pixel driving circuit and the pixel driving circuit of the 4a-1 column as the second pixel driving circuit as an example.
  • CV is a transfer hole that exposes the first anode connection line or the second anode connection line.
  • the first anode connecting line CL1 and the second anode connecting line CL2 each include: a first connecting segment, a second connecting segment and a third connecting segment, the first connecting segment and the third connecting segment extend along the column direction, the second connecting segment extends along the row direction, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment, and are electrically connected to the second connecting segment respectively.
  • the orthographic projection of the first connection segment CL1 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the first pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment CL12 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the first electrode AL3 of the third light-emitting device on the substrate
  • the orthographic projection of the third connection segment CL13 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the first electrode AL1 of the first light-emitting device on the substrate.
  • the orthographic projection of the first connection segment CL21 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the second pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment CL22 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the first electrode AL3 of the third light emitting device on the substrate
  • the orthographic projection of the third connection segment CL23 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the first electrode AL2 of the second light emitting device on the substrate
  • the first anode connection line CL1 and the second anode connection line CL2 are respectively located at the same side of the anode connection via hole V of the third pixel driving circuit.
  • the first anode connection line CL1 includes: a first connection segment CL11, a second connection segment CL12 and a third connection segment CL13, the first connection segment CL11 and the third connection segment CL13 extend in the column direction, the second connection segment CL12 extends in the row direction, the first connection segment CL11 and the third connection segment CL13 are located on the same side of the second connection segment CL12, and are electrically connected to the second connection segment CL12 respectively,
  • the second anode connection line CL2 includes: a fourth connection segment CL21 and a fifth connection segment CL22, the fourth connection segment CL21 and the fifth connection segment CL22 are connected and arranged at an acute angle, and the fourth connection segment CL21 extends in the column direction.
  • the orthographic projection of the first connection segment CL11 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the first pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment CL12 of the first anode connection line CL1 on the substrate partially overlaps or does not overlap with the orthographic projection of the first electrode AL3 of the third light emitting device on the substrate
  • the orthographic projection on the substrate partially overlaps with the orthographic projection on the substrate of the first electrode AL1 of the first light-emitting device.
  • FIG12 is illustrated by taking the orthographic projection of the second connection segment CL12 of the first anode connection line CL1 on the substrate partially overlapping with the orthographic projection on the substrate of the first electrode AL3 of the third light-emitting device as an example
  • FIG14 is illustrated by taking the orthographic projection of the second connection segment CL12 of the first anode connection line CL1 on the substrate not overlapping with the orthographic projection on the substrate of the first electrode AL3 of the third light-emitting device as an example.
  • the orthographic projection of the fourth connection segment CL21 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the second pixel driving circuit and the first electrode AL1 of the first light-emitting device on the substrate, and the orthographic projection of the fifth connection segment CL22 of the second anode connection line CL2 on the substrate partially overlaps with the first electrode AL2 of the second light-emitting device.
  • the orthographic projection of the second anode connecting line CL2 on the substrate does not overlap with the orthographic projection of the first electrode AL3 of the third light-emitting device on the substrate, and the first anode connecting line CL1 and the second anode connecting line CL2 are respectively located on different sides of the anode connecting via V of the third pixel driving circuit.
  • the second anode connection line CL2 includes: a first connection segment CL21, a second connection segment CL22 and a third connection segment CL23, the first connection segment CL21 and the third connection segment CL23 extend in the column direction, the second connection segment CL22 extends in the row direction, the first connection segment CL21 and the third connection segment CL23 are located on the same side of the second connection segment CL22, and are electrically connected to the second connection segment CL22 respectively,
  • the first anode connection line CL1 includes: a fourth connection segment CL11 and a fifth connection segment CL12, the fourth connection segment CL11 and the fifth connection segment CL12 are connected and arranged at an acute angle, and the fourth connection segment CL11 extends in the column direction.
  • the orthographic projection of the fourth connection segment CL11 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the first pixel driving circuit and the first electrode AL2 of the second light-emitting device on the substrate, and the orthographic projection of the fifth connection segment CL12 of the first anode connection line CL1 on the substrate partially overlaps with the orthographic projection of the first electrode AL1 of the first light-emitting device on the substrate.
  • the orthographic projection of the first connection segment CL21 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the anode connection via V of the second pixel driving circuit on the substrate
  • the orthographic projection of the second connection segment CL22 of the second anode connection line CL2 on the substrate partially overlaps or does not overlap with the orthographic projection of the first electrode AL3 of the third light-emitting device on the substrate
  • the orthographic projection of the third connection segment CL23 of the second anode connection line CL2 on the substrate partially overlaps with the orthographic projection of the first electrode AL2 of the second light-emitting device on the substrate.
  • the orthographic projection of the first anode connecting line CL1 on the substrate does not overlap with the orthographic projection of the first electrode AL3 of the third light-emitting device on the substrate, and the first anode connecting line CL1 and the second anode connecting line CL2 are respectively connected to different sides of the anode via V of the third pixel driving circuit.
  • the light emitting device as in FIGS. 7 to 15 may be located only in the first driving region, or at least in the first driving region.
  • the first driving area may include: a first display area and a second display area, the first display area is at least partially surrounded by the second display area, the second display area may be a light-transmitting display area, and the first display area is a normal display area.
  • the display substrate may be a display substrate provided with an under-screen camera.
  • FIG16 is a cross-sectional schematic diagram of another display substrate.
  • the substrate further includes: a second drive area 200
  • the first drive area 100 includes: a first side and a second side arranged opposite to each other
  • the second drive area 200 is located at least one of the first side and the second side of the first drive area 100
  • the second drive area 200 is also provided with a gate drive circuit and a light-emitting device
  • the gate drive circuit is configured to provide a control signal to the pixel drive circuit.
  • the light-emitting device in the display substrate provided in FIG16 can be arranged on the pixel drive circuit and the gate drive circuit.
  • CV is a transfer hole exposing the first anode connection line or the second anode connection line.
  • At least one first anode connection line CL1 is respectively connected to a first The first pixel driving circuit in the driving area is electrically connected to the first electrode AL1 of at least one first light-emitting device in the second driving area, and at least one second anode connection line CL2 is electrically connected to the second pixel driving circuit in the first driving area and the first electrode AL2 of at least one second light-emitting device in the second driving area.
  • the pixel driving circuit in the display substrate provided in FIG. 16 may include: a display pixel driving circuit and a virtual pixel driving circuit, and the pixel driving circuit electrically connected to the first electrode AL1 of at least one first light emitting device located in the second driving area may be a virtual pixel driving circuit.
  • the first anode connection line CL1 and the second anode connection line CL2 are disposed in different layers.
  • the first anode connection line CL1 and the second anode connection line CL2 are disposed in different layers or in the same layer.
  • the first anode connection line CL1 may include a metal line or a transparent conductive line.
  • the second anode connection line CL2 may include a metal line or a transparent conductive layer.
  • FIG. 17 is a schematic cross-sectional view of FIG. 7 along the A-A direction
  • FIG. 18 is a schematic cross-sectional view of FIG. 7 along the B-B direction.
  • the display substrate includes: a driving structure layer and a light emitting structure layer disposed on a substrate 10, the driving structure layer is provided with a pixel driving circuit, a gate driving circuit and a data signal line, and the light emitting structure layer is provided with a light emitting device.
  • the pixel driving circuit includes: a transistor and a capacitor, and the capacitor includes: a first plate and a second plate.
  • the driving structure layer includes: a first conductive layer 22, a second conductive layer 23 and a third conductive layer 24 sequentially stacked on the substrate 10, and the light emitting structure layer includes: a fourth conductive layer 32, an organic light emitting layer 33 and a fifth conductive layer.
  • the first conductive layer 22 may include at least: gate electrodes of a plurality of transistors, a first plate of a capacitor, and a gate line.
  • the gate line includes: a scan signal line, a reset signal line, and a light emitting signal line; when the pixel driving circuit is as shown in FIG4A , the gate line includes: a scan signal line, a reset signal line, a light emitting signal line, and a control signal line.
  • the second conductive layer 23 may include at least: a second plate of a capacitor.
  • the third conductive layer 24 includes at least source and drain electrodes of a plurality of transistors and a data signal line.
  • the fourth conductive layer 32 includes at least: a first electrode of the light emitting device.
  • FIG. 17 is described by taking the light emitting device as a first light emitting device as an example
  • FIG. 18 is described by taking the light emitting device as a second light emitting device as an example.
  • the light emitting structure layer may further include a pixel definition layer 31 .
  • the first anode connection line CL1 is located in the third conductive layer or the fourth conductive layer.
  • FIG17 is an example in which the first anode connection line CL1 is located in the fourth conductive layer.
  • the second anode connection line CL2 is located in the third conductive layer or the fourth conductive layer.
  • FIG18 is an example in which the second anode connection line CL2 is located in the third conductive layer.
  • the third conductive layer may have a single layer structure or a multi-layer structure.
  • the third conductive layer when the third conductive layer is a multilayer structure, the third conductive layer includes: a first sub-conductive layer and a second sub-conductive layer, or the third conductive layer includes: a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, wherein the first sub-conductive layer and the second sub-conductive layer are metal conductive layers, and the third sub-conductive layer includes: a metal conductive layer or Transparent conductive layer.
  • FIG. 17 and FIG. 18 illustrate an example in which the third conductive layer 24 includes: a first sub-conductive layer 241 , a second sub-conductive layer 242 , and a third sub-conductive layer 243 , and the third sub-conductive layer is a metal conductive layer.
  • the number of the third sub-conductive layer is at least one.
  • the number of the third sub-conductive layer may be one, or may be three.
  • the third conductive layer may include a first metal conductive layer and a second metal conductive layer stacked, or may include: a first metal conductive layer, a second metal conductive layer, a third metal conductive layer stacked, or may include: a first metal conductive layer, a second metal conductive layer, a transparent conductive layer stacked, or may include: a first metal conductive layer, a second metal conductive layer, a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer stacked.
  • the third sub-conductive layer may include a transparent conductive layer; when the display substrate is a display substrate provided with an under-screen camera, the third sub-conductive layer may include: three transparent conductive layers.
  • the first anode connection line CL1 and the second anode connection line CL2 are located in at least one film layer of the third conductive layer.
  • the third conductive layer includes a first metal conductive layer and a second metal conductive layer that are stacked
  • the first anode connection line CL1 can be located in one of the first metal conductive layer and the second metal conductive layer
  • the second anode connection line CL2 can be located in one of the first metal conductive layer and the second metal conductive layer
  • the third conductive layer includes: a first metal conductive layer, a second metal conductive layer, and a third metal conductive layer that are stacked
  • the first anode connection line CL1 can be located in one of the first metal conductive layer, the second metal conductive layer, and the third metal conductive layer
  • the second anode connection line CL2 can be located in one of the first metal conductive layer, the second metal conductive layer, and the third metal conductive layer
  • the third metal conductive layer includes: a first metal conductive layer, a
  • the first anode connection line CL may be made of the same material as the film layer disposed on the same layer, or may be made of a different material than the film layer disposed on the same layer, and the present disclosure does not make any limitation thereto.
  • the first conductive layer, the second conductive layer and the third conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, Ti/Al/Ti, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the fourth conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the fifth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.
  • the transistors in the pixel driving circuit include: a low temperature polysilicon transistor, or may include a low temperature polysilicon transistor and an oxide transistor.
  • FIG. 17 and FIG. 18 illustrate the pixel driving circuit including: a low temperature polysilicon transistor 210 and an oxide transistor 220 as an example.
  • the driving structure layer may further include a semiconductor layer, wherein the semiconductor layer is located on a side of the first conductive layer close to the substrate.
  • the semiconductor layer pattern may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, a double layer, or a multilayer.
  • the semiconductor layer may include at least an active layer of a transistor.
  • the driving structure layer may also include: an insulating layer located between the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer, and a planar layer located on the side of the third conductive layer away from the substrate.
  • the driving structure layer may also include: a first semiconductor layer 21, a second semiconductor layer 25 and a sixth conductive layer 26, the first semiconductor layer 21 is located on the side of the first conductive layer close to the substrate, the second semiconductor layer is located on the side of the second conductive layer away from the substrate, and the sixth conductive layer is located between the second semiconductor layer and the third conductive layer.
  • the first semiconductor layer may include at least an active layer of a low temperature polysilicon transistor.
  • the second semiconductor layer may include at least an active layer of an oxide transistor.
  • the first semiconductor layer pattern may be an amorphous silicon layer or a polycrystalline silicon layer.
  • the second semiconductor layer pattern may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, a double layer, or a multilayer.
  • the gate line connected to the gate electrode of the oxide transistor has a double-layer structure and includes a first sub-gate line and a second sub-gate line.
  • the third conductive layer may include at least a first sub-gate line of a gate line connected to a gate electrode of the oxide transistor.
  • the sixth conductive layer may include at least a second sub-gate line of the gate line connected to the gate electrode of the oxide transistor.
  • the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, Ti/Al/Ti, etc.
  • a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the driving structure layer may also include: an insulating layer located between any two adjacent film layers among the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the sixth conductive layer and the third conductive layer, and a flat layer on the substrate side of the third conductive layer.
  • the third conductive layer when the third conductive layer is a multilayer structure, a flat layer is provided between adjacent film layers in the third conductive layer.
  • the third conductive layer may include a first metal conductive layer and a second metal conductive layer stacked, a flat layer is provided between the first metal conductive layer and the second metal conductive layer.
  • a flat layer is provided between the first metal conductive layer and the second metal conductive layer, and a flat layer is provided between the second metal conductive layer and the third metal conductive layer.
  • the third conductive layer includes: a first metal conductive layer, a second metal conductive layer, and a transparent conductive layer arranged in a stacked manner, a flat layer is provided between the first metal conductive layer and the second metal conductive layer, and a flat layer is provided between the second metal conductive layer and the transparent conductive layer.
  • the third conductive layer includes: a first metal conductive layer, a second metal conductive layer, a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer arranged in a stacked manner, a flat layer is provided between the first metal conductive layer and the second metal conductive layer, a flat layer is provided between the second metal conductive layer and the first transparent conductive layer, a flat layer is provided between the first transparent conductive layer and the second transparent conductive layer, and a flat layer is provided between the second transparent conductive layer and the third transparent conductive layer.
  • the driving structure layer may include: a first insulating layer 11 located between the first semiconductor layer 21 and the first conductive layer 22, a second insulating layer 12 located between the first conductive layer 22 and the second conductive layer 23, a third insulating layer 13 located between the second conductive layer 23 and the second semiconductor layer 25, a sixth insulating layer 14 located between the second semiconductor layer and the sixth conductive layer 26, a fifth insulating layer 15 located between the sixth conductive layer 26 and the first sub-conductive layer 241, a first flat layer 16 located between the first sub-conductive layer 241 and the second sub-conductive layer 242, a second flat layer 17 located between the second sub-conductive layer 242 and the third sub-conductive layer 243, and a third flat layer 18 located on the side of the third sub-conductive layer 243 away from the substrate.
  • the insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • the planar layer may employ an organic material such as resin or the like.
  • the display substrate further includes: an encapsulation structure layer disposed on a side of the light emitting structure layer away from the base.
  • the display substrate may further include other film layers, such as a touch control structure layer, etc., which is not limited in the present disclosure.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display substrate may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiments of the present disclosure are not limited thereto.
  • the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示基板和显示装置，其中，显示基板包括：基底以及设置在基底上的多行多列像素驱动电路、多行多列发光器件、多条数据信号线和多条阳极连接线，基底包括：第一驱动区，像素驱动电路和数据信号线位于第一驱动区，发光器件和阳极连接线至少部分位于第一驱动区；发光器件包括：第一发光器件、第二发光器件和第三发光器件，多个第一发光器件和多个第二发光器件沿列方向交替排布，多个第三发光器件沿列方向排布；第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器的第一电极电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接。

Description

一种显示基板和显示装置
本申请要求于2023年5月26日提交的、申请号为202310612797.X、发明名称为“一种显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：基底以及设置在基底上的多行多列像素驱动电路、多行多列发光器件、多条数据信号线和多条阳极连接线，所述基底包括：第一驱动区，所述像素驱动电路和所述数据信号线位于所述第一驱动区，所述发光器件和所述阳极连接线至少部分位于所述第一驱动区；像素驱动电路分别与数据信号线和发光器件连接，所述发光器件包括：第一发光器件、第二发光器件和第三发光器件，多个第一发光器件和多个第二发光器件沿列方向交替排布，多个第三发光器件沿列方向排布，所述发光器件包括：第一电极；
在所述第一驱动区，第n行第4a-3列发光器件为第一发光器件，第n行第4a-1列发光器件为第二发光器件，第n+1行第4a-3列发光器件为第二发光器件，第n+1行第4a-1列发光器件为第一发光器件，第偶数列发光器件为第三发光器件，1≤a≤M/4，1≤n≤N-1，M为第一驱动区的发光器件或者像素驱动电路的总列数，且为偶数；N为第一驱动区的发光器件或者像素驱动电路的总行数；
第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器的第一电极电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接；
第n行第2f-1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f+1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第2f+1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f-1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第偶数列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第偶数列像素驱动电路所在区域在基底上的正投影部分交叠，1≤f≤M/2，且为奇数。
在示例性实施方式中，所述像素驱动电路设置有阳极连接过孔，所述发光器件的第一电极通过阳极连接过孔与像素驱动电路电连接，所述像素驱动电路包括：第一像素驱动电 路、第二像素驱动电路和第三像素驱动电路，所述第一像素驱动电路被配置为驱动所述第一发光器件发光，所述第二像素驱动电路被配置为驱动所述第二发光器件发光，所述第三像素驱动电路被配置为驱动所述第三发光器件发光；
第奇数列像素驱动电路为第一像素驱动电路或者第二像素驱动电路，相邻奇数列的像素驱动电路不同，第偶数列像素驱动电路为第三像素驱动电路；
至少一个第一发光器件的第一电极在基底上的正投影与第一发光器件所连接的阳极连接线在基底上的正投影部分交叠；
至少一个第一发光器件的第一电极在基底上的正投影与第一发光器件所连接的第一像素驱动电路的阳极连接过孔在基底上的正投影不交叠；
至少一个第二发光器件的第一电极在基底上的正投影与第二发光器件所连接的阳极连接线在基底上的正投影部分交叠；
至少一个第二发光器件第一电极在基底上的正投影与第二发光器件所连接的第二像素驱动电路的阳极连接过孔在基底上的正投影不交叠；
所述第三发光器件的第一电极在基底上的正投影与第三发光器件所连接的第三像素驱动电路的阳极连接过孔在基底上的正投影部分交叠。
在示例性实施方式中，所述阳极连接线包括：第一阳极连接线和第二阳极连接线；
所述第一阳极连接线分别与部分第一像素驱动电路和部分第一像素驱动电路所连接的第一发光器件的第一电极电连接，所述第一阳极连接线在基底上的正投影与所连接的第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，且与所连接的第一发光器件的第一电极在基底上的正投影部分交叠；
所述第二阳极连接线分别与部分第二像素驱动电路和部分第二像素驱动电路所连接的第二发光器件的第一电极电连接，所述第二阳极连接线在基底上的正投影与所连接的第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，且与所连接的第二发光器件的第一电极在基底上的正投影部分交叠。
在示例性实施方式中，所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一阳极连接线和所述第二阳极连接线为直线型，所述第一阳极连接线的延伸方向和所述第二阳极连接线的延伸方向相交，且所述第一阳极连接线的延伸方向和所述第二阳极连接线的延伸方向均不同于行方向和列方向；
所述第一阳极连接线在基底上的正投影与第二发光器件的第一电极和所述第三发光器件的第一电极在基底上的正投影不交叠，所述第二阳极连接线在基底上的正投影与第一发光器件的第一电极和所述第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线位于所述第三像素驱动电路的阳极连接过孔的同一侧。
在示例性实施方式中，所述第一阳极连接线和所述第二阳极连接线包括：第一连接段和第二连接段，位于同一阳极连接线的所述第一连接段和所述第二连接段连接，且所述第一连接段和所述第二连接段呈直角设置，所述第一连接段沿列方向延伸，所述第二连接段沿行方向延伸；
所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔和第二发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与所述第二阳极连接线的第二连接段、第一发光器件的第一电极和第二发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第一连 接段在基底上的正投影与第二像素驱动电路的阳极连接过孔和第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第一发光器件的第一电极和所述第二发光器件的第一电极在基底上的正投影部分交叠；
所述第一阳极连接线和所述第二阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，且位于所述第三像素驱动电路的阳极连接过孔的同一侧。
在示例性实施方式中，所述第一阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第二阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈直角设置，所述第四连接段沿列方向延伸，所述第五连接段沿行方向延伸；
所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第三连接段在基底上的正投影与第一发光器件的第一电极和所述第二阳极连接线的第五连接段在基底上的正投影部分交叠，所述第二阳极连接线的第四连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔和第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第五连接段在基底上的正投影与所述第一发光器件的第一电极和第二发光器件的第一电极部分交叠；
所述第二阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的不同侧。
在示例性实施方式中，所述第二阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第一阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈直角设置，所述第四连接段沿列方向延伸，所述第五连接段沿行方向延伸；
所述第一阳极连接线的第四连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔和第二发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第五连接段在基底上的正投影与第一发光器件的第一电极、第二发光器件的第一电极和第二阳极连接线的第三连接段在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第三连接段在基底上的正投影与第二发光器件的第一电极在基底上的正投影部分交叠；
所述第一阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的不同侧。
在示例性实施方式中，所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影不交叠。
在示例性实施方式中，所述第一阳极连接线和所述第二阳极连接线均包括：第一连接 段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接；
所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第三连接段在基底上的正投影与第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第三连接段在基底上的正投影与第二发光器件的第一电极在基底上的正投影部分交叠；
所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的同一侧。
在示例性实施方式中，所述第一阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第二阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈锐角设置，所述第四连接段沿列方向延伸；
所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠或者不交叠，所述第一阳极连接线的第三连接段在基底上的正投影与第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第四连接段在基底上的正投影与所述第二像素驱动电路的阳极连接过孔和第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第五连接段在基底上的正投影与第二发光器件的第一电极部分交叠；
所述第二阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的不同侧。
在示例性实施方式中，所述第二阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第一阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈锐角设置，所述第四连接段沿列方向延伸；
所述第一阳极连接线的第四连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔和第二发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第五连接段在基底上的正投影与第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠或者不交叠，所述第二阳极连接线的第三连接段在基底上的正投影与第二发光器件的第一电极在基底上的正投影部分交叠；
所述第一阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别所述第三像素驱动电路的阳极 连接过孔的不同侧。
在示例性实施方式中，第4a-3列像素驱动电路为第一像素驱动电路，第4a-1列像素驱动电路为第二像素驱动电路；
第b行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第b行第d列的发光器件的第一电极在基底上的正投影部分交叠，第c行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第c行第d列发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线分别与第c行第4a-3列像素驱动电路和第c行第4a-1列发光器件的第一电极电连接，所述第二阳极连接线通分别与第c行第4a-1列像素驱动电路和第c行第4a-3列发光器件的第一电极电连接，其中，1≤b≤N，且为奇数，1≤c≤N，且为偶数，1≤d≤M，且d为奇数，N为像素驱动电路的总列数。
在示例性实施方式中，位于奇数行的第一发光器件的第一电极的面积大于位于偶数行的第一发光器件的第一电极的面积，位于奇数行的第二发光器件的第一电极的面积大于位于偶数行的第二发光器件的第一电极的面积。
在示例性实施方式中，第4a-3列像素驱动电路为第二像素驱动电路，第4a-1列像素驱动电路为第一像素驱动电路；
第c行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第c行第d列的发光器件的第一电极在基底上的正投影部分交叠，第b行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第b行第d列发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线分别与第b行第4a-1列像素驱动电路和第b行第4a-3列发光器件的第一电极电连接，所述第二阳极连接线分别与第b行第4a-3列像素驱动电路和第b行第4a-1列发光器件的第一电极电连接，其中，1≤b≤N，且为奇数，1≤c≤N，且为偶数，1≤d≤M，且d为奇数，N为像素驱动电路的总列数。
在示例性实施方式中，位于偶数行的第一发光器件的第一电极的面积大于位奇数行的第一发光器件的第一电极的面积，位于偶数行的第二发光器件的第一电极的面积大于位于奇数行的第二发光器件的第一电极的面积。
在示例性实施方式中，所述基底还包括：第二驱动区，所述第一驱动区包括：相对设置的第一侧和第二侧，所述第二驱动区位于所述第一驱动区的第一侧和第二侧中的至少一侧，且所述第二驱动区还设置有栅极驱动电路和发光器件，所述栅极驱动电路被配置为向像素驱动电路提供控制信号；
至少一条第一阳极连接线分别与位于第一驱动区的第一像素驱动电路和位于第二驱动区的至少一个第一发光器件的第一电极电连接，至少一条第二阳极连接线分别与位于第一驱动区的第二像素驱动电路和位于第二驱动区的至少一个第二发光器件的第一电极电连接。
在示例性实施方式中，当所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影部分交叠时，所述第一阳极连接线和所述第二阳极连接线异层设置，当所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影不交叠时，所述第一阳极连接线和所述第二阳极连接线异层设置或者同层设置；
所述第一阳极连接线包括：金属线或者透明导电线，所述第二阳极连接线包括：金属线或者透明导电层。
在示例性实施方式中，所述显示基板包括：设置在所述基底上的驱动结构层和发光结构层，所述驱动结构层设置有像素驱动电路、栅极驱动电路和数据信号线，所述发光结构 层设置有发光器件；所述驱动结构层包括：依次叠设在所述基底上的第一导电层、第二导电层和第三导电层，所述发光结构层包括：第四导电层、有机发光层和第五导电层；
所述第三导电层至少包括：多个晶体管的源漏电极和数据信号线；
所述第四导电层至少包括：发光器件的第一电极；
所述第一阳极连接线位于所述第三导电层或者第四导电层，所述第二阳极连接线位于所述第三导电层或者第四导电层。
在示例性实施方式中，所述第三导电层为单层结构或者多层结构；
当所述第三导电层为多层结构时，所述第三导电层包括：第一子导电层和第二子导电层，或者第三导电层包括：第一子导电层、第二子导电层和第三子导电层，其中，第一子导电层和第二子导电层为金属导电层，第三子导电层包括：金属导电层或者透明导电层；
当所述第三子导电层为透明导电层时，第三子导电层的数量为至少一个；
当所述第三导电层为多层结构时，所述第一阳极连接线和所述第二阳极连接线位于所述第三导电层的至少一个膜层中。
在示例性实施方式中，所述第一发光器件发射红色或者蓝色中的一种颜色的光线，所述第二发光器件发射为红色或者蓝色中的另一种颜色的光线，所述第三发光器件发射绿色光线。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3A为一个像素驱动电路的等效电路示意图；
图3B为图3A提供的像素驱动电路的工作时序图；
图4A为另一像素驱动电路的等效电路示意图；
图4B为图4A提供的像素驱动电路的工作时序图；
图5为本公开实施例提供的显示基板的结构示意图一；
图6为本公开实施例提供的显示基板的结构示意图二；
图7为显示基板的截面示意图一；
图8为显示基板的截面示意图二；
图9为显示基板的截面示意图三；
图10为显示基板的截面示意图四；
图11为显示基板的截面示意图五
图12为显示基板的截面示意图六；
图13为显示基板的截面示意图七；
图14为显示基板的截面示意图八；
图15为显示基板的截面示意图九；
图16为另一显示基板的截面示意图；
图17为图7沿A-A向的截面示意图；
图18为图7沿B-B向的截面示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情 况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(Gate1至GateN)、多个数据信号线(Data1到DataL)和多个像素驱动电路Pxij。
在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线Data1、Data2、Data3、……和DataL的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线Data1、Data2、Data3、……和DataL，L可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线Gate1、Gate2、Gate3、……和GateN的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线Gate1至GateN。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，N可以是自然数。每个像素驱动电路Pxij可以连接到对应的数据信号线和对应的扫描信号线，i和j可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个电路单元P和多个发光单元，电路单元包括：像素驱动电路，多个发光单元的至少一个包括出射第一颜色光线的第一发光器件、出射第二颜色光线的第二发光器件和出射第三颜色光线的第三发光器件，第像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向所连接的发光器件输出相应的电流。发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一发光器件可以出射红色光线，第二发光器件可以是出射蓝色光线，第三发光器件可以出射绿色光线。
在示例性实施方式中，如图2所示，一个发光单元可以包括四个发光器件，四个发光器件可以为一个第一发光器件、一个第二发光器件和两个第三发光器件。四个发光器件可 以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。图2是以四个发光器件正方形方式排列为例进行说明的。图2中的四个发光器件的排列方式称为拜耳排列方式。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一电极(阳极)、有机发光层和第二电极(阴极)。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有发光器件的空穴注入层可以是连接在一起的共通层，所有发光器件的电子注入层可以是连接在一起的共通层，所有发光器件的空穴传输层可以是连接在一起的共通层，所有发光器件的电子传输层可以是连接在一起的共通层，所有发光器件的空穴阻挡层可以是连接在一起的共通层，相邻发光器件的发光层可以有少量的交叠，或者可以是隔离的，相邻发光器件的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。
在示例性实施方式中，图3A为一个像素驱动电路的等效电路示意图。如图3A所示，像素驱动电路可以包括7个晶体管(第一晶体管M1到第七晶体管M7)、1个电容C和8个信号线(数据信号线Data、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、高电平电源线VDD和低电平电源线VSS)。
在示例性实施方式中，如图3A所示，电容C的第一极板与高电平电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管M1的控制极与复位信号线Reset连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第一节点N1连接；第二晶体管M2的控制极与扫描信号线Gate连接，第二晶体管M2的第一极与第一节点N1连接，第二晶体管M2的第二极与第二节点N2连接。第三晶体管M3的控制极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的控制极与扫描信号线GATE连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第二节点N2连接。第五晶体管M5的控制极与发光信号线EM连接，第五晶体管M5的第一极与高电平电源线VDD连接，第五晶体管M5的第二极与第二节点N2连接；第六晶体管M6的控制极与发光信号线EM连接，第六晶体管M6的第一极与第三节点N3连接，第六晶体管M6的第二极与发光器件L的第一极连接。第七晶体管M7的控制极与复位信号线Reset或者扫描信号线Gate连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件的第二极与低电平电源线VSS连接，图3A是以第七晶体管M7的控制极与复位信号线Reset为例进行说明的。
在示例性实施方式中，高电平电源线VDD的信号为持续提供高电平信号，低电平电源线VSS的信号为低电平信号。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压 (例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管M1到第七晶体管M7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施例中，当显示基板为LTPO显示基板时，第一晶体管T1和第二晶体管T2可以为N型晶体管，其余晶体管为P型晶体管。当显示基板为LTPS显示基板时，第一晶体管M1至第七晶体管M7为P型晶体管。
图3B为图3A提供的像素驱动电路的工作时序图，图3B是以图3A中的晶体管均为P型晶体管为例进行说明的。下面通过图3B示例的像素驱动电路的工作过程说明本公开示例性实施例。在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，扫描信号线Gate和发光信号线EM的信号均为高电平信号，复位信号线Reset的信号为低电平信号。复位信号线Reset的信号为高电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压,第七晶体管M7导通，第二初始信号线INIT2的初始电压提供至发光器件L的第一极，对发光器件L的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化。扫描信号线Gate和发光信号线EM的信号为高电平信号，第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6断开，此阶段发光器件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate为低电平信号，发光信号线EM和和复位信号线Reset的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。扫描信号线Gate的信号为低电平信号，第二晶体管T2和第四晶体管M4导通，第二晶体管M2和第四晶体管M4导通使得数据信号线Data输出的数据电压经过第二节点N、导通的第三晶体管M3、2第三节点N3和导通的第二晶体管M2提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压，确保发光器件L不发光。复位信号线Reset的信号为高电平信号，第一晶体管M1断开。发光信号线EM的信号为高电平信号，第五晶体管M5和第六晶体管M6断开。
第三阶段A3、称为发光阶段，扫描信号线Gate和复位信号线Reset的信号为高电平信号，发光信号线EM的信号为低电平信号。发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的控制极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源线VDD输出的电源电压。
在示例性实施方式中，图4A为另一像素驱动电路的等效电路示意图。如图4A所示，像素驱动电路可以包括8个晶体管(第一晶体管M1到第八晶体管M8)、1个电容C和9个信号线(数据信号线Data、控制信号线Scan、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、高电平电源线VDD和低电平电源线VSS)。
在示例性实施方式中，图4A提供的像素驱动电路适用于LTPO显示基板中。
在示例性实施方式中，电容C的第一极板与高电平电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管M1的控制极与复位信号线Reset连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第四节点N4连接。第二晶体管M2的控制极与扫描信号线Gate连接，第二晶体管M2的第一极与第四节点N4连接，第二晶体管M2的第二极与第二节点N2连接。第三晶体管M3的控制极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的控制极与扫描信号线Gate连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第三节点N3连接。第五晶体管M5的控制极与发光信号线EM连接，第五晶体管M5的第一极与高电平电源线VDD连接，第五晶体管M5的第二极与第三节点N3连接。第六晶体管M6的控制极与发光信号线EM连接，第六晶体管M6的第一极与第二节点N2连接，第六晶体管M6的第二极与发光器件L的第一极连接。第七晶体管M7的控制极与复位信号线Reset连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件L的第二极与低电平电源线VSS连接。第八晶体管M8的控制极与控制信号线SCAN连接，第八晶体管M8的第一极与第一节点N1连接，第八晶体管M8的第二极与第四节点N4连接。
在示例性实施方式中，第七晶体管M7的控制极还可以与扫描信号线Gate连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件L的第二极与低电平电源线VSS连接。
在示例性实施方式中，高电平电源线VDD的信号为持续提供高电平信号，低电平电源线VSS的信号为低电平信号。
在示例性实施方式中，第八晶体管M8为金属氧化物晶体管，且为N型晶体管，第一晶体管M1至第七晶体管M7为低温多晶硅晶体管，且为P型晶体管。
在示例性实施方式中，第八晶体管M8为氧化物晶体管可以减少漏电流，提升像素驱动电路的性能，可以降低像素驱动电路的功耗。
图4B为图4A提供的像素驱动电路的工作时序图。下面通过图4B示例的像素驱动电路的工作过程说明本公开示例性实施例。像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，控制信号线Scan、发光信号线EM和扫描信号线Gate的信号均为高电平信号，复位信号线Reset的信号为低电平信号。复位信号线Reset的信号为低电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号提供至第四节点N4，第七晶体管M7导通，第二初始信号线INIT2的初始电压提供至发光器件L的第一极，对发光器件L的第一极进行初始化(复位)，例如：清空其内部的预存电压，完成初始化，确保发光器件L不发光。控制信号线Scan的信号为高电平信号，第八晶体管M8导通，第四节点N4的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压。扫描信号线Gate和发光信号线EM的信号为高电平信号，第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6第七晶体管M7截止，此阶段，发光器件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为低电平信号，复位信号线Reset、发光信号线EM和控制信号线Scan的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。扫描信号线Gate的信号为低电平信号，第二晶体管M2和第四晶体管M4导通，控制信号线Scan的信号为高电平信号，第八晶体管M8导通。第二晶体管M2、第四晶体管M4和第八晶体管M8导通使得数据信号线Data输出的数据电压经过第三节点N3、导通的第三晶体管M3、第二节点N2、导通的第二晶体管M2、第四节点N4和导通的第八晶体管M8提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压。复位信号线Reset的信号为低电平信号，第一晶体管M1和第七晶体管M7断开。发光信号线EM的信号为高电平信号，第五晶体管M5和第六晶体管M6断开。
第三阶段A3、称为发光阶段，控制信号线Scan和发光信号线EM的信号均为低电平信号，扫描信号线Gate和复位信号线Reset的信号为高电平信号。复位信号线Reset的信号为低电平信号，第一晶体管M1和第七晶体管M7截止。控制信号线Scan为低电平信号、扫描信号线Gate和复位信号线Reset的信号为高电平信号，第二晶体管M2、第四晶体管M4和第八晶体管M8截止。发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源端VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的控制极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源端VDD输出的电源电压。
随着显示技术的发展，拜耳排列的子像素排布设计已成为主流产品常用的设计。如图2所示，奇数列数据信号线与驱动第一发光器件的像素驱动电路和驱动第二发光器件的像素驱动电路电连接，使得当显示产品在显示红蓝纯色画面时，向数据信号线提供信号的驱动器会在第一颜色数据信号和第二颜色数据信号之间高频切换，使得显示产品的功耗较高。
图5为本公开实施例提供的显示基板的结构示意图一，图6为本公开实施例提供的显示基板的结构示意图二。如图5和图6所示，本公开实施例提供的显示基板可以包括：基底以及设置在基底上的多行多列像素驱动电路、多行多列发光器件、多条数据信号线Data和多条阳极连接线，像素驱动电路分别与数据信号线和发光器件连接，发光器件包括：第一发光器件L1、第二发光器件L2和第三发光器件L3，多个第一发光器件L1和多个第二发光器件L2沿列方向交替排布，多个第三发光器件L3沿列方向排布，发光器件包括：第一电极。图5和图6是以阳极连接线CL1和CL2为例进行说明的。图5和图6中仅示出了第一驱动区。
在示例性实施方式中，如图5和图6所示，在第一驱动区，第n行第4a-3列发光器件为第一发光器件，第n行第4a-1列发光器件为第二发光器件，第n+1行第4a-3列发光器件为第二发光器件，第n+1行第4a-1列发光器件为第一发光器件，第偶数列发光器件为第三发光器件，1≤a≤M/4，1≤n≤N-1，M为第一驱动区的发光器件或者像素驱动电路的总列数，且为偶数；N为第一驱动区的发光器件或者像素驱动电路的总行数。
在示例性实施方式中，如图5和图6所示，第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器的第一电极件电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接。图5和图6是以第奇数列的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器的第一电极电连接，第偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接为例进行说明的。
在示例性实施方式中，如图5和图6所示，第n行第2f-1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f+1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第2f+1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f-1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第偶数列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第偶数列像素驱动电路所在区域在基底上的正投影部分交叠，1≤f≤M/2，且为奇数。示例性地，当M＝8，f＝1或3，以第一行像素驱动电路为例，第一行第一列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第一行第三列像素驱动电路所在区域在基底上的正投影部分交叠，第一行第三列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第一行第一列像素驱动电路所在区域在基底上的正投影部分交叠，第一行第五列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第一行第七列像素驱动电路所在区域在基底上的正投影部分交叠，第一行第七列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第一行第五列像素驱动电路所在区域在基底上的正投影部分交叠，第一行第二列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第一行第二列像素驱动电路所在区域在基底上的正投影部分交叠，第一行第四列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第一行第四列像素驱动电路所在区域在基底上的正投影部分交叠，依次类推。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，如图5和图6所示，在第一驱动区，第奇数行第4a-3列发光器件为第一发光器件L1，第奇数行第4a-1列发光器件为第二发光器件L2，第偶数行第4a-3列发光器件为第二发光器件L2，第奇数行第4a-1列发光器件为第一发光器件L1，第偶数列发光器件为第三发光器件L3，1≤a≤M/4，M为发光器件的总列数，且为偶数。 示例性地，所有奇数行的发光器件的排布方式相同，以第一行为例，第一行第一列发光器件、第一行第五列发光器件、第一行第九列发光器件依次类推均为第一发光器件，第一行第三列发光器件、第一行第七列发光器件、第一行第十一列发光器件依次类推均为第二发光器件。所有偶数行发光器件的排布方式相同，以第二行为例，第二行第一列发光器件、第二行第五列发光器件、第二行第九列发光器件依次类推均为第二发光器件，第二行第三列发光器件、第二行第七列发光器件、第二行第十一列发光器件依次类推均为第一发光器件。
在示例性实施方式中，一列像素驱动电路可以与至少一条数据信号线电连接。图5和图6是以一列像素驱动电路与一条数据信号线电连接，且图5和图6仅示出了第一条数据信号线Data1至第八条数据信号线Data8。
在示例性实施方式中，第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器件电连接，使得与第奇数列或偶数列中之一的像素驱动电路连接的数据信号线仅提供第一颜色数据信号或者第二颜色数据信号。其中，当第奇数列或偶数列中之一的像素驱动电路与第一发光器件电连接时，与第奇数列或偶数列中之一的像素驱动电路连接的数据信号线提供第一颜色数据信号，当第奇数列或偶数列中之一的像素驱动电路与第二发光器件电连接时，与第奇数列或偶数列中之一的像素驱动电路连接的数据信号线提供第二颜色数据信号。第奇数列或偶数列中另一者的像素驱动电路与第三发光器件电连接，使得与奇数列或偶数列中另一者的像素驱动电路连接的数据信号线仅提供第三颜色数据信号。
在示例性实施方式中，显示基板还与数据驱动器电连接，数据驱动器被配置为向数据信号线提供信号。由于第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器件电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件电连接，使得无论显示基板显示什么画面，数据信号线持续提供同一颜色数据信号，即向数据信号线提供信号的数据驱动器不需要在不同颜色数据信号之间进行高频切换。
本公开实施例提供的显示基板包括：包括：基底以及设置在基底上的多行多列像素驱动电路、多行多列发光器件、多条数据信号线和多条阳极连接线，所述基底包括：第一驱动区，所述像素驱动电路和所述数据信号线位于所述第一驱动区，所述发光器件和所述阳极连接线至少部分位于所述第一驱动区；像素驱动电路分别与数据信号线和发光器件连接，所述发光器件包括：第一发光器件、第二发光器件和第三发光器件，多个第一发光器件和多个第二发光器件沿列方向交替排布，多个第三发光器件沿列方向排布；，所述发光器件包括：第一电极；在所述第一驱动区，第n行第4a-3列发光器件为第一发光器件，第n行第4a-1列发光器件为第二发光器件，第n+1行第4a-3列发光器件为第二发光器件，第n+1行第4a-1列发光器件为第一发光器件，第偶数列发光器件为第三发光器件，1≤a≤M/4，1≤n≤N-1，M为第一驱动区的发光器件或者像素驱动电路的总列数，且为偶数；N为第一驱动区的发光器件或者像素驱动电路的总行数，第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器的第一电极件电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接；第n行第2f-1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f+1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第2f+1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f-1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第偶数列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第偶数列像素驱动电路所在区域在基底上的正投影部分交叠，1≤f≤M/2，且为奇数。本公开通过第奇数列或偶数列中之一的像素驱动电路通过阳极连接线 与第一发光器件或者第二发光器的第一电极电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接，可以在当显示产品在显示红蓝纯色画面时，使得提供数据信号的数据驱动器不需要在不同数据信号之间高频切换，可以降低显示产品的功耗，提升显示产品的可靠性。
在示例性实施方式中，第一发光器件发射红色或者蓝色中的一种颜色的光线，第二发光器件发射为红色或者蓝色中的另一种颜色的光线，第三发光器件发射绿色光线。
在示例性实施方式中，如图5和图6所示，像素驱动电路设置有阳极连接过孔V，发光器件的第一电极通过阳极连接过孔与像素驱动电路电连接。
在示例性实施方式中，阳极连接孔被配置为暴露出如图3A和图4A提供的像素驱动电路中的第六晶体管的第二极(也是第七晶体管的第二极)的过孔。至少一条阳极连接线通过阳极连接孔与所连接的像素驱动电路中的第六晶体管的第二极(也是第七晶体管的第二极)
在示例性实施方式中，显示基板还包括：转接孔，转接孔被配置为暴露出阳极连接线。示例性地，至少一个发光器件的第一电极通过转接孔与阳极连接线电连接。
在示例性实施方式中，如图5和图6所示，像素驱动电路包括：第一像素驱动电路P1、第二像素驱动电路P2和第三像素驱动电路P3，第一像素驱动电路P1被配置为驱动第一发光器件L1发光，第二像素驱动电路P2被配置为驱动第二发光器件L2发光，第三像素驱动电路P3被配置为驱动第三发光器件L3发光。其中，第奇数列像素驱动电路为第一像素驱动电路或者第二像素驱动电路，第偶数列像素驱动电路为第三像素驱动电路。
在示例性实施方式中，如图5和图6所示，第d列像素驱动电路为第一像素驱动电路和第二像素驱动电路中的其中一个，第d+2列像素驱动电路为第一像素驱动电路和第二像素驱动电路中的另一个，1≤d≤M，且d为奇数。示例性地，第一列像素驱动电路为第一像素驱动电路时，第三列像素驱动电路为第二像素驱动电路，第五列像素驱动电路为第一像素驱动电路，第七列像素驱动电路为第二像素驱动电路，依次类推。第一列像素驱动电路为第二像素驱动电路时，第三列像素驱动电路为第一像素驱动电路，第五列像素驱动电路为第二像素驱动电路，第七列像素驱动电路为第一像素驱动电路，依次类推。
在示例性实施方式中，至少一个第一发光器件L1的第一电极在基底上的正投影与第一发光器件L1所连接的阳极连接线在基底上的正投影部分交叠，至少一个第一发光器件L1的第一电极在基底上的正投影与第一发光器件L1所连接的第一像素驱动电路P1的阳极连接过孔V在基底上的正投影不交叠。
在示例性实施方式中，至少一个第二发光器件L2的第一电极在基底上的正投影与第二发光器件L2所连接的阳极连接线在基底上的正投影部分交叠，至少一个第二发光器件L2第一电极在基底上的正投影与第二发光器件L2所连接的第二像素驱动电路P2的阳极连接过孔V在基底上的正投影不交叠。
在示例性实施方式中，第三发光器件L3的第一电极在基底上的正投影与第三发光器件L3所连接的第三像素驱动电路P3的阳极连接过孔V在基底上的正投影部分交叠。
在示例性实施方式中，如图5和图6所示，阳极连接线可以包括：第一阳极连接线CL1和第二阳极连接线CL2。
在示例性实施方式中，第一阳极连接线CL1分别与部分第一像素驱动电路和部分第一像素驱动电路所连接的第一发光器件的第一电极电连接，第一阳极连接线CL1在基底上的正投影与所连接的第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，且 与所连接的第一发光器件的第一电极在基底上的正投影部分交叠。
在示例性实施方式中，第二阳极连接线CL2分别与部分第二像素驱动电路和部分第二像素驱动电路所连接的第二发光器件的第一电极电连接，第二阳极连接线CL2在基底上的正投影与所连接的第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，且与所连接的第二发光器件的第一电极在基底上的正投影部分交叠。
在示例性实施方式中，如图5所示，第4a-3列像素驱动电路为第一像素驱动电路P1，第4a-1列像素驱动电路为第二像素驱动电路P2。示例性地，第一列像素驱动电路、第五列像素驱动电路、第九列像素驱动电路依次类推为第一像素驱动电路P1，第二列像素驱动电路、第五列像素驱动电路、第九列像素驱动电路依次类推为第二像素驱动电路P2。
在示例性实施方式中，如图5所示，第b行第d列像素驱动电路的阳极连接过孔V在基底上的正投影与第b行第d列的发光器件的第一电极在基底上的正投影部分交叠，其中，1≤b≤N，且为奇数，1≤d≤M，且d为奇数，N为像素驱动电路的总列数，即任一奇数行任一奇数列像素驱动电路的阳极连接过孔V在基底上的正投影与任一奇数行任一奇数列的发光器件的第一电极在基底上的正投影部分交叠，示例性地，第一行第一列像素驱动电路的阳极连接过孔V在基底上的正投影与第一行第一列的发光器件的第一电极在基底上的正投影部分交叠，第一行第三列像素驱动电路的阳极连接过孔V在基底上的正投影与第一行第三列的发光器件的第一电极在基底上的正投影部分交叠，依次类推。
在示例性实施方式中，如图5所示，第c行第d列像素驱动电路的阳极连接过孔V在基底上的正投影与第c行第d列发光器件的第一电极在基底上的正投影不交叠，其中，1≤c≤N，且为偶数，即任一偶数行任一奇数列像素驱动电路的阳极连接过孔V在基底上的正投影与任一偶数行任一奇数列发光器件的第一电极在基底上的正投影不交叠，示例性地，第二行第一列像素驱动电路的阳极连接过孔V在基底上的正投影与第二行第一列的发光器件的第一电极在基底上的正投影不交叠，第二行第三列像素驱动电路的阳极连接过孔V在基底上的正投影与第二行第三列的发光器件的第一电极在基底上的正投影不交叠，依次类推。
在示例性实施方式中，如图5所示，第一阳极连接线CL1分别与第c行第4a-3列像素驱动电路和第c行第4a-1列发光器件的第一电极电连接。示例性地，第一阳极连接线CL1分别与第二行第一列像素驱动电路和第二行第三列发光器件的第一电极电连接，第一阳极连接线CL1分别与第二行第五列像素驱动电路和第二行第七列发光器件的第一电极电连接，第一阳极连接线CL1分别与第二行第九列像素驱动电路和第二行第十一列发光器件的第一电极电连接，依次类推。
在示例性实施方式中，如图5所示，第二阳极连接线CL2通分别与第c行第4a-1列像素驱动电路和第c行第4a-3列发光器件的第一电极电连接。示例性地，第二阳极连接线CL2分别与第二行第三列像素驱动电路和第二行第一列发光器件的第一电极电连接，第二阳极连接线CL2分别与第二行第七列像素驱动电路和第二行第五列发光器件的第一电极电连接，第二阳极连接线CL2分别与第二行第十一列像素驱动电路和第二行第九列发光器件的第一电极电连接，依次类推。
在示例性实施方式中，位于奇数行的第一发光器件的第一电极的面积大于位于偶数行的第一发光器件的第一电极的面积，位于奇数行的第二发光器件的第一电极的面积大于位于偶数行的第二发光器件的第一电极的面积。
在示例性实施方式中，位于奇数行的第一发光器件的第一电极包括：第一电极主体部和第一电极连接部，第一电极连接部与第一发光器件所连接的像素驱动电路连接。位于偶 数行的第一发光器件的第一电极仅包括第一电极主体部。
在示例性实施方式中，位于奇数行的第二发光器件的第一电极包括：第二电极主体部和第二电极连接部，第二电极连接部与第二发光器件所连接的像素驱动电路连接。位于偶数行的第二发光器件的第一电极仅包括第二电极主体部。
在示例性实施方式中，第三发光器件的第一电极包括：第三电极主体部和第三电极连接部。
在示例性实施方式中，如图6所示，第4a-3列像素驱动电路为第二像素驱动电路P2，第4a-1列像素驱动电路为第一像素驱动电路P1。示例性地，示例性地，第一列像素驱动电路、第五列像素驱动电路、第九列像素驱动电路依次类推为第二像素驱动电路P2，第二列像素驱动电路、第五列像素驱动电路、第九列像素驱动电路依次类推为第一像素驱动电路P1。
在示例性实施方式中，如图6所示，第c行第d列像素驱动电路的阳极连接过孔V在基底上的正投影与第c行第d列的发光器件的第一电极在基底上的正投影部分交叠，其中，1≤c≤N，且为偶数，1≤d≤M，且d为奇数，N为像素驱动电路的总列数，即任一偶数行任一奇数列像素驱动电路的阳极连接过孔V在基底上的正投影与任一偶数行任一奇数列的发光器件的第一电极在基底上的正投影部分交叠，示例性地，第二行第一列像素驱动电路的阳极连接过孔V在基底上的正投影与第二行第一列的发光器件的第一电极在基底上的正投影部分交叠，第二行第三列像素驱动电路的阳极连接过孔V在基底上的正投影与第二行第三列的发光器件的第一电极在基底上的正投影部分交叠，依次类推。
在示例性实施方式中，如图6所示，第b行第d列像素驱动电路的阳极连接过孔V在基底上的正投影与第b行第d列发光器件的第一电极在基底上的正投影不交叠，其中，1≤b≤N，且为奇数，即任一奇数行任一奇数列像素驱动电路的阳极连接过孔V在基底上的正投影与任一奇数行任一奇数列发光器件的第一电极在基底上的正投影不交叠，示例性地，第一行第一列像素驱动电路的阳极连接过孔V在基底上的正投影与第一行第一列的发光器件的第一电极在基底上的正投影不交叠，第一行第三列像素驱动电路的阳极连接过孔V在基底上的正投影与第一行第三列的发光器件的第一电极在基底上的正投影不交叠，依次类推。
在示例性实施方式中，如图6所示，第一阳极连接线CL1分别与第b行第4a-1列像素驱动电路和第b行第4a-3列发光器件的第一电极电连接。示例性地，第一阳极连接线CL1分别与第一行第三列像素驱动电路和第一行第一列发光器件的第一电极电连接，第一阳极连接线CL1分别与第一行第七列像素驱动电路和第一行第九列发光器件的第一电极电连接，第一阳极连接线CL1分别与第二行第十一列像素驱动电路和第二行第九列发光器件的第一电极电连接，依次类推。
在示例性实施方式中，如图6所示，第二阳极连接线CL2分别与第b行第4a-3列像素驱动电路和第b行第4a-1列发光器件的第一电极电连接。示例性地，第二阳极连接线CL2分别与第一行第一列像素驱动电路和第一行第三列发光器件的第一电极电连接，第二阳极连接线CL2分别与第一行第五列像素驱动电路和第二行第七列发光器件的第一电极电连接，第二阳极连接线CL2分别与第一行第九列像素驱动电路和第二行第十一列发光器件的第一电极电连接，依次类推。
在示例性实施方式中，位于偶数行的第一发光器件的第一电极的面积大于位奇数行的第一发光器件的第一电极的面积，位于偶数行的第二发光器件的第一电极的面积大于位于奇数行的第二发光器件的第一电极的面积。
在示例性实施方式中，位于偶数行的第一发光器件的第一电极包括：第一电极主体部和第一电极连接部，第一电极连接部与第一发光器件所连接的像素驱动电路连接。位于奇数行的第一发光器件的第一电极仅包括第一电极主体部。
在示例性实施方式中，位于偶数行的第二发光器件的第一电极包括：第二电极主体部和第二电极连接部，第二电极连接部与第二发光器件所连接的像素驱动电路连接。位于奇数行的第二发光器件的第一电极仅包括第二电极主体部。
在示例性实施方式中，第三发光器件的第一电极包括：第三电极主体部和第三电极连接部。
在示例性实施方式中，当第4a-3列像素驱动电路为第二像素驱动电路P2，第4a-1列像素驱动电路为第一像素驱动电路P1，或者，第4a-3列像素驱动电路为第一像素驱动电路P1，第4a-1列像素驱动电路为第二像素驱动电路P2时，第一发光器件的第一电极还可以包括：至少一个第一凸出部，至少一个第一凸出部设置在第一电极主体部上。第二发光器件的第一电极还可以包括：至少一个第二凸出部，至少一个第二凸出部设置在第二电极主体部上。第三发光器件中的第一电极还可以包括：至少一个第三凸出部，至少一个第三凸出部设置在第三电极主体部上。
在示例性实施方式中，第一凸出部、第二凸出部和第三凸出部被配置为遮挡光线被配置为遮挡光线。
在示例性实施方式中，第一阳极连接线在基底上的正投影与第一凸出部、第二凸出部和第三凸出部中的至少一个在基底上的正投影部分交叠。
在示例性实施方式中，第二阳极连接线在基底上的正投影与第一凸出部、第二凸出部和第三凸出部中的至少一个在基底上的正投影部分交叠。
在示例性实施方式中，图7为显示基板的截面示意图一，图8为显示基板的截面示意图二，图9为显示基板的截面示意图三，图10为显示基板的截面示意图四。如图7至图10所示，第一阳极连接线CL1在基底上的正投影与第二阳极连接线CL2在基底上的正投影至少部分交叠。第一阳极连接线CL1在基底上的正投影与第二阳极连接线CL2在基底上的正投影至少部分交叠可以减少第一阳极连接线和第二阳极连接线的长度，降低显示基板的成本。图7至图9是以第4a-3列像素驱动电路为第一像素驱动电路，第4a-1列像素驱动电路为第二像素驱动电路为例进行说明的。图7至图10中，CV为暴露出第一阳极连接线或者第二阳极连接线的转接孔。
在示例性实施方式中，如图7所示，第一阳极连接线CL1和第二阳极连接线CL2为直线型，第一阳极连接线CL1的延伸方向和第二阳极连接线CL2的延伸方向相交，且第一阳极连接线CL1的延伸方向和第二阳极连接线CL2的延伸方向均不同于行方向和列方向。
在示例性实施方式中，如图7所示，第一阳极连接线CL1在基底上的正投影与第二发光器件的第一电极AL2和第三发光器件的第一电极AL3在基底上的正投影不交叠，第二阳极连接线CL2在基底上的正投影与第一发光器件的第一电极AL1和第三发光器件的第一电极AL3在基底上的正投影不交叠，第一阳极连接线CL1和第二阳极连接线CL2位于第三像素驱动电路的阳极连接过孔的同一侧。
在示例性实施方式中，如图8所示，第一阳极连接线CL1和第二阳极连接线CL2包括：第一连接段和第二连接段，位于同一阳极连接线的第一连接段和第二连接段连接，且第一连接段和第二连接段呈直角设置，第一连接段沿列方向延伸，第二连接段沿行方向延伸。
在示例性实施方式中，如图8所示，第一阳极连接线CL1的第一连接段CL11在基底上的正投影与第一像素驱动电路P1的阳极连接过孔VV和第二发光器件的第一电极AL2在基底上的正投影部分交叠，第一阳极连接线CL1的第二连接段CL12在基底上的正投影与第二阳极连接线CL2的第二连接段CL22、第一发光器件的第一电极AL1和第二发光器件的第一电极AL2在基底上的正投影部分交叠。
在示例性实施方式中，如图8所示，第二阳极连接线CL2的第一连接段CL21在基底上的正投影与第二像素驱动电路的阳极连接过孔V和第一发光器件的第一电极AL1在基底上的正投影部分交叠，第二阳极连接线CL2的第二连接段CL22在基底上的正投影与第一发光器件的第一电极AL1和第二发光器件的第一电极AL2在基底上的正投影部分交叠。
在示例性实施方式中，如图8所示，第一阳极连接线CL1和第二阳极连接线CL2在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影不交叠，且位于第三像素驱动电路P3的阳极连接过孔V的同一侧。
在示例性实施方式中，如图9所示，第一阳极连接线CL1包括：第一连接段CL11、第二连接段CL12和第三连接段CL13，第一连接段CL11和第三连接段CL13沿列方向延伸，第二连接段CL12沿行方向延伸，第一连接段CL11和第三连接段CL13位于第二连接段CL12的同一侧，且分别与第二连接段CL12电连接，第二阳极连接线CL2包括：第四连接段CL21和第五连接段CL22，第四连接段CL21和第五连接段CL22连接，且呈直角设置，第四连接段CL21沿列方向延伸，第五连接段CL22沿行方向延伸。
在示例性实施方式中，如图9所示，第一阳极连接线CL1的第一连接段CL11在基底上的正投影与第一像素驱动电路的阳极连接过孔V在基底上的正投影部分交叠，第一阳极连接线CL1的第二连接段CL12在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠，第一阳极连接线CL1的第三连接段CL13在基底上的正投影与第一发光器件的第一电极AL1和第二阳极连接线CL2的第五连接段CL22在基底上的正投影部分交叠，第二阳极连接线CL2的第四连接段CL21在基底上的正投影与第二像素驱动电路的阳极连接过孔V和第一发光器件的第一电极AL1在基底上的正投影部分交叠，第二阳极连接线CL2的第五连接段CL22在基底上的正投影与第一发光器件的第一电极AL1和第二发光器件的第一电极AL2部分交叠。
在示例性实施方式中，如图9所示，第二阳极连接线CL2在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影不交叠，第一阳极连接线CL1和第二阳极连接线CL2分别位于第三像素驱动电路的阳极连接过孔V的不同侧。
在示例性实施方式中，如图10所示，第二阳极连接线CL2包括：第一连接段CL21、第二连接段CL22和第三连接段CL23，第一连接段CL21和第三连接段CL23沿列方向延伸，第二连接段CL22沿行方向延伸，第一连接段CL21和第三连接段CL23位于第二连接段CL22的同一侧，且分别与第二连接段CL22电连接，第一阳极连接线CL1包括：第四连接段CL11和第五连接段CL12，第四连接段CL11和第五连接段CL12连接，且呈直角设置，第四连接段CL11沿列方向延伸，第五连接段CL12沿行方向延伸。
在示例性实施方式中，如图10所示，第一阳极连接线CL1的第四连接段CL11在基底上的正投影与第一像素驱动电路的阳极连接过孔V和第二发光器件的第一电极AL2在基底上的正投影部分交叠，第一阳极连接线CL1的第五连接段CL12在基底上的正投影与第一发光器件的第一电极AL1、第二发光器件的第一电极AL2和第二阳极连接线CL2的第三连接段CL23在基底上的正投影部分交叠。
在示例性实施方式中，如图10所示，第二阳极连接线CL2的第一连接段CL21在基底上的正投影与第二像素驱动电路的阳极连接过孔V在基底上的正投影部分交叠，第二阳极连接线CL2的第二连接段CL22在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠，第二阳极连接线CL2的第三连接段CL23在基底上的正投影与第二发光器件的第一电极AL2在基底上的正投影部分交叠；
在示例性实施方式中，如图10所示，第一阳极连接线CL1在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影不交叠，第一阳极连接线CL1和第二阳极连接线CL2分别位于第三像素驱动电路的阳极连接过孔V的不同侧。
在示例性实施方式中，图11为显示基板的截面示意图五，图12为显示基板的截面示意图六，图13为显示基板的截面示意图七，图14为显示基板的截面示意图八，图15为显示基板的截面示意图九。如图11至图15所示，第一阳极连接线CL1在基底上的正投影与第二阳极连接线CL2在基底上的正投影不交叠。第一阳极连接线CL1在基底上的正投影与第二阳极连接线CL2在基底上的正投影不交叠可以减少第一阳极连接线和第二阳极连接线的信号之间的串扰。图11至图15是以第4a-3列像素驱动电路为第一像素驱动电路，第4a-1列像素驱动电路为第二像素驱动电路为例进行说明的。图11至图15中，CV为暴露出第一阳极连接线或者第二阳极连接线的转接孔。
在示例性实施方式中，如图11所示，第一阳极连接线CL1和第二阳极连接线CL2均包括：第一连接段、第二连接段和第三连接段，第一连接段和第三连接段沿列方向延伸，第二连接段沿行方向延伸，第一连接段和第三连接段位于第二连接段的同一侧，且分别与第二连接段电连接。
在示例性实施方式中，如图11所示，第一阳极连接线CL1的第一连接段CL1在基底上的正投影与第一像素驱动电路的阳极连接过孔V在基底上的正投影部分交叠，第一阳极连接线CL1的第二连接段CL12在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠，第一阳极连接线CL1的第三连接段CL13在基底上的正投影与第一发光器件的第一电极AL1在基底上的正投影部分交叠。
在示例性实施方式中，如图11所示，第二阳极连接线CL2的第一连接段CL21在基底上的正投影与第二像素驱动电路的阳极连接过孔V在基底上的正投影部分交叠，第二阳极连接线CL2的第二连接段CL22在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠，第二阳极连接线CL2的第三连接段CL23在基底上的正投影与第二发光器件的第一电极AL2在基底上的正投影部分交叠；
在示例性实施方式中，如图11所示，第一阳极连接线CL1和第二阳极连接线CL2分别位于第三像素驱动电路的阳极连接过孔V的同一侧。
在示例性实施方式中，如图12和图14所示，第一阳极连接线CL1包括：第一连接段CL11、第二连接段CL12和第三连接段CL13，第一连接段CL11和第三连接段CL13沿列方向延伸，第二连接段CL12沿行方向延伸，第一连接段CL11和第三连接段CL13位于第二连接段CL12的同一侧，且分别与第二连接段CL12电连接，第二阳极连接线CL2包括：第四连接段CL21和第五连接段CL22，第四连接段CL21和第五连接段CL22连接，且呈锐角设置，第四连接段CL21沿列方向延伸。
在示例性实施方式中，如图12和图14所示，第一阳极连接线CL1的第一连接段CL11在基底上的正投影与第一像素驱动电路的阳极连接过孔V在基底上的正投影部分交叠，第一阳极连接线CL1的第二连接段CL12在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠或者不交叠，第一阳极连接线CL1的第三连接段CL13 在基底上的正投影与第一发光器件的第一电极AL1在基底上的正投影部分交叠。图12是以第一阳极连接线CL1的第二连接段CL12在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠为例进行说明的，图14是以第一阳极连接线CL1的第二连接段CL12在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影不交叠为例进行说明的。
在示例性实施方式中，如图12和图14所示，第二阳极连接线CL2的第四连接段CL21在基底上的正投影与第二像素驱动电路的阳极连接过孔V和第一发光器件的第一电极AL1在基底上的正投影部分交叠，第二阳极连接线CL2的第五连接段CL22在基底上的正投影与第二发光器件的第一电极AL2部分交叠。
在示例性实施方式中，如图12和图14所示，第二阳极连接线CL2在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影不交叠，第一阳极连接线CL1和第二阳极连接线CL2分别位于第三像素驱动电路的阳极连接过孔V的不同侧。
在示例性实施方式中，如图13和图15所示，第二阳极连接线CL2包括：第一连接段CL21、第二连接段CL22和第三连接段CL23，第一连接段CL21和第三连接段CL23沿列方向延伸，第二连接段CL22沿行方向延伸，第一连接段CL21和第三连接段CL23位于第二连接段CL22的同一侧，且分别与第二连接段CL22电连接，第一阳极连接线CL1包括：第四连接段CL11和第五连接段CL12，第四连接段CL11和第五连接段CL12连接，且呈锐角设置，第四连接段CL11沿列方向延伸。
在示例性实施方式中，如图13和图15所示，第一阳极连接线CL1的第四连接段CL11在基底上的正投影与第一像素驱动电路的阳极连接过孔V和第二发光器件的第一电极AL2在基底上的正投影部分交叠，第一阳极连接线CL1的第五连接段CL12在基底上的正投影与第一发光器件的第一电极AL1在基底上的正投影部分交叠。
在示例性实施方式中，如图13和图15所示，第二阳极连接线CL2的第一连接段CL21在基底上的正投影与第二像素驱动电路的阳极连接过孔V在基底上的正投影部分交叠，第二阳极连接线CL2的第二连接段CL22在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影部分交叠或者不交叠，第二阳极连接线CL2的第三连接段CL23在基底上的正投影与第二发光器件的第一电极AL2在基底上的正投影部分交叠。
在示例性实施方式中，如图13和图15所示，第一阳极连接线CL1在基底上的正投影与第三发光器件的第一电极AL3在基底上的正投影不交叠，第一阳极连接线CL1和第二阳极连接线CL2分别第三像素驱动电路的阳极连接过孔V的不同侧。
在示例性实施方式中，如图7至图15中的发光器件可以仅位于第一驱动区，或者至少位于第一驱动区。
在示例性实施方式中，第一驱动区可以包括：第一显示区和第二显示区，第一显示区至少部分围设在第二显示区，第二显示区可以为透光显示区，第一显示区为正常显示区，此时，显示基板可以为设置有屏下摄像头的显示基板。
在示例性实施方式中，图16为另一显示基板的截面示意图。如图16所示，基底还包括：第二驱动区200，第一驱动区100包括：相对设置的第一侧和第二侧，第二驱动区200位于第一驱动区100的第一侧和第二侧中的至少一侧，且第二驱动区200还设置有栅极驱动电路和发光器件，栅极驱动电路被配置为向像素驱动电路提供控制信号。图16提供的显示基板中发光器件可以设置在像素驱动电路和栅极驱动电路上。图16中，CV为暴露出第一阳极连接线或者第二阳极连接线的转接孔。
在示例性实施方式中，如图16所示，至少一条第一阳极连接线CL1分别与位于第一 驱动区的第一像素驱动电路和位于第二驱动区的至少一个第一发光器件的第一电极AL1电连接，至少一条第二阳极连接线CL2分别与位于第一驱动区的第二像素驱动电路和位于第二驱动区的至少一个第二发光器件的第一电极AL2电连接。
图16中提供的显示基板中像素驱动电路可以包括：显示像素驱动电路和虚拟像素驱动电路，与位于第二驱动区的至少一个第一发光器件的第一电极AL1电连接的像素驱动电路可以为虚拟像素驱动电路。
在示例性实施方式中，当第一阳极连接线CL1在基底上的正投影与第二阳极连接线CL2在基底上的正投影部分交叠时，第一阳极连接线CL1和第二阳极连接线CL2异层设置。
在示例性实施方式中，当第一阳极连接线CL1在基底上的正投影与第二阳极连接线CL2在基底上的正投影不交叠时，第一阳极连接线CL1和第二阳极连接线CL2异层设置或者同层设置。
在示例性实施方式中，第一阳极连接线CL1可以包括：金属线或者透明导电线。
在示例性实施方式中，第二阳极连接线CL2可以包括：金属线或者透明导电层。
在示例性实施方式中，图17为图7沿A-A向的截面示意图，图18为图7沿B-B向的截面示意图。如图17和图18所示，显示基板包括：设置在基底10上的驱动结构层和发光结构层，驱动结构层设置有像素驱动电路、栅极驱动电路和数据信号线，发光结构层设置有发光器件。像素驱动电路包括：晶体管和电容，电容包括：第一极板和第二极板。
在示例性实施方式中，驱动结构层包括：依次叠设在基底10上的第一导电层22、第二导电层23和第三导电层24，发光结构层包括：第四导电层32、有机发光层33和第五导电层。
在示例性实施方式中，第一导电层22至少可以包括：多个晶体管的栅电极、电容的第一极板以及栅线。其中，当像素驱动电路为图3A时，栅线包括：扫描信号线、复位信号线、发光信号线，当像素驱动电路为图4A时，栅线包括：扫描信号线、复位信号线、发光信号线和控制信号线。
在示例性实施方式中，第二导电层23至少可以包括：电容的第二极板。
在示例性实施方式中，第三导电层24至少包括：多个晶体管的源漏电极和数据信号线。
在示例性实施方式中，第四导电层32至少包括：发光器件的第一电极。图17是以发光器件为第一发光器件为例进行说明的，图18是以发光器件为第二发光器件为例进行说明的。
在示例性实施方式中，发光结构层还可以包括：像素定义层31。
在示例性实施方式中，第一阳极连接线CL1位于第三导电层或者第四导电层。图17是以第一阳极连接线CL1位于第四导电层为例进行说明的。
在示例性实施方式中，第二阳极连接线CL2位于第三导电层或者第四导电层。图18是第二阳极连接线CL2位于第三导电层为例进行说明的。
在示例性实施方式中，第三导电层可以为单层结构或者多层结构。
在示例性实施方式中，当第三导电层为多层结构时，第三导电层包括：第一子导电层和第二子导电层，或者第三导电层包括：第一子导电层、第二子导电层和第三子导电层，其中，第一子导电层和第二子导电层为金属导电层，第三子导电层包括：金属导电层或者 透明导电层。图17和图18是以第三导电层24包括：第一子导电层241、第二子导电层242和第三子导电层243，且第三子导电层为金属导电层为例进行说明的。
在示例性实施方式中，当第三子导电层为透明导电层时，第三子导电层的数量为至少一个。示例性地，第三子导电层的数量可以为一个，或者可以为三个。示例性地，第三导电层可以包括层叠设置的第一金属导电层和第二金属导电层，或者可以包括：层叠设置的第一金属导电层、第二金属导电层、第三金属导电层，或者可以包括：层叠设置的第一金属导电层、第二金属导电层、透明导电层，或者可以包括：层叠设置的第一金属导电层、第二金属导电层、第一透明导电层、第二透明导电层和第三透明导电层。
在示例性实施方式中，当显示基板为图16提供的显示基板时，第三子导电层可以包括一个透明导电层，当显示基板为设置有屏下摄像头的显示基板时，第三子导电层可以包括：三个透明导电层。
在示例性实施方式中，当第三导电层为多层结构时，第一阳极连接线CL1和第二阳极连接线CL2位于第三导电层的至少一个膜层中。示例性地，当第三导电层包括层叠设置的第一金属导电层和第二金属导电层时，第一阳极连接线CL1可以位于第一金属导电层和第二金属导电层中的其中一个膜层，第二阳极连接线CL2可以位于第一金属导电层和第二金属导电层中的其中一个膜层；当第三导电层包括：层叠设置的第一金属导电层、第二金属导电层、第三金属导电层时，第一阳极连接线CL1可以位于第一金属导电层、第二金属导电层和第三金属导电层中的其中一个膜层，第二阳极连接线CL2可以位于第一金属导电层、第二金属导电层和第三金属导电层中的其中一个膜层，当第三导电层包括：层叠设置的第一金属导电层、第二金属导电层、透明导电层时，第一阳极连接线CL1可以位于第一金属导电层、第二金属导电层、透明导电层中的其中一个膜层，第二阳极连接线CL2可以位于第一金属导电层、第二金属导电层、透明导电层中的其中一个膜层；当第三导电层包括：层叠设置的第一金属导电层、第二金属导电层、第一透明导电层、第二透明导电层和第三透明导电层，第一阳极连接线CL1可以位于第一金属导电层、第二金属导电层、第一透明导电层、第二透明导电层和第三透明导电层中的其中一个膜层，第二阳极连接线CL2可以位于第一金属导电层、第二金属导电层、第一透明导电层、第二透明导电层和第三透明导电层中的其中一个膜层，本公开对此不做任何限定。
在示例性实施方式，第一阳极连接线CL可以与同层设置膜层的制作材料线相同，或者可以与同层设置膜层的制作材料不同，本公开对此不做任何限定。
在示例性实施方式中，第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo，Ti/Al/Ti等。
在示例性实施方式中，第四导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述导电的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性地，第四导电层可以为钛、铝和钛形成的三层堆叠结构。
在示例性实施方式中，像素驱动电路中的晶体管包括：低温多晶体管晶体管，或者可以包括低温多晶硅晶体管和氧化物晶体管。图17和图18是以像素驱动电路包括：低温多晶硅晶体管210和氧化物晶体管220为例进行说明的。
在示例性实施方式中，当像素驱动电路中的晶体管包括：低温多晶体管晶体管时，驱动结构层还可以包括：半导体层，半导体层位于第一导电层靠近基底的一侧。
在示例性实施方式中，半导体层图案可以为非晶硅层或者多晶硅层，或者可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中，半导体层可以至少包括：晶体管的有源层。
在示例性实施方式中，当像素驱动电路中的晶体管包括：低温多晶体管晶体管时，驱动结构层还可以包括：位于半导体层、第一导电层、第二导电层和第三导电层之间的绝缘层以及位于第三导电层远离基底一侧的平坦层。
在示例性实施方式中，如图17和图18所示，当像素驱动电路中的晶体管包括：低温多晶硅晶体管和氧化物晶体管时，驱动结构层还可以包括：第一半导体层21、第二半导体层25和第六导电层26，第一半导体层21位于第一导电层靠近基底的一侧，第二半导体层位于第二导电层远离基底的一侧，第六导电层位于第二半导体层和第三导电层之间。
在示例性实施方式中，第一半导体层至少可以包括：低温多晶硅晶体管的有源层。
在示例性实施方式中，第二半导体层至少可以包括：氧化物晶体管的有源层。
在示例性实施方式中，第一半导体层图案可以为非晶硅层或者多晶硅层。
在示例性实施方式中，第二半导体层图案可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中当像素驱动电路中的晶体管包括：低温多晶硅晶体管和氧化物晶体管时，与氧化物晶体管的栅电极连接的栅线为双层结构，且包括第一子栅线和第二子栅线。
在示例性实施方式中，第三导电层至少可以包括：与氧化物晶体管的栅电极连接的栅线的第一子栅线。
在示例性实施方式中，第六导电层至少可以包括：与氧化物晶体管的栅电极连接的栅线的第二子栅线。
在示例性实施方式中，第六导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo，Ti/Al/Ti等。
在示例性实施方式中，如图17和图18所示，当像素驱动电路中的晶体管包括：低温多晶硅晶体管和氧化物晶体管时，驱动结构层还可以包括：位于第一半导体层、第一导电层、第二导电层、第二半导体层、第六导电层和第三导电层中任一两个相邻膜层之间的绝缘层以及第三导电层位于基底一侧的平坦层。
在示例性实施方式中，当第三导电层为多层结构时，第三导电层中的相邻膜层之间设置平坦层。示例性地，当第三导电层可以包括层叠设置的第一金属导电层和第二金属导电层时，第一金属导电层和第二金属导电层之间设置有平坦。当第三导电层包括：层叠设置 的第一金属导电层、第二金属导电层、第三金属导电层时，第一金属导电层和第二金属导电层之间设置有平坦层，第二金属导电层和第三金属导电层之间设置有平坦层。当第三导电层包括：层叠设置的第一金属导电层、第二金属导电层和透明导电层时，第一金属导电层和第二金属导电层之间设置有平坦层，第二金属导电层和透明导电层之间设置有平坦层。当第三导电层包括：层叠设置的第一金属导电层、第二金属导电层、第一透明导电层、第二透明导电层和第三透明导电层时，第一金属导电层和第二金属导电层之间设置有平坦层，第二金属导电层和第一透明导电层之间设置有平坦层，第一透明导电层和第二透明导电层之间设置有平坦层，第二透明导电层和第三透明导电层之间设置有平坦层。
在示例性实施方式中，如图17和图18所示，驱动结构层可以包括：位于第一半导体层21和第一导电层22之间的第一绝缘层11，位于第一导电层22和第二导电层23之间的第二绝缘层12，位于第二导电层23和第二半导体层25之间的第三绝缘层13，位于第二半导体层和第六导电层26之间的第六绝缘层14，位于第六导电层26和第一子导电层241之间的第五绝缘层15，位于第一子导电层241和第二子导电层242之间的第一平坦层16，位于第二子导电层242和第三子导电层243之间的第二平坦层17以及位于第三子导电层243远离基底一侧的第三平坦层18。
在示例性实施方式中，绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施方式中，平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，显示基板还包括：设置在发光结构层远离基底一侧的封装结构层。
在示例性实施方式中，显示基板还可以包括其它膜层，如触控结构层等，本公开在此不做限定。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示基板可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种显示基板，包括：基底以及设置在基底上的多行多列像素驱动电路、多行多列发光器件、多条数据信号线和多条阳极连接线，所述基底包括：第一驱动区，所述像素驱动电路和所述数据信号线位于所述第一驱动区，所述发光器件和所述阳极连接线至少部分位于所述第一驱动区；像素驱动电路分别与数据信号线和发光器件连接，所述发光器件包括：第一发光器件、第二发光器件和第三发光器件，多个第一发光器件和多个第二发光器件沿列方向交替排布，多个第三发光器件沿列方向排布，所述发光器件包括：第一电极；
    在所述第一驱动区，第n行第4a-3列发光器件为第一发光器件，第n行第4a-1列发光器件为第二发光器件，第n+1行第4a-3列发光器件为第二发光器件，第n+1行第4a-1列发光器件为第一发光器件，第偶数列发光器件为第三发光器件，1≤a≤M/4，1≤n≤N-1，M为第一驱动区的发光器件或者像素驱动电路的总列数，且为偶数；N为第一驱动区的发光器件或者像素驱动电路的总行数；
    第奇数列或偶数列中之一的像素驱动电路通过阳极连接线与第一发光器件或者第二发光器的第一电极电连接，第奇数列或偶数列中另一者的像素驱动电路与第三发光器件的第一电极电连接；
    第n行第2f-1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f+1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第2f+1列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第2f-1列像素驱动电路所在区域在基底上的正投影部分交叠，第n行第偶数列像素驱动电路所连接的发光器件的第一电极在基底上的正投影与第n行第偶数列像素驱动电路所在区域在基底上的正投影部分交叠，1≤f≤M/2，且为奇数。
  2. 根据权利要求1所述的显示基板，其中，所述像素驱动电路设置有阳极连接过孔，所述发光器件的第一电极通过阳极连接过孔与像素驱动电路电连接，所述像素驱动电路包括：第一像素驱动电路、第二像素驱动电路和第三像素驱动电路，所述第一像素驱动电路被配置为驱动所述第一发光器件发光，所述第二像素驱动电路被配置为驱动所述第二发光器件发光，所述第三像素驱动电路被配置为驱动所述第三发光器件发光；
    第奇数列像素驱动电路为第一像素驱动电路或者第二像素驱动电路，第偶数列像素驱动电路为第三像素驱动电路；
    至少一个第一发光器件的第一电极在基底上的正投影与第一发光器件所连接的阳极连接线在基底上的正投影部分交叠，
    至少一个第一发光器件的第一电极在基底上的正投影与第一发光器件所连接的第一像素驱动电路的阳极连接过孔在基底上的正投影不交叠，
    至少一个第二发光器件的第一电极在基底上的正投影与第二发光器件所连接的阳极连接线在基底上的正投影部分交叠，
    至少一个第二发光器件第一电极在基底上的正投影与第二发光器件所连接的第二像素驱动电路的阳极连接过孔在基底上的正投影不交叠，
    所述第三发光器件的第一电极在基底上的正投影与第三发光器件所连接的第三像素驱动电路的阳极连接过孔在基底上的正投影部分交叠。
  3. 根据权利要求2所述的显示基板，其中，所述阳极连接线包括：第一阳极连接线和第二阳极连接线；
    所述第一阳极连接线分别与部分第一像素驱动电路和部分第一像素驱动电路所连接的第一发光器件的第一电极电连接，所述第一阳极连接线在基底上的正投影与所连接的第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，且与所连接的第一发光器件的第一电极在基底上的正投影部分交叠；
    所述第二阳极连接线分别与部分第二像素驱动电路和部分第二像素驱动电路所连接的第二发光器件的第一电极电连接，所述第二阳极连接线在基底上的正投影与所连接的第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，且与所连接的第二发光器件的第一电极在基底上的正投影部分交叠。
  4. 根据权利要求3所述的显示基板，其中，所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影至少部分交叠。
  5. 根据权利要求4所述的显示基板，其中，所述第一阳极连接线和所述第二阳极连接线为直线型，所述第一阳极连接线的延伸方向和所述第二阳极连接线的延伸方向相交，且所述第一阳极连接线的延伸方向和所述第二阳极连接线的延伸方向均不同于行方向和列方向；
    所述第一阳极连接线在基底上的正投影与第二发光器件的第一电极和所述第三发光器件的第一电极在基底上的正投影不交叠，所述第二阳极连接线在基底上的正投影与第一发光器件的第一电极和所述第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线位于所述第三像素驱动电路的阳极连接过孔的同一侧。
  6. 根据权利要求4所述的显示基板，其中，所述第一阳极连接线和所述第二阳极连接线包括：第一连接段和第二连接段，位于同一阳极连接线的所述第一连接段和所述第二连接段连接，且所述第一连接段和所述第二连接段呈直角设置，所述第一连接段沿列方向延伸，所述第二连接段沿行方向延伸；
    所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔和第二发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与所述第二阳极连接线的第二连接段、第一发光器件的第一电极和第二发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔和第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第一发光器件的第一电极和所述第二发光器件的第一电极在基底上的正投影部分交叠；
    所述第一阳极连接线和所述第二阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，且位于所述第三像素驱动电路的阳极连接过孔的同一侧。
  7. 根据权利要求4所述的显示基板，其中，所述第一阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第二阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈直角设置，所述第四连接段沿列方向延伸，所述第五连接段沿行方向延伸；
    所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第三连接段在基底上的正投影与第一发光器件的第一电极和所述第二阳极连接线的第五连接段在基底上的正投影部分交叠，所述第二阳极连接线的第四连接段在基底上的正投影与第二像 素驱动电路的阳极连接过孔和第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第五连接段在基底上的正投影与所述第一发光器件的第一电极和第二发光器件的第一电极部分交叠；
    所述第二阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的不同侧。
  8. 根据权利要求4所述的显示基板，其中，所述第二阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第一阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈直角设置，所述第四连接段沿列方向延伸，所述第五连接段沿行方向延伸；
    所述第一阳极连接线的第四连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔和第二发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第五连接段在基底上的正投影与第一发光器件的第一电极、第二发光器件的第一电极和第二阳极连接线的第三连接段在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第三连接段在基底上的正投影与第二发光器件的第一电极在基底上的正投影部分交叠；
    所述第一阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的不同侧。
  9. 根据权利要求所述的显示基板，其中，所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影不交叠。
  10. 根据权利要求9所述的显示基板，其中，所述第一阳极连接线和所述第二阳极连接线均包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接；
    所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第三连接段在基底上的正投影与第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第三连接段在基底上的正投影与第二发光器件的第一电极在基底上的正投影部分交叠；
    所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的同一侧。
  11. 根据权利要求9所述的显示基板，其中，所述第一阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且 分别与第二连接段电连接，所述第二阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈锐角设置，所述第四连接段沿列方向延伸；
    所述第一阳极连接线的第一连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第一阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠或者不交叠，所述第一阳极连接线的第三连接段在基底上的正投影与第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第四连接段在基底上的正投影与所述第二像素驱动电路的阳极连接过孔和第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第五连接段在基底上的正投影与第二发光器件的第一电极部分交叠；
    所述第二阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别位于所述第三像素驱动电路的阳极连接过孔的不同侧。
  12. 根据权利要求9所述的显示基板，其中，所述第二阳极连接线包括：第一连接段、第二连接段和第三连接段，所述第一连接段和所述第三连接段沿列方向延伸，所述第二连接段沿行方向延伸，所述第一连接段和所述第三连接段位于所述第二连接段的同一侧，且分别与第二连接段电连接，所述第一阳极连接线包括：第四连接段和第五连接段，所述第四连接段和所述第五连接段连接，且呈锐角设置，所述第四连接段沿列方向延伸；
    所述第一阳极连接线的第四连接段在基底上的正投影与第一像素驱动电路的阳极连接过孔和第二发光器件的第一电极在基底上的正投影部分交叠，所述第一阳极连接线的第五连接段在基底上的正投影与第一发光器件的第一电极在基底上的正投影部分交叠，所述第二阳极连接线的第一连接段在基底上的正投影与第二像素驱动电路的阳极连接过孔在基底上的正投影部分交叠，所述第二阳极连接线的第二连接段在基底上的正投影与第三发光器件的第一电极在基底上的正投影部分交叠或者不交叠，所述第二阳极连接线的第三连接段在基底上的正投影与第二发光器件的第一电极在基底上的正投影部分交叠；
    所述第一阳极连接线在基底上的正投影与第三发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线和所述第二阳极连接线分别所述第三像素驱动电路的阳极连接过孔的不同侧。
  13. 根据权利要求3至12任一项所述的显示基板，其中，第4a-3列像素驱动电路为第一像素驱动电路，第4a-1列像素驱动电路为第二像素驱动电路；
    第b行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第b行第d列的发光器件的第一电极在基底上的正投影部分交叠，第c行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第c行第d列发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线分别与第c行第4a-3列像素驱动电路和第c行第4a-1列发光器件的第一电极电连接，所述第二阳极连接线通分别与第c行第4a-1列像素驱动电路和第c行第4a-3列发光器件的第一电极电连接，其中，1≤b≤N，且为奇数，1≤c≤N，且为偶数，1≤d≤M，且d为奇数。
  14. 根据权利要求13所述的显示基板，其中，位于奇数行的第一发光器件的第一电极的面积大于位于偶数行的第一发光器件的第一电极的面积，位于奇数行的第二发光器件的第一电极的面积大于位于偶数行的第二发光器件的第一电极的面积。
  15. 根据权利要求3至12任一项所述的显示基板，其中，第4a-3列像素驱动电路为第二像素驱动电路，第4a-1列像素驱动电路为第一像素驱动电路；
    第c行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第c行第d列的发光 器件的第一电极在基底上的正投影部分交叠，第b行第d列像素驱动电路的阳极连接过孔在基底上的正投影与第b行第d列发光器件的第一电极在基底上的正投影不交叠，所述第一阳极连接线分别与第b行第4a-1列像素驱动电路和第b行第4a-3列发光器件的第一电极电连接，所述第二阳极连接线分别与第b行第4a-3列像素驱动电路和第b行第4a-1列发光器件的第一电极电连接，其中，1≤b≤N，且为奇数，1≤c≤N，且为偶数，1≤d≤M，且d为奇数。
  16. 根据权利要求15所述的显示基板，其中，位于偶数行的第一发光器件的第一电极的面积大于位奇数行的第一发光器件的第一电极的面积，位于偶数行的第二发光器件的第一电极的面积大于位于奇数行的第二发光器件的第一电极的面积。
  17. 根据权利要求14或16所述的显示基板，其中，所述基底还包括：第二驱动区，所述第一驱动区包括：相对设置的第一侧和第二侧，所述第二驱动区位于所述第一驱动区的第一侧和第二侧中的至少一侧，且所述第二驱动区还设置有栅极驱动电路和发光器件，所述栅极驱动电路被配置为向像素驱动电路提供控制信号；
    至少一条第一阳极连接线分别与位于第一驱动区的第一像素驱动电路和位于第二驱动区的至少一个第一发光器件的第一电极电连接，至少一条第二阳极连接线分别与位于第一驱动区的第二像素驱动电路和位于第二驱动区的至少一个第二发光器件的第一电极电连接。
  18. 根据权利要求17所述的显示基板，其中，当所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影部分交叠时，所述第一阳极连接线和所述第二阳极连接线异层设置，当所述第一阳极连接线在基底上的正投影与所述第二阳极连接线在基底上的正投影不交叠时，所述第一阳极连接线和所述第二阳极连接线异层设置或者同层设置；
    所述第一阳极连接线包括：金属线或者透明导电线，所述第二阳极连接线包括：金属线或者透明导电层。
  19. 根据权利要求18所述的显示基板，其中，所述显示基板包括：设置在所述基底上的驱动结构层和发光结构层，所述驱动结构层设置有像素驱动电路、栅极驱动电路和数据信号线，所述发光结构层设置有发光器件；所述驱动结构层包括：依次叠设在所述基底上的第一导电层、第二导电层和第三导电层，所述发光结构层包括：第四导电层、有机发光层和第五导电层；
    所述第三导电层至少包括：多个晶体管的源漏电极和数据信号线；
    所述第四导电层至少包括：发光器件的第一电极；
    所述第一阳极连接线位于所述第三导电层或者第四导电层，所述第二阳极连接线位于所述第三导电层或者第四导电层。
  20. 根据权利要求19所述的显示基板，其中，所述第三导电层为单层结构或者多层结构；
    当所述第三导电层为多层结构时，所述第三导电层包括：第一子导电层和第二子导电层，或者第三导电层包括：第一子导电层、第二子导电层和第三子导电层，其中，第一子导电层和第二子导电层为金属导电层，第三子导电层包括：金属导电层或者透明导电层；
    当所述第三子导电层为透明导电层时，第三子导电层的数量为至少一个；
    当所述第三导电层为多层结构时，所述第一阳极连接线和所述第二阳极连接线位于所述第三导电层的至少一个膜层中。
  21. 根据权利要求1所述的显示基板，其中，所述第一发光器件发射红色或者蓝色中的一种颜色的光线，所述第二发光器件发射为红色或者蓝色中的另一种颜色的光线，所述第三发光器件发射绿色光线。
  22. 一种显示装置，包括：如权利要求1至21任一项所述的显示基板。
PCT/CN2024/095268 2023-05-26 2024-05-24 一种显示基板和显示装置 WO2024245148A1 (zh)

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* Cited by examiner, † Cited by third party
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US20150015472A1 (en) * 2013-07-09 2015-01-15 Akira Nakayama Display panel driving apparatus
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CN114784082A (zh) * 2022-06-15 2022-07-22 京东方科技集团股份有限公司 显示基板和显示装置
CN115377169A (zh) * 2022-08-31 2022-11-22 京东方科技集团股份有限公司 显示基板和显示装置
CN115988916A (zh) * 2021-10-14 2023-04-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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US20150015472A1 (en) * 2013-07-09 2015-01-15 Akira Nakayama Display panel driving apparatus
CN115988916A (zh) * 2021-10-14 2023-04-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114120905A (zh) * 2021-11-12 2022-03-01 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
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