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WO2023016341A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023016341A1
WO2023016341A1 PCT/CN2022/110291 CN2022110291W WO2023016341A1 WO 2023016341 A1 WO2023016341 A1 WO 2023016341A1 CN 2022110291 W CN2022110291 W CN 2022110291W WO 2023016341 A1 WO2023016341 A1 WO 2023016341A1
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WO
WIPO (PCT)
Prior art keywords
electrode
display substrate
signal line
layer
orthographic projection
Prior art date
Application number
PCT/CN2022/110291
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English (en)
French (fr)
Inventor
方飞
刘珂
石领
卢辉
王铸
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/293,783 priority Critical patent/US20250126988A1/en
Publication of WO2023016341A1 publication Critical patent/WO2023016341A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED

Definitions

  • This article relates to but not limited to the field of display technology, and specifically relates to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • the present disclosure provides a display substrate, including a plurality of circuit units, scanning signal lines for supplying scanning signals to the circuit units, and first power lines for supplying power signals; at least one circuit unit includes a pixel driving circuit, and The pixel drive circuit includes a first shielding electrode connected to the first power supply line, the orthographic projection of the first shielding electrode on the display substrate plane and the orthographic projection of the scanning signal line on the display substrate plane overlap at least partially.
  • the pixel driving circuit further includes a driving transistor and a first plate and a second plate forming a storage capacitor, the orthographic projection of the first plate on the plane of the display substrate is the same as that of the Orthographic projections of the second plate on the plane of the display substrate at least partially overlap; the first shielding electrode is connected to the second plate, and the second plate is connected to the first power line through a via hole .
  • the pixel driving circuit further includes a compensation transistor and a first connection electrode, the first end of the first connection electrode is connected to the first region of the active layer in the compensation transistor through a via hole, The second end of the first connection electrode is connected to the first electrode plate through a via hole, and the orthographic projection of the first connection electrode on the plane of the display substrate is the same as that of the scanning signal line on the plane of the display substrate.
  • the orthographic projections on are at least partially overlapping.
  • the orthographic projection of the first shielding electrode on the plane of the display substrate and the orthographic projection of the scanning signal line on the plane of the display substrate have a first overlapping area
  • the first connection The orthographic projection of the electrode on the plane of the display substrate and the orthographic projection of the scanning signal line on the plane of the display substrate have a second overlapping area, and the second overlapping area at least partially overlaps with the first overlapping area .
  • the second overlapping area is located within the range of the first overlapping area.
  • the first overlapping region has a first width
  • the second overlapping region has a second width
  • the first width is greater than the second width
  • the first width and the second width is the dimension in the first direction
  • the second width is 40% to 60% of the first width L1.
  • the first width is 2.5 ⁇ m to 3.0 ⁇ m.
  • the second width is 1.3 ⁇ m to 2.0 ⁇ m.
  • the main body portion of the scanning signal line extends along a first direction
  • the main body portion of the first shielding electrode extends along a second direction
  • the first direction crosses the second direction
  • the first shielding electrode is arranged on the side of the second pole plate close to the scanning signal line, and the orthographic projection of the end of the first shielding electrode away from the second pole plate on the plane of the display substrate is the same as the Orthographic projections of the scanning signal lines on the plane of the display substrate at least partially overlap.
  • the first shielding electrode and the second electrode plate are arranged in the same layer and are connected to each other as an integral structure.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged on a base, between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer are all provided with An insulating layer; the first shielding electrode, the first connecting electrode and the scanning signal line are located in different conductive layers.
  • the scanning signal line is disposed in the first conductive layer
  • the first shielding electrode is disposed in the second conductive layer
  • the first connection electrode is disposed in the third conductive layer. layer.
  • the semiconductor layer includes an active layer of a plurality of transistors in the pixel driving circuit
  • the first conductive layer includes a scanning signal line, gate electrodes of a plurality of transistors, and a first electrode of a storage capacitor plate
  • the second conductive layer includes the first shielding electrode and the second plate of the storage capacitor
  • the third conductive layer includes the data signal line and the first connection electrode
  • the fourth conductive layer includes the first power supply Wire.
  • the second conductive layer further includes a second shielding electrode
  • the second shielding electrode includes a first sub-electrode and a second sub-electrode connected to each other, and the first sub-electrode is on the substrate.
  • the orthographic projection at least partially overlaps the orthographic projection of the data signal line on the substrate, and the orthographic projection of the second sub-electrode on the substrate is located between the orthographic projection of the data signal line on the substrate and the first connection electrode. Between orthographic projections on the base.
  • the second shielding electrode is connected to the first power line through a via hole.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate, including:
  • a plurality of circuit units, a scanning signal line for supplying scanning signals to the circuit units, and a first power supply line for supplying power signals are formed on the substrate, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit includes a pixel driving circuit that is compatible with the first A power line is connected to the first shielding electrode, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the scanning signal line on the substrate.
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 5 is a working timing diagram of a pixel driving circuit
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure.
  • Fig. 8a is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure
  • Figure 8b is a schematic plan view of the first conductive layer in Figure 8a;
  • Fig. 9a is a schematic diagram of forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • Figure 9b is a schematic plan view of the second conductive layer in Figure 9a;
  • Fig. 10a is a schematic diagram of forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure
  • Fig. 10b is a schematic plan view of a plurality of via holes in Fig. 10a;
  • Fig. 11a is a schematic diagram after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • Figure 11b is a schematic plan view of the third conductive layer in Figure 11a;
  • Fig. 12a is a schematic diagram of forming a first flat layer pattern according to an exemplary embodiment of the present disclosure
  • Figure 12b is a schematic plan view of a plurality of vias in Figure 12a;
  • FIG. 13a is a schematic diagram of the present disclosure showing that the fourth conductive layer pattern is formed on the substrate
  • Figure 13b is a schematic plan view of the fourth conductive layer in Figure 13a;
  • FIG. 14 is a schematic diagram of forming a second flat layer pattern according to an exemplary embodiment of the present disclosure.
  • 15 is a schematic diagram of an exemplary embodiment of the present disclosure after forming an anode pattern
  • FIG. 16 is a schematic diagram of a patterned pixel definition layer according to an exemplary embodiment of the present disclosure.
  • 51 first power line
  • 52 anode connection electrode
  • 61 anode
  • 103 light-emitting structure layer
  • 104 encapsulation layer
  • 210 transistor
  • 211 storage capacitor
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged, and “source terminal” and “drain terminal” can be interchanged.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit and receive electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scanning driver, a light emitting driver, a plurality of scanning signal lines, a plurality of data signal lines, a plurality of light emitting signal lines, and a pixel array.
  • the driver, the scanning driver and the light emitting driver are connected, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scanning driver is respectively connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo) connection.
  • D1 to Dn data signal lines
  • S1 to Sm scanning signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one pixel driving circuit.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver.
  • the driver can supply a clock signal, an emission stop signal, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light emitting driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting driver can be configured in the form of a shift register, and can generate emission signals in a manner of sequentially transmitting emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits light of the first color, and a first sub-pixel P1 that emits light of the second color.
  • the second sub-pixel P2 and a third sub-pixel P3 that emit light of a third color may each include a circuit unit and a light emitting device, and the circuit unit may include a scanning signal line, a data signal line, a light emitting signal line and a pixel driving circuit , the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line, and output it to the light emitting device corresponding current.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the third sub-pixel P3 It may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be a rectangle, a rhombus, a pentagon or a hexagon, and the three sub-pixels may be arranged horizontally, vertically or in characters.
  • at least one pixel unit P may include four sub-pixels, which is not limited in the present disclosure.
  • Fig. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base, and a light-emitting structure layer 103 disposed on the base 102.
  • Layer 103 is away from the encapsulation layer 104 on the side of the substrate.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of signal lines and a plurality of circuit units, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and storage capacitors.
  • FIG. 3 only one driving transistor 210 and one storage capacitor are used.
  • Capacitor 211 is taken as an example for illustration.
  • the light-emitting structure layer 103 may include a plurality of light-emitting devices, at least one light-emitting device may include an anode 301, an organic light-emitting layer 303 and a cathode 304, the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole, and the organic light-emitting layer 303 is connected to the anode 301 , the cathode 304 is connected to the organic light-emitting layer 303 , and the organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304 .
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short), and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together
  • all The hole blocking layer of the sub-pixels can be a common layer connected together, and the light-emitting layer and the electron blocking layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected with 7 signal lines (data signal line D, first scan The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power line VDD and the second power line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor
  • the first pole of the second transistor T2, the control pole of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3 and the second terminal of the storage capacitor C.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 When a turn-on level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the light emitting device may be an OLED comprising a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode), or may be a QLED comprising a stacked first pole (anode) , a quantum dot light-emitting layer and a second pole (cathode).
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first transistor T1 to the seventh transistor T7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to realize low-frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 5 is a working timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 4.
  • the pixel driving circuit in FIG. 4 includes seven transistors (the first transistor T1 to the seventh transistor T7) and one storage capacitor C, All transistors are P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is supplied to the second node N2, and charge the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of a circuit unit.
  • the display substrate in a plane parallel to the display substrate, the display substrate may include a plurality of circuit units and a plurality of signal lines, and the plurality of circuit units may be arranged in sequence along the first direction X to form a row of circuit units.
  • the circuit units can be arranged sequentially along the second direction Y to form a circuit unit column, a plurality of circuit unit rows and a plurality of circuit unit columns form a circuit unit array arranged in an array, and the first direction X crosses the second direction Y.
  • the plurality of signal lines may at least include a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, an initial signal line 31, a data signal line 44, and a first power supply line 51
  • at least One circuit unit may include a pixel driving circuit.
  • the main parts of the first scanning signal line 21, the second scanning signal line 22, the light emission control line 23 and the initial signal line 31 can extend along the first direction X
  • the main parts of the data signal line 44 and the first power line 51 can extend along the first direction X. extending along the second direction Y.
  • a extending along the B direction means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the B direction, and the main part extends along the B The length extending in one direction is greater than the length extending in the other direction of the minor portion.
  • the first scan signal line 21 and the second scan signal line 22 are configured to provide a scan signal to the pixel drive circuit
  • the light emission control line 23 is configured to provide a light emission control signal to the pixel drive circuit
  • the initial signal line 31 is configured to provide an initial signal to the pixel drive circuit
  • the data signal line 44 is configured to provide a data signal to the pixel drive circuit
  • the first power line 51 is configured to provide a power signal to the pixel drive circuit.
  • the pixel driving circuit may include a plurality of transistors and a storage capacitor
  • the plurality of transistors may include a first transistor T1 to a seventh transistor T7
  • the third transistor T3 is a driving transistor
  • the storage capacitor may include a first plate 24 and the second pole plate 32, the orthographic projection of the first pole plate 24 on the display substrate plane and the orthographic projection of the second pole plate 32 on the display substrate plane at least partially overlap.
  • the gate electrode of the first transistor T1 is connected to the second scanning signal line 22, the first electrode of the first transistor T1 is connected to the initial signal line 31, and the second electrode of the first transistor T1 is respectively connected to the second The first electrode of the transistor T2, the gate electrode of the third transistor T3 and the first electrode plate 24 of the storage capacitor are connected.
  • the gate electrode of the second transistor T2 is connected to the first scanning signal line 21, and the first pole of the second transistor T2 is respectively connected to the second pole of the first transistor T1, the gate electrode of the third transistor T3 and the first plate of the storage capacitor. 24, and the second pole of the second transistor T2 is respectively connected with the second pole of the third transistor T3 and the first pole of the sixth transistor T6.
  • the gate electrode of the third transistor T3 is respectively connected with the second pole of the first transistor T1, the first pole of the second transistor T2 and the first plate 24 of the storage capacitor, and the first pole of the third transistor T3 is connected with the fourth transistor respectively.
  • the second pole of T4 is connected to the second pole of the fifth transistor T5, and the second pole of the third transistor T3 is respectively connected to the second pole of the second transistor T2 and the first pole of the sixth transistor T6.
  • the gate electrode of the fourth transistor T4 is connected to the first scanning signal line 21, the first pole of the fourth transistor T4 is connected to the data signal line 44, and the second pole of the fourth transistor T4 is respectively connected to the first pole and the third transistor T3.
  • the second pole of the fifth transistor T5 is connected.
  • the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line 23
  • the first pole of the fifth transistor T5 is respectively connected to the first power supply line 51 and the second plate 32 of the storage capacitor
  • the second pole of the fifth transistor T5 is respectively connected to the
  • the first pole of the third transistor T3 is connected to the second pole of the fourth transistor T4.
  • the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line 23
  • the first pole of the sixth transistor T6 is respectively connected to the second pole of the second transistor T2 and the second pole of the third transistor T3, and the second pole of the sixth transistor T6
  • the poles are respectively connected with the second pole of the seventh transistor T7 and the first pole of the light emitting device.
  • the gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22, the first pole of the seventh transistor T7 is connected to the initial signal line 31, and the second pole of the seventh transistor T7 is respectively connected to the second pole of the sixth transistor T6 and The first pole of the light emitting device is connected.
  • the first plate 24 of the storage capacitor is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the gate electrode of the third transistor T3, and the second electrode of the storage capacitor
  • the board 32 is connected to the first power line 51 and the first pole of the fifth transistor T5, respectively.
  • the first plate 24 of the storage capacitor may serve as the gate electrode of the third transistor T3.
  • the pixel driving circuit may include a first shielding electrode 34, and the first shielding electrode 34 is configured to shield the influence of the voltage jump of the scan signal on the third transistor T3, so as to avoid the influence of the voltage jump of the scan signal on the driving transistor T3. Performance, improve the display effect.
  • the first shielding electrode 34 may be connected to the first power line 51, and the orthographic projection of the first shielding electrode 34 on the plane of the display substrate is at least at least equal to the orthographic projection of the first scanning signal line 21 on the plane of the display substrate. partially overlap.
  • the pixel driving circuit may include a first connection electrode 41 configured as a second pole of the first transistor T1 and a first pole of the second transistor T2.
  • the body portion of the first connection electrode 41 may extend along the second direction Y. Referring to FIG.
  • the first end of the first connection electrode 41 is connected to the first region of the active layer in the second transistor T2 through a via hole, and the second end of the first connection electrode 41 is connected to the first plate 24 (ie, the third transistor T2) through a via hole.
  • the gate electrode of T3 is connected, and the orthographic projection of the first connecting electrode 41 on the plane of the display substrate overlaps at least partially with the orthographic projection of the first scanning signal line 21 on the plane of the display substrate.
  • the orthographic projection of the first shielding electrode 34 on the plane of the display substrate and the orthographic projection of the first scanning signal line 21 on the plane of the display substrate have a first overlapping area
  • the first connecting electrode 41 has a first overlapping area on the plane of the display substrate.
  • the orthographic projection on , and the orthographic projection of the first scanning signal line 21 on the display substrate plane have a second overlapping area, and the second overlapping area at least partially overlaps with the first overlapping area.
  • the second overlapping area is located within the range of the first overlapping area.
  • the first shielding electrode 34 is connected to the second plate 32 of the storage capacitor, and the second plate 32 of the storage capacitor is connected to the first power line 51 through a via hole.
  • the first shielding electrode 34 may be in the shape of a strip whose main body extends along the second direction Y, and is disposed on the side of the second electrode plate 32 close to the first scanning signal line 21 , the first shielding electrode 34
  • the orthographic projection of the end away from the second electrode plate 32 on the plane of the display substrate overlaps at least partially the orthographic projection of the first scanning signal line 21 on the plane of the display substrate.
  • the pixel driving circuit may include a second shielding electrode 35, and the second shielding electrode 35 is configured to shield the impact of the data voltage jump on key nodes, so as to prevent the data voltage jump from affecting the key nodes of the pixel driving circuit. Potential, improve the display effect.
  • the second shielding electrode 35 may be connected to the first power line 51, and the orthographic projection of the second shielding electrode 35 on the substrate is at least at least equal to the orthographic projection of the fourth active layer of the fourth transistor T4 on the substrate. partially overlap.
  • the second shielding electrode 35 may include a first sub-electrode and a second sub-electrode connected to each other, and the orthographic projection of the first sub-electrode on the substrate may be at least at least the same as the orthographic projection of the data signal line 44 on the substrate. Partially overlapping, the orthographic projection of the second sub-electrode on the substrate is located between the orthographic projection of the data signal line 44 on the substrate and the orthographic projection of the first connecting electrode 41 on the substrate.
  • the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate in a plane perpendicular to the display substrate.
  • the semiconductor layer may include active layers of a plurality of transistors
  • the first conductive layer may include a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, a first plate 24 of a storage capacitor, and a plurality of transistors.
  • Gate electrode, the second conductive layer may include the initial signal line 31, the second plate 32 of the storage capacitor, the first shielding electrode 34 and the second shielding electrode 35
  • the third conductive layer may include the data signal line 44 and the first connection electrode 41.
  • the fourth conductive layer may include the first power line 51.
  • the first shielding electrode 34 and the second plate 32 of the storage capacitor disposed on the same layer are an integral structure connected to each other.
  • the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer
  • the first insulating layer is disposed between the base and the semiconductor layer
  • the second insulating layer is disposed between the base and the semiconductor layer.
  • the second insulating layer is arranged between the semiconductor layer and the first conductive layer
  • the third insulating layer is arranged between the first conductive layer and the second conductive layer
  • the fourth insulating layer is arranged between the second conductive layer and the third conductive layer
  • the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A , or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the manufacturing process of the display substrate may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate.
  • the semiconductor layer on the first insulating layer is shown in FIG. 7 .
  • the semiconductor layer of each circuit unit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17
  • the active layer 17 is an integral structure connected to each other.
  • the first active layer 11, the second active layer 12, the fourth active layer 14, and the seventh active layer 17 are located in a direction opposite to the second direction Y of the third active layer 13. side, the fifth active layer 15 and the sixth active layer 16 are located on one side of the third active layer 13 in the second direction Y, and the first active layer 11 and the seventh active layer 17 are located on the second active layer 12 and the side of the fourth active layer 14 away from the third active layer 13 .
  • the shape of the first active layer 11 may be "n"
  • the shape of the second active layer 12 may be "7”
  • the shape of the third active layer 13 may be "several”.
  • the shape of the fourth active layer 14 may be "I”
  • the shape of the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 11-1 of the first active layer 11 simultaneously functions as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 simultaneously
  • the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the fifth active layer 15
  • the second region 15-2 of the third active layer 13 the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15
  • the second region 13-2 of the third active layer 13 serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16 at the same time.
  • the second region 13-2 of the third active layer 13, the second region 12-2 of the second active layer 12, and the first region 16-1 of the sixth active layer 16 are connected to each other, and the sixth active layer
  • the second region 16 - 2 of 16 serves as the second region 17 - 2 of the seventh active layer 17 at the same time.
  • the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are separately disposed.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, and patterning the first conductive film through a patterning process to form
  • the second insulating layer covering the semiconductor layer pattern and the first conductive layer pattern disposed on the second insulating layer are shown in FIG. 8a and FIG. 8b, and FIG. 8b is a schematic plan view of the first conductive layer in FIG. 8a.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layer pattern of each circuit unit at least includes: a first scanning signal line 21 , a second scanning signal line 22 , a light emission control line 23 and a first plate 24 of a storage capacitor.
  • the main parts of the first scanning signal line 21 , the second scanning signal line 22 and the light emission control line 23 may extend along the first direction X, and the first scanning signal line 21 and the second scanning signal line 22 may Located on the side of the first pole plate 24 opposite to the second direction Y, the light emission control line 23 may be located on the side of the first pole plate 24 in the second direction Y, and the first pole plate 24 of the storage capacitor may be set in the first scan Between the signal line 21 and the light emission control line 23 .
  • the first pole plate 24 can be rectangular, and the corners of the rectangle can be chamfered. The projections have overlapping areas.
  • the first plate 24 may serve as a plate of the storage capacitor and a gate electrode of the third transistor T3 at the same time.
  • the overlapping area of the first scanning signal line 21 and the second active layer 12 serves as the gate electrode of the second transistor T2, and the first scanning signal line 21 is provided with The raised gate block 21 - 1 , the orthographic projection of the gate block 21 - 1 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate, forming a second transistor T2 with a double gate structure.
  • the area where the first scanning signal line 21 overlaps with the fourth active layer 14 is used as the gate electrode of the fourth transistor T4, and the area where the second scanning signal line 22 overlaps with the first active layer 11 is used as the first double gate structure.
  • the gate electrode of the transistor T1 the area where the second scanning signal line 22 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7.
  • the area where the emission control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5
  • the area where the emission control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6.
  • the semiconductor layer may be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the area blocked by the first conductive layer forms the first transistors T1 to the seventh In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are all conductorized.
  • forming the pattern of the second conductive layer may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, and forming The third insulating layer covering the first conductive layer and the pattern of the second conductive layer disposed on the third insulating layer are shown in FIG. 9a and FIG. 9b , and FIG. 9b is a schematic plan view of the second conductive layer in FIG. 9a .
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the second conductive layer pattern of each circuit unit at least includes: an initial signal line 31, a second plate 32 of a storage capacitor, a plate connection line 33, a first shielding electrode 34 and a second shield electrode 35 .
  • the main part of the initial signal line 31 may extend along the first direction X, the initial signal line 31 may be located on the side of the second scanning signal line 22 away from the first scanning signal line 21 , and the second electrode plate 32 As another plate of the storage capacitor, it is located between the first scanning signal line 21 and the light emission control line 23.
  • the first shielding electrode 34 can be located on the side of the second plate 32 close to the first scanning signal line 21.
  • the second shielding electrode 34 The electrode 35 may be located between the first scan signal line 21 (excluding the main part of the gate block 21 - 1 ) and the second scan signal line 22 .
  • the outline of the second pole plate 32 can be rectangular, the corners of the rectangle can be chamfered, and the orthographic projection of the second pole plate 32 on the base is the same as that of the first pole plate 24 on the base There is an overlapping area in the orthographic projection, and the first pole plate 24 and the second pole plate 32 form a storage capacitor of the pixel driving circuit.
  • an opening 36 is disposed on the second pole plate 32 , and the opening 36 may be located in the middle of the second pole plate 32 .
  • the opening 36 may be rectangular, so that the second pole plate 32 forms a ring structure.
  • the opening 36 exposes the third insulating layer covering the first pole plate 24 , and the orthographic projection of the first pole plate 24 on the base includes the orthographic projection of the opening 36 on the base.
  • the opening 36 is configured to accommodate the subsequently formed first via hole, the first via hole is located in the opening 36 and exposes the first electrode plate 24, so that the subsequently formed first connecting electrode is connected to the first electrode plate 24.
  • the plates 24 are connected.
  • the plate connecting wire 33 may be arranged on one side of the second polar plate 32 in the first direction X and on the opposite side of the first direction X, and the first end of the electrode plate connecting wire 33 is connected to this
  • the second pole plate 32 of the circuit unit is connected, and the second end of the pole plate connection line 33 extends along the first direction X or the opposite direction of the first direction X, and is connected to the second pole plate 32 of the adjacent circuit unit, that is,
  • the plate connecting wires 33 are configured to connect the second plates 32 of adjacent circuit units in a row of circuit units to each other.
  • the second pole plates of a plurality of circuit units in a circuit unit row can form an integrated structure connected to each other through the plate connection line 33, and the second plate of the integrated structure can be multiplexed as a power signal line To ensure that multiple second plates in one circuit unit row have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • the first shielding electrode 34 may be in the shape of a strip extending along the second direction Y, and may be disposed on the side of the second electrode plate 32 close to the first scanning signal line 21 and connected to the second electrode plate 32. 32 is an integral structure connected to each other.
  • the orthographic projection of the end of the first shielding electrode 34 away from the second electrode plate 32 on the substrate at least partially overlaps the orthographic projection of the first scanning signal line 21 on the substrate.
  • the first shielding electrode 34 is configured to shield the influence of the voltage jump of the first scanning signal on the third transistor T3, so as to prevent the performance of the driving transistor from being affected by the voltage jump of the first scanning signal and improve the display effect.
  • the first scanning signal line 21 whose body part extends along the first direction X has a width B in the overlapping area
  • the first shielding electrode 34 whose body part extends along the second direction Y has a width B in the overlapping area.
  • a width L1, a width B and a first width L1 refer to a dimension perpendicular to its extending direction.
  • the second shielding electrode 35 is configured to shield the influence of the data voltage jump on key nodes, avoiding the influence of the data voltage jump on the potential of the key nodes of the pixel driving circuit, and improving the display effect.
  • the shape of the second shielding electrode 35 may be "L", and may include a first sub-electrode 35-1 and a second sub-electrode 35-2, and the first end of the first sub-electrode 35-1 is located away from the first shielding electrode 34.
  • the second end of the first sub-electrode 35-1 is connected to the first end of the second sub-electrode 35-2, and the second end of the second sub-electrode 35-2 is along the After extending in the direction opposite to the second direction Y, it is located on a side of the first initial line 31 close to the first shielding electrode 34 .
  • the orthographic projection of the first sub-electrode 35-1 on the substrate may at least partially overlap with the orthographic projection of the fourth active layer 14 on the substrate, and the orthographic projection of the first sub-electrode 35-1 on the substrate The projection may at least partially overlap with the orthographic projection of the subsequently formed data signal lines on the substrate.
  • the orthographic projection of the second sub-electrode 35-2 on the substrate may be located between the orthographic projection of the subsequently formed data signal line on the substrate and the orthographic projection of the subsequently formed first connection electrode on the substrate. .
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • the fourth insulating layer is provided with a plurality of via holes, as shown in FIG. 10a and FIG. 10b , and FIG. 10b is a schematic plan view of the plurality of via holes in FIG. 10a .
  • the multiple vias of each circuit unit at least include: a first via V1, a second via V2, a third via V3, a second via V2, and a third via V3 , the fourth via hole V4, the fifth via hole V5, the eighth via hole V8 and the sixth via hole V6.
  • the orthographic projection of the first via hole V1 on the substrate may be within the range of the orthographic projection of the opening 36 on the substrate, and the fourth insulating layer and the third insulating layer in the first via hole V1 are covered. etched away to expose the surface of the first pole plate 24 .
  • the first via hole V1 is configured to connect the subsequently formed first connecting electrode (the second pole of the first transistor T1 and the first pole of the second transistor T2 ) to the first plate 24 through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate may be within the range of the orthographic projection of the sixth active layer on the substrate, and the fourth insulating layer, the third The insulating layer and the second insulating layer are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer).
  • the second via hole V2 is configured to connect the second pole of the sixth transistor T6 (the second pole of the seventh transistor T7 ) formed subsequently to the second region of the sixth active layer through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate may be within the range of the orthographic projection of the fourth active layer on the substrate, and the fourth insulating layer, the third The insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer.
  • the third via hole V3 is configured to connect the subsequently formed data signal line to the first region of the fourth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate may be within the range of the orthographic projection of the second active layer on the substrate, and the fourth insulating layer, the third The insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer).
  • the fourth via hole V4 is configured to connect the subsequently formed first connection electrode (the second pole of the first transistor T1 and the first pole of the second transistor T2 ) to the first region of the second active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate may be within the range of the orthographic projection of the seventh active layer on the substrate, and the fourth insulating layer, the third The insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer (which is also the first region of the first active layer).
  • the fifth via hole V5 is configured to connect the first electrode of the subsequently formed seventh transistor T7 (the first electrode of the first transistor T1 ) to the first region of the seventh active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate may be within the range of the orthographic projection of the initial signal line 31 on the substrate, and the fourth insulating layer in the sixth via hole V6 is etched away. , exposing the surface of the initial signal line 31 .
  • the sixth via hole V6 is configured to connect the first pole of the subsequently formed seventh transistor T7 (also the first pole of the first transistor T1 ) to the initial signal line 31 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film by a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer as shown in Figure 11a and Figure 11b, Figure 11b is a schematic plan view of the third conductive layer in Figure 11a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 first source-drain metal
  • the third conductive layer at least includes: a first connection electrode 41 , a second connection electrode 42 , a third connection electrode 43 and a data signal line 44 .
  • the body portion of the first connection electrode 41 may extend along the second direction Y. Referring to FIG. The first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) through the fourth via hole V4, and the second end thereof is connected to the second region of the first active layer through the first via hole V1.
  • the first plate 24 is connected such that the first plate 24 (the gate electrode of the third transistor T3), the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 41 may function as a second pole of the first transistor T1 and a first pole of the second transistor T2.
  • the orthographic projection of the first connection electrode 41 on the substrate at least partially overlaps the orthographic projection of the first scanning signal line 21 on the substrate, and the orthographic projection of the first connection electrode 41 on the substrate overlaps with the first The orthographic projections of shield electrodes 34 on the substrate at least partially overlap.
  • the first end of the second connection electrode 42 is connected to the initial signal line 31 through the sixth via hole V6, and the second end thereof is connected to the first region ( Also the first region of the first active layer) is connected so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the initial signal line 31 .
  • the second connection electrode 42 may function as a first pole of the first transistor T1 and a first pole of the seventh transistor T7.
  • the third connection electrode 43 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the second via hole V2, so that the second region of the sixth transistor T6 The pole and the second pole of the seventh transistor T7 have the same potential.
  • the third connection electrode 43 may function as a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7.
  • the third connection electrode 43 is configured to be connected to a subsequently formed anode connection electrode.
  • the body portion of the data signal line 44 may extend along the second direction Y. Referring to FIG.
  • the data signal line 44 is connected to the first region of the fourth active layer through the third via hole V3, and writes the data signal into the first electrode of the fourth transistor T4.
  • the first scanning signal line 21 whose body part extends along the first direction X has a width B in the overlapping area
  • the first connection electrode 41 whose body part extends along the second direction Y has a width B in the overlapping area.
  • the two width L2, the width B and the second width L2 refer to the dimension perpendicular to the extending direction thereof.
  • the second overlapping area A2 may be located within the range of the first overlapping area A1, that is, the outline of the first overlapping area A1 may include the outline of the second overlapping area A2.
  • the first width L1 may be greater than or equal to the second width L2, that is, the area of the first overlapping area A1 may be greater than or equal to the area of the second overlapping area A2.
  • the second width L2 may be about 40% to 60% of the first width L1.
  • the first width L1 may be about 2.5 ⁇ m to 3.0 ⁇ m
  • the second width L2 may be about 1.3 ⁇ m to 2.0 ⁇ m.
  • the first shielding electrode 34 in a plane parallel to the substrate, can block the overlapping area of the first connection electrode 41 and the first scanning signal line 21, and in a plane perpendicular to the substrate, the first shielding electrode 34 The electrode 34 is located between the first scanning signal line 21 and the first connection electrode 41 . Since the first shielding electrode 34 is connected to the subsequently formed first power supply line, the first shielding electrode 34 can effectively shield the influence of the voltage jump of the scanning signal on the first scanning signal line 21 on the first connecting electrode 41, thereby effectively avoiding the first connecting electrode 41. The impact of the voltage jump of the scanning signal on the scanning signal line 21 on the gate electrode of the third transistor T3 ensures the performance of the third transistor T3 and improves the display effect.
  • the second shielding electrode 35 can effectively shield the impact of the data voltage jump on the key nodes in the pixel driving circuit, avoiding the data voltage jump from affecting the potential of the key nodes in the pixel driving circuit, and improving the display effect.
  • the second shielding electrodes 35 in adjacent circuit units in the first direction X may be connected to each other to reduce resistance.
  • Forming a first flat layer pattern may include: coating the first planar film on the substrate on which the foregoing pattern is formed, and patterning the first planar film by a patterning process to form a covering third conductive layer.
  • the first flat layer is provided with a plurality of via holes on the first flat layer, as shown in FIG. 12a and FIG. 12b , and FIG. 12b is a schematic plan view of the plurality of via holes in FIG. 12a .
  • the plurality of vias of each circuit unit at least include an eleventh via V11 , a twelfth via V12 , a thirteenth via V13 and a fourteenth via V14 .
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the third connecting electrode 43 on the substrate, and the first planar layer inside the eleventh via hole V11 is removed. , exposing the surface of the third connection electrode 43 .
  • the eleventh via hole V11 is configured such that the subsequently formed anode connection electrode is connected to the third connection electrode 43 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate, and the first flat layer, the second The four insulating layers, the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer.
  • the twelfth via hole V12 is configured to connect the subsequently formed first power line to the first region of the fifth active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate may be within the range of the orthographic projection of the second plate 32 on the substrate, and the first flat layer and the The fourth insulating layer is etched away, exposing the surface of the second pole plate 32 .
  • the thirteenth via hole V13 is configured to connect the subsequently formed first power line to the second plate 32 through the via hole.
  • the thirteenth vias V13 may include multiple, and the plurality of thirteenth vias V13 may be arranged in sequence along the second direction Y, so as to increase the connection between the first power line and the second plate 32 reliability.
  • the orthographic projection of the fourteenth via hole V14 on the substrate may be within the range of the orthographic projection of the second shielding electrode 35 on the substrate, and the first planar layer and the The fourth insulating layer is etched away, exposing the surface of the second shielding electrode 35 .
  • the fourteenth via hole V14 is configured to connect the subsequently formed first power line to the second shielding electrode 35 through the via hole.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film by a patterning process, and forming a layer disposed on the first planar layer.
  • FIG. 13b is a schematic plan view of the fourth conductive layer in FIG. 13a.
  • the fourth conductive layer at least includes: a first power line 51 and an anode connection electrode 52 .
  • a body portion of the first power line 51 may extend along the second direction Y, and the first power line 51 may be located between the first connection electrode 41 and the data signal line 44 .
  • the first power line 51 is connected to the first region of the fifth active layer through the twelfth via hole V12 on the one hand, connected to the second electrode plate 32 through the thirteenth via hole V13 on the other hand, and connected to the second electrode plate 32 through the 10th via hole V13 on the other hand.
  • the four vias V14 are connected to the second shielding electrode 35, so that the second pole plate 32, the first shielding electrode 34 and the second shielding electrode 35 have the same potential as the first power line 51, and the first power signal is written into the second shielding electrode.
  • the anode connection electrode 52 may be rectangular and connected to the third connection electrode 43 through the eleventh via hole V11. Since the third connection electrode 43 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the anode connection electrode 52 is connected to the sixth active layer through the third connection electrode 43. The second region of the source layer (also the second region of the seventh active layer) is connected.
  • the first power line 51 may be a straight line of unequal width.
  • the side of the first power line 51 close to the data signal line 44 may be provided with a first groove, and the side of the first power line 51 close to the first connection electrode 41 may be provided with a second groove.
  • the first power line 51 adopts a straight line with variable width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.
  • Forming a second flat layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, and patterning the second planar film by a patterning process to form a covering fourth conductive layer.
  • the second flat layer is provided with via holes, as shown in FIG. 14 .
  • the via hole of each circuit unit includes at least the twenty-first hole V21 .
  • the orthographic projection of the twenty-first hole V21 on the substrate may be within the range of the orthographic projection of the anode connection electrode 52 on the substrate, and the second flat layer in the twenty-first hole V21 is removed. , exposing the surface of the anode connection electrode 52 .
  • the twenty-first hole V21 is configured such that a subsequently formed anode is connected to the anode connection electrode 52 through the via hole.
  • the driving circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a light emission control circuit connected to the pixel driving circuit. line, initial signal line, data signal line and first power line.
  • the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a Four insulating layers, a third conductive layer, a first flat layer, a fourth conductive layer and a second flat layer.
  • a light emitting structure layer may be prepared on the driving circuit layer, and the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode pattern may include: depositing a fifth conductive film on the substrate on which the foregoing pattern is formed, patterning the fifth conductive film by a patterning process, and forming an anode disposed on the second planar layer 61 patterns, as shown in Figure 15.
  • the anode 61 can be connected to the anode connection electrode 52 through the twenty-first hole V21 . Since the anode connection electrode 52 is connected with the third connection electrode 43 as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 through the via hole, the anode 61 can pass through the anode connection electrode 52 and the third connection electrode 43 The connection with the sixth transistor T6 and the seventh transistor T7 realizes that the pixel driving circuit can drive the light emitting device to emit light.
  • the anode 61 may include an anode body part and a plurality of protrusions, the shape of the anode body part may be a rectangle with rounded corners, the plurality of protrusions may include a first protrusion and a second protrusion, and the second protrusion may include a first protrusion and a second protrusion. Both the first protrusion and the second protrusion are connected to the main body of the anode.
  • the first protrusion may be a rectangle protruding toward the gate electrode of the second transistor T2, configured to adjust the parasitic capacitance of key nodes in the pixel driving circuit, and reduce the difference between the parasitic capacitances of key nodes in adjacent circuit units, so as to Reduce the brightness difference and improve the display effect.
  • the second protrusion may be a rectangle protruding toward the anode connection electrode 52 and configured to be connected to the anode connection electrode 52 through the twenty-first hole V21.
  • Forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process, forming a pixel definition layer pattern, and the pixel definition layer
  • the pattern may include pixel openings 71 exposing the anodes 61, as shown in FIG. 16 .
  • the subsequent preparation process may include: forming an organic light-emitting layer by evaporation or inkjet printing process, the organic light-emitting layer is connected to the anode through the pixel opening, and a cathode is formed on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer .
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo )
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), Can be single layer, multilayer or composite layer.
  • the first insulating layer is called the buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), Materials such as hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the first flat layer and the second flat layer can be made of organic materials, such as resin and the like.
  • the fifth conductive layer can adopt a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO/Ag/ITO and the like.
  • the pixel definition layer can be polyimide, acrylic or polyethylene terephthalate.
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy.
  • the first shielding electrode in the second conductive layer, in the plane parallel to the substrate, the first shielding electrode blocks the overlapping area of the first connection electrode and the first scanning signal line, and in the vertical In the plane of the substrate, the first shielding electrode is located between the first scanning signal line and the first connection electrode, and the first shielding electrode is connected to the first power supply line, so the first shielding electrode can effectively shield the first scanning signal line
  • the impact of the voltage jump of the scanning signal on the first connection electrode thereby effectively avoiding the impact of the voltage jump of the scanning signal on the first scanning signal line on the gate electrode of the third transistor T3, ensuring the stability of the working performance of the driving transistor and improving the display performance. Effect.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the structure and its preparation process shown above in the present disclosure are only exemplary illustrations.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the first power line may be disposed in the third conductive layer ( SD1 ), the first power line and the data signal line are disposed on the same layer, and formed simultaneously through the same patterning process.
  • the first shielding electrode can be set separately, not connected to the second plate, but connected to the first power line formed later through a via hole.
  • the third conductive layer and the first planar layer may be provided with a fifth insulating layer (PVX), which is not limited in this disclosure.
  • the display substrate of the present disclosure can be applied in a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc., the disclosure is not limited here.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc.
  • the present disclosure also provides a method for preparing a display substrate, so as to manufacture the display substrate provided by the above-mentioned embodiments.
  • the preparation method includes:
  • a plurality of circuit units, a scanning signal line for supplying scanning signals to the circuit units, and a first power supply line for supplying power signals are formed on the substrate, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit includes a pixel driving circuit that is compatible with the first A power line is connected to the first shielding electrode, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the scanning signal line on the substrate.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiments of the present disclosure are not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括多个电路单元、向电路单元提供扫描信号的扫描信号线和提供电源信号的第一电源线（51）；至少一个电路单元包括像素驱动电路，像素驱动电路包括与第一电源线（51）连接的第一屏蔽电极（34），第一屏蔽电极（34）在显示基板平面上的正投影与扫描信号线在显示基板平面上的正投影至少部分重叠。

Description

显示基板及其制备方法、显示装置
本申请要求于2021年8月11日提交中国专利局、申请号为202110917746.9、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括多个电路单元、向所述电路单元提供扫描信号的扫描信号线和提供电源信号的第一电源线；至少一个电路单元包括像素驱动电路，所述像素驱动电路包括与所述第一电源线连接第一屏蔽电极，所述第一屏蔽电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影至少部分重叠。
在示例性实施方式中，所述像素驱动电路还包括驱动晶体管以及形成存储电容的第一极板和第二极板，所述第一极板在所述显示基板平面上的正投 影与所述第二极板在所述显示基板平面上的正投影至少部分重叠；所述第一屏蔽电极与所述第二极板连接，所述第二极板通过过孔与所述第一电源线连接。
在示例性实施方式中，所述像素驱动电路还包括补偿晶体管和第一连接电极，所述第一连接电极的第一端通过过孔与所述补偿晶体管中有源层的第一区连接，所述第一连接电极的第二端通过过孔与所述第一极板连接，所述第一连接电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影至少部分重叠。
在示例性实施方式中，所述第一屏蔽电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影具有第一重叠区域，所述第一连接电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影具有第二重叠区域，所述第二重叠区域与所述第一重叠区域至少部分交叠。
在示例性实施方式中，所述第二重叠区域位于所述第一重叠区域的范围之内。
在示例性实施方式中，所述第一重叠区域具有第一宽度，所述第二重叠区域具有第二宽度；所述第一宽度大于所述第二宽度，所述第一宽度和第二宽度为所述第一方向的尺寸。
在示例性实施方式中，所述第二宽度为所述第一宽度L1的40％至60％。
在示例性实施方式中，所述第一宽度为2.5μm至3.0μm。
在示例性实施方式中，所述第二宽度为1.3μm至2.0μm。
在示例性实施方式中，所述扫描信号线的主体部分沿着第一方向延伸，所述第一屏蔽电极的主体部分沿着第二方向延伸，所述第一方向与第二方向交叉；所述第一屏蔽电极设置在所述第二极板靠近所述扫描信号线的一侧，所述第一屏蔽电极远离所述第二极板的一端在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影至少部分重叠。
在示例性实施方式中，所述第一屏蔽电极和所述第二极板同层设置，且 为相互连接的一体结构。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层之间以及所述第三导电层和所述第四导电层之间均设置有绝缘层；所述第一屏蔽电极、第一连接电极和扫描信号线位于不同的导电层。
在示例性实施方式中，所述扫描信号线设置在所述第一导电层中，所述第一屏蔽电极设置在所述第二导电层中，所述第一连接电极在所述第三导电层中。
在示例性实施方式中，所述半导体层包括所述像素驱动电路中多个晶体管的有源层，所述第一导电层包括扫描信号线、多个晶体管的栅电极和存储电容的第一极板，所述第二导电层包括所述第一屏蔽电极和存储电容的第二极板，所述第三导电层包括数据信号线和第一连接电极，所述第四导电层包括第一电源线。
在示例性实施方式中，所述第二导电层还包括第二屏蔽电极，所述第二屏蔽电极包括相互连接的第一子电极和第二子电极，所述第一子电极在基底上的正投影与所述数据信号线在基底上的正投影至少部分重叠，所述第二子电极在基底上的正投影位于所述数据信号线在基底上的正投影和所述第一连接电极在基底上的正投影之间。
在示例性实施方式中，所述第二屏蔽电极通过过孔与所述第一电源线连接。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，包括：
在基底上形成多个电路单元、向所述电路单元提供扫描信号的扫描信号线和提供电源信号的第一电源线，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括与所述第一电源线连接第一屏蔽电极，所述第一屏蔽电极在所述基底上的正投影与所述扫描信号线在基底上的正投影至少部分重叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为本公开示例性实施例一种显示基板的结构示意图；
图7为本公开示例性实施例形成半导体层图案后的示意图；
图8a为本公开示例性实施例形成第一导电层图案后的示意图；
图8b为图8a中第一导电层的平面示意图；
图9a为本公开示例性实施例形成第二导电层图案后的示意图；
图9b为图9a中第二导电层的平面示意图；
图10a为本公开示例性实施例形成第四绝缘层图案后的示意图；
图10b为图10a中多个过孔的平面示意图；
图11a为本公开示例性实施例形成第三导电层图案后的示意图；
图11b为图11a中第三导电层的平面示意图；
图12a为本公开示例性实施例形成第一平坦层图案后的示意图；
图12b为图12a中多个过孔的平面示意图；
图13a为本公开显示基板形成第四导电层图案后的示意图；
图13b为图13a中第四导电层的平面示意图；
图14为本公开示例性实施例形成第二平坦层图案后的示意图；
图15为本公开示例性实施例形成阳极图案后的示意图；
图16为本公开示例性实施例形成像素定义层图案后的示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；       13—第三有源层；
14—第四有源层；       15—第五有源层；       16—第六有源层；
17—第七有源层；       21—第一扫描信号线；   21-1—栅极块；
22—第二扫描信号线；   23—发光控制线；       24—第一极板；
31—初始信号线；       32—第二极板；         33—极板连接线；
34—第一屏蔽电极；     35—第二屏蔽电极；     35-1—第一子电极；
35-2—第二子电极；     36—开口；             41—第一连接电极；
42—第二连接电极；     43—第三连接电极；     44—数据信号线；
51—第一电源线；       52—阳极连接电极；     61—阳极；
71—像素开口；         101—基底；            102—驱动电路层；
103—发光结构层；      104—封装层；          210—晶体管；
211—存储电容；        301—阳极；            302—像素定义层；
303—有机发光层；      304—阴极；            401—第一封装层；
402—第二封装层；      403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也 不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的 电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器、多个扫描信号线、多个数据信号线、多个发光信号线和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n 可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和一个出射第三颜色光线的第三子像素P3，三个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和发光信号线和像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字等方式排列。在一种示例性实施方式中，至少一个像素单元P可以包括四个子像素，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的 结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个信号线和多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，图3中仅以一个驱动晶体管210和一个存储电容211为例进行示意。发光结构层103可以包括多个发光器件，至少一个发光器件可以包括阳极301、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶 体管T7)和1个存储电容C，像素驱动电路分别与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信 号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存 储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图6为本公开示例性实施例一种显示基板的结构示意图，示意了一个电路单元的平面结构。如图6所示，在平行于显示基板的平面内，显示基板可以包括多个电路单元和多条信号线，多个电路单元可以沿着第一方向X依次排布形成电路单元行，多个电路单元可以沿着第二方向Y依次排布形成电路单元列，多个电路单元行和多个电路单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
在示例性实施方式中，多条信号线可以至少包括第一扫描信号线21、第二扫描信号线22、发光控制线23、初始信号线31、数据信号线44和第一电 源线51，至少一个电路单元可以包括像素驱动电路。第一扫描信号线21、第二扫描信号线22、发光控制线23和初始信号线31的主体部分可以沿着第一方向X延伸，数据信号线44和第一电源线51的主体部分可以沿着第二方向Y延伸。本公开中，A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其它方向伸展的长度。
在示例性实施方式中，第一扫描信号线21和第二扫描信号线22被配置为向像素驱动电路提供扫描信号，发光控制线23被配置为向像素驱动电路提供发光控制信号，初始信号线31被配置为向像素驱动电路提供初始信号，数据信号线44被配置为向像素驱动电路提供数据信号，第一电源线51被配置为向像素驱动电路提供电源信号。
在示例性实施方式中，像素驱动电路可以包括多个晶体管和存储电容，多个晶体管可以包括第一晶体管T1至第七晶体管T7，第三晶体管T3为驱动晶体管，存储电容可以包括第一极板24和第二极板32，第一极板24在显示基板平面上的正投影与第二极板32在显示基板平面上的正投影至少部分重叠。
在示例性实施方式中，第一晶体管T1的栅电极与第二扫描信号线22连接，第一晶体管T1的第一极与初始信号线31连接，第一晶体管T1的第二极分别与第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容的第一极板24连接。第二晶体管T2的栅电极与第一扫描信号线21连接，第二晶体管T2的第一极分别与第一晶体管T1的第二极、第三晶体管T3的栅电极和存储电容的第一极板24连接，第二晶体管T2的第二极分别与第三晶体管T3的第二极和第六晶体管T6的第一极连接。第三晶体管T3的栅电极分别与第一晶体管T1的第二极、第二晶体管T2的第一极和存储电容的第一极板24连接，第三晶体管T3的第一极分别与第四晶体管T4的第二极和第五晶体管T5的第二极连接，第三晶体管T3的第二极分别与第二晶体管T2的第二极和第六晶体管T6的第一极连接。第四晶体管T4的栅电极与第一扫描信号线21连接，第四晶体管T4的第一极与数据信号线44连接，第四晶体管T4的第二极分别与第三晶体管T3的第一极和第五晶体管T5的第二极连 接。第五晶体管T5的栅电极与发光信号线23连接，第五晶体管T5的第一极分别与第一电源线51和存储电容的第二极板32连接，第五晶体管T5的第二极分别与第三晶体管T3的第一极和第四晶体管T4的第二极连接。第六晶体管T6的栅电极与发光信号线23连接，第六晶体管T6的第一极分别与第二晶体管T2的第二极和第三晶体管T3的第二极连接，第六晶体管T6的第二极分别与第七晶体管T7的第二极和发光器件的第一极连接。第七晶体管T7的栅电极与第二扫描信号线22连接，第七晶体管T7的第一极与初始信号线31连接，第七晶体管T7的第二极分别与第六晶体管T6的第二极和发光器件的第一极连接。
在示例性实施方式中，存储电容的第一极板24分别与第一晶体管T1的第二极、第二晶体管T2的第一极和第三晶体管T3的栅电极连接，存储电容的第二极板32分别与第一电源线51和第五晶体管T5的第一极连接。
在示例性实施方式中，存储电容的第一极板24可以作为第三晶体管T3的栅电极。
在示例性实施方式中，像素驱动电路可以包括第一屏蔽电极34，第一屏蔽电极34被配置为屏蔽扫描信号电压跳变对第三晶体管T3的影响，避免扫描信号电压跳变影响驱动晶体管的性能，提高显示效果。
在示例性实施方式中，第一屏蔽电极34可以与第一电源线51连接，第一屏蔽电极34在显示基板平面上的正投影与第一扫描信号线21在显示基板平面上的正投影至少部分重叠。
在示例性实施方式中，像素驱动电路可以包括第一连接电极41，第一连接电极41被配置为作为第一晶体管T1的第二极和第二晶体管T2的第一极。第一连接电极41的主体部分可以沿着第二方向Y延伸。第一连接电极41的第一端通过过孔与第二晶体管T2中有源层的第一区连接，第一连接电极41的第二端通过过孔与第一极板24(即第三晶体管T3的栅电极)连接，第一连接电极41在显示基板平面上的正投影与第一扫描信号线21在显示基板平面上的正投影至少部分重叠。
在示例性实施方式中，第一屏蔽电极34在显示基板平面上的正投影与第一扫描信号线21在显示基板平面上的正投影具有第一重叠区域，第一连接电 极41在显示基板平面上的正投影与第一扫描信号线21在显示基板平面上的正投影具有第二重叠区域，第二重叠区域与第一重叠区域至少部分交叠。
在示例性实施方式中，第二重叠区域位于第一重叠区域的范围之内。
在示例性实施方式中，第一屏蔽电极34与存储电容的第二极板32连接，存储电容的第二极板32通过过孔与第一电源线51连接。
在示例性实施方式中，第一屏蔽电极34可以为主体部分沿着第二方向Y延伸的条形状，设置在第二极板32靠近第一扫描信号线21的一侧，第一屏蔽电极34远离第二极板32的一端在显示基板平面上的正投影与第一扫描信号线21在显示基板平面上的正投影至少部分交叠。
在示例性实施方式中，像素驱动电路可以包括第二屏蔽电极35，第二屏蔽电极35被配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施方式中，第二屏蔽电极35可以与第一电源线51连接，第二屏蔽电极35在基底上的正投影与第四晶体管T4的第四有源层在基底上的正投影至少部分重叠。
在示例性实施方式中，第二屏蔽电极35可以包括相互连接的第一子电极和第二子电极，第一子电极在基底上的正投影可以与数据信号线44在基底上的正投影至少部分重叠，第二子电极在基底上的正投影位于数据信号线44在基底上的正投影和第一连接电极41在基底上的正投影之间。
在示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。半导体层可以包括多个晶体管的有源层，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23、存储电容的第一极板24和多个晶体管的栅电极，第二导电层可以包括初始信号线31、存储电容的第二极板32、第一屏蔽电极34和第二屏蔽电极35，第三导电层可以包括数据信号线44和第一连接电极41，第四导电层可以包括第一电源线51。
在示例性实施方式中，同层设置的第一屏蔽电极34和存储电容的第二极板32为相互连接的一体结构。
在示例性实施方式中，显示基板可以包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以一个电路单元为例，显示基板的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图7所示。
在示例性实施例中，每个电路单元的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构。
在示例性实施例中，第一有源层11、第二有源层12、第四有源层14和第七有源层17位于第三有源层13第二方向Y的反方向的一侧，第五有源层15和第六有源层16位于第三有源层13第二方向Y的一侧，第一有源层11和第七有源层17位于第二有源层12和第四有源层14远离第三有源层13的一侧。
在示例性实施例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“I”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一区11-1同时作为第七有源层17的第一区17-1，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，即第三有源层13的第一区13-1、第四有源层14的第二区14-2和第五有源层15的第二区15-2之间相互连接，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，即第三有源层13的第二区13-2、第二有源层12的第二区12-2和第六有源层16的第一区16-1之间相互连接，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2。在示例性实施例中，第四有源层14的第一区14-1和第五有源层15的第一区15-1单独设置。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图8a和图8b所示，图8b为图8a中第一导电层的平面示意图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
结合图7至图8b所示，每个电路单元的第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板 24。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22和发光控制线23的主体部分可以沿第一方向X延伸，第一扫描信号线21和第二扫描信号线22可以位于第一极板24第二方向Y的反方向的一侧，发光控制线23可以位于第一极板24第二方向Y的一侧，存储电容的第一极板24可以设置在第一扫描信号线21和发光控制线23之间。
在示例性实施例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三有源层13在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施例中，第一扫描信号线21与第二有源层12相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二有源层12在基底上的正投影存在重叠区域，形成双栅结构的第二晶体管T2。第一扫描信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极，第二扫描信号线22与第一有源层11相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与第七有源层17相重叠的区域作为第七晶体管T7的栅电极。发光控制线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六有源层16相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图9a和图9b所示，图9b为图9a中第二导电层的平面示意图。在示例性实施例中，第二导电层 可以称为第二栅金属(GATE 2)层。
结合图7至图9b所示，每个电路单元的第二导电层图案至少包括：初始信号线31、存储电容的第二极板32、极板连接线33、第一屏蔽电极34和第二屏蔽电极35。
在示例性实施例中，初始信号线31的主体部分可以沿第一方向X延伸，初始信号线31可以位于第二扫描信号线22远离第一扫描信号线21的一侧，第二极板32作为存储电容的另一个极板，位于第一扫描信号线21和发光控制线23之间，第一屏蔽电极34可以位于第二极板32靠近第一扫描信号线21的一侧，第二屏蔽电极35可以位于第一扫描信号线21(不包含栅极块21-1的主体部分)与第二扫描信号线22之间。
在示例性实施例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域，第一极板24和第二极板32构成像素驱动电路的存储电容。
在示例性实施例中，第二极板32上设置有开口36，开口36可以位于第二极板32的中部。开口36可以为矩形，使第二极板32形成环形结构。开口36暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口36在基底上的正投影。在示例性实施例中，开口36被配置为容置后续形成的第一过孔，第一过孔位于开口36内并暴露出第一极板24，使后续形成的第一连接电极与第一极板24连接。
在示例性实施例中，极板连接线33可以设置在第二极板32第一方向X的一侧和第一方向X的反方向的一侧，极板连接线33的第一端与本电路单元的第二极板32连接，极板连接线33的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻电路单元的第二极板32连接，即极板连接线33配置为使一电路单元行上相邻电路单元的第二极板32相互连接。在示例性实施例中，通过极板连接线33可以使一电路单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一电路单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第一屏蔽电极34可以为沿着第二方向Y延伸的条 形状，可以设置在第二极板32靠近第一扫描信号线21的一侧，且与第二极板32为相互连接的一体结构。第一屏蔽电极34远离第二极板32的一端在基底上的正投影与第一扫描信号线21在基底上的正投影至少部分重叠。第一屏蔽电极34被配置为屏蔽屏蔽第一扫描信号电压跳变对第三晶体管T3的影响，避免第一扫描信号电压跳变影响驱动晶体管的性能，提高显示效果。
在示例性实施例中，主体部分沿着第一方向X延伸的第一扫描信号线21在重叠区域具有宽度B，主体部分沿着第二方向Y延伸的第一屏蔽电极34在重叠区域具有第一宽度L1，宽度B和第一宽度L1是指垂直于其延伸方向的尺寸。
在示例性实施例中，第一屏蔽电极34在基底上的正投影与第一扫描信号线21在基底上的正投影具有第一重叠区域A1，则第一重叠区域A1的面积约为A1＝L1*B，第一宽度L1为第一方向X的尺寸，第一宽度B为第二方向Y的尺寸。
在示例性实施例中，第二屏蔽电极35被配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。第二屏蔽电极35的形状可以呈“L”字形，可以包括第一子电极35-1和第二子电极35-2，第一子电极35-1的第一端位于远离第一屏蔽电极34的一侧，第一子电极35-1的第二端沿着第一方向X延伸后，与第二子电极35-2的第一端连接，第二子电极35-2的第二端沿着第二方向Y的反方向延伸后，位于所述第一初始线31靠近第一屏蔽电极34的一侧。
在示例性实施例中，第一子电极35-1在基底上的正投影可以与第四有源层14在基底上的正投影至少部分重叠，第一子电极35-1在基底上的正投影可以与后续形成的数据信号线在基底上的正投影至少部分重叠。
在示例性实施例中，第二子电极35-2在基底上的正投影可以位于后续形成的数据信号线在基底上的正投影和后续形成的第一连接电极在基底上的正投影之间。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层 上设置有多个过孔，如图10a和图10b所示，图10b为图10a中多个过孔的平面示意图。
结合图7至图10b所示，每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第八过孔V8和第六过孔V6。
在示例性实施例中，第一过孔V1在基底上的正投影可以位于开口36在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一连接电极(第一晶体管T1的第二极和第二晶体管T2的第一极)与通过该过孔与第一极板24连接。
在示例性实施例中，第二过孔V2在基底上的正投影可以位于第六有源层在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第二过孔V2配置为使后续形成的第六晶体管T6的第二极(第七晶体管T7的第二极)通过该过孔与第六有源层的第二区连接。
在示例性实施例中，第三过孔V3在基底上的正投影可以位于第四有源层在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第三过孔V3配置为使后续形成的数据信号线通过该过孔与第四有源层的第一区连接。
在示例性实施例中，第四过孔V4在基底上的正投影可以位于第二有源层在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第四过孔V4配置为使后续形成的第一连接电极(第一晶体管T1的第二极和第二晶体管T2的第一极)通过该过孔与第二有源层的第一区连接。
在示例性实施例中，第五过孔V5在基底上的正投影可以位于第七有源层在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第五过孔V5配置为使后续形成的第七晶体管T7的第一极 (第一晶体管T1的第一极)通过该过孔与第七有源层的第一区连接。
在示例性实施例中，第六过孔V6在基底上的正投影可以位于初始信号线31在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面。第六过孔V6配置为使后续形成的第七晶体管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与初始信号线31连接。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图11a和图11b所示，图11b为图11a中第三导电层的平面示意图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
结合图7至图11b所示，第三导电层至少包括：第一连接电极41、第二连接电极42、第三连接电极43和数据信号线44。
在示例性实施例中，第一连接电极41的主体部分可以沿着第二方向Y延伸。第一连接电极41的第一端通过第四过孔V4与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24(第三晶体管T3的栅电极)、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极41可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施例中，第一连接电极41在基底上的正投影与第一扫描信号线21在基底上的正投影至少部分交叠，第一连接电极41在基底上的正投影与第一屏蔽电极34在基底上的正投影至少部分交叠。
在示例性实施例中，第二连接电极42的第一端通过第六过孔V6与初始信号线31连接，其第二端通过第五过孔V5与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与初始信号线31相同的电位。在示例性实施例中，第二连接电极42可以作为第一晶体管T1的第一极和第七晶体管T7的第一极。
在示例性实施例中，第三连接电极43通过第二过孔V2与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第 七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极43可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第三连接电极43被配置为与后续形成的阳极连接电极连接。
在示例性实施例中，数据信号线44的主体部分可以沿着第二方向Y延伸。数据信号线44通过第三过孔V3与第四有源层的第一区连接，将数据信号写入第四晶体管T4的第一极。
在示例性实施例中，主体部分沿着第一方向X延伸的第一扫描信号线21在重叠区域具有宽度B，主体部分沿着第二方向Y延伸的第一连接电极41在重叠区域具有第二宽度L2，宽度B和第二宽度L2是指垂直于其延伸方向的尺寸。
在示例性实施例中，第一连接电极41在基底上的正投影与第一扫描信号线21在基底上的正投影具有第二重叠区域A2，则第二重叠区域A2的面积约为A2＝L2*B，第二宽度L2为第一方向X的尺寸，第一宽度B为第二方向Y的尺寸。
第二重叠区域A2可以位于第一重叠区域A1的范围之内，即第一重叠区域A1的轮廓可以包含第二重叠区域A2的轮廓。
在示例性实施例中，第一宽度L1可以大于或等于第二宽度L2，即第一重叠区域A1的面积可以大于或等于第二重叠区域A2的面积。
在示例性实施例中，第二宽度L2可以约为第一宽度L1的40％至60％。
在示例性实施例中，第一宽度L1可以约为2.5μm至3.0μm，第二宽度L2可以约为1.3μm至2.0μm。
在示例性实施例中，在平行于基底的平面内，第一屏蔽电极34可以遮挡第一连接电极41与第一扫描信号线21的交叠区域，在垂直于基底的平面内，第一屏蔽电极34位于第一扫描信号线21和第一连接电极41之间。由于第一屏蔽电极34与后续形成的第一电源线连接，因而第一屏蔽电极34可以有效屏蔽第一扫描信号线21上扫描信号电压跳变对第一连接电极41的影响，进而有效避免第一扫描信号线21上扫描信号电压跳变对第三晶体管T3的栅电极的影响，保证了第三晶体管T3的性能，提高显示效果。
在示例性实施例中，由于第二屏蔽电极35中第一子电极35-1在基底上的正投影与数据信号线44在基底上的正投影至少部分重叠，第二屏蔽电极35中第二子电极35-2在基底上的正投影位于数据信号线44在基底上的正投影与第一连接电极41在基底上的正投影之间，且第二屏蔽电极35与后续形成的第一电源线连接，因而第二屏蔽电极35可以有效屏蔽了数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，第一方向X上相邻电路单元中的第二屏蔽电极35可以相互连接，以降低电阻。
(6)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦层上设置有多个过孔，如图12a和图12b所示，图12b为图12a中多个过孔的平面示意图。
结合图7至图12b所示，每个电路单元的多个过孔至少包括第十一过孔V11、第十二过孔V12、第十三过孔V13和第十四过孔V14。
在示例性实施例中，第十一过孔V11在基底上的正投影位于第三连接电极43在基底上的正投影的范围之内，第十一过孔V11内的第一平坦层被去掉，暴露出第三连接电极43的表面。第十一过孔V11配置为使后续形成的阳极连接电极通过该过孔与第三连接电极43连接。
在示例性实施例中，第十二过孔V12在基底上的正投影位于第五有源层在基底上的正投影的范围之内，第十二过孔V12内的第一平坦层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第十二过孔V12配置为使后续形成的第一电源线通过该过孔与第五有源层的第一区连接。
在示例性实施例中，第十三过孔V13在基底上的正投影可以位于第二极板32在基底上的正投影的范围之内，第十三过孔V13内的第一平坦层和第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第十三过孔V13配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在示例性实施例中， 第十三过孔V13可以包括多个，多个第十三过孔V13可以沿着第二方向Y依次排列，以增加第一电源线与第二极板32的连接可靠性。
在示例性实施例中，第十四过孔V14在基底上的正投影可以位于第二屏蔽电极35在基底上的正投影的范围之内，第十四过孔V14内的第一平坦层和第四绝缘层被刻蚀掉，暴露出第二屏蔽电极35的表面。第十四过孔V14配置为使后续形成的第一电源线通过该过孔与第二屏蔽电极35连接。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图13a和图13b所示，图13b为图13a中第四导电层的平面示意图。
结合图7至图13b所示，第四导电层至少包括：第一电源线51和阳极连接电极52。
在示例性实施例中，第一电源线51的主体部分可以沿着第二方向Y延伸，第一电源线51可以位于第一连接电极41与数据信号线44之间。第一电源线51一方面通过第十二过孔V12与第五有源层的第一区连接，另一方面通过第十三过孔V13与第二极板32连接，又一方面通过第十四过孔V14与第二屏蔽电极35连接，使得第二极板32、第一屏蔽电极34和第二屏蔽电极35具有与第一电源线51相同的电位，并将第一电源信号写入第五晶体管T5。
在示例性实施例中，阳极连接电极52可以为矩形状，通过第十一过孔V11与第三连接电极43连接。由于第三连接电极43通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了阳极连接电极52通过第三连接电极43与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施例中，第一电源线51可以为非等宽度的直线。第一电源线51靠近数据信号线44的一侧可以设置第一凹槽，第一电源线51靠近第一连接电极41的一侧可以设置第二凹槽。第一电源线51采用变宽度的直线，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
(8)形成第二平坦层图案。在示例性实施例中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有过孔，如图14所示。
结合图7至图14所示，每个电路单元的过孔至少包括第二十一孔V21。
在示例性实施例中，第二十一孔V21在基底上的正投影可以位于阳极连接电极52在基底上的正投影的范围之内，第二十一孔V21内的第二平坦层被去掉，暴露出阳极连接电极52的表面。在示例性实施例中，第二十一孔V21配置为使后续形成的阳极通过该过孔与阳极连接电极52连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光控制线、初始信号线、数据信号线和第一电源线。在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施例中，制备完成驱动电路层后，可以在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(9)形成阳极图案。在示例性实施例中，形成阳极图案可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第二平坦层上的阳极61图案，如图15所示。
结合图7至图15所示，阳极61可以通过第二十一孔V21与阳极连接电极52连接。由于阳极连接电极52通过过孔与作为第六晶体管T6的第二极和第七晶体管T7的第二极的第三连接电极43连接，因而阳极61可以通过阳极连接电极52和第三连接电极43与第六晶体管T6和第七晶体管T7的连接，实现了像素驱动电路可以驱动发光器件发光。
在示例性实施例中，阳极61可以包括阳极主体部和多个凸起，阳极主体部的形状可以为具有圆角的矩形，多个凸起可以包括第一凸起和第二凸起，第一凸起和第二凸起均与阳极主体部连接。第一凸起可以是向着第二晶体管 T2的栅电极凸出的矩形，配置为调整像素驱动电路中关键节点的寄生电容，减小相邻电路单元中关键节点节点寄生电容之间的差异，以减小亮度差异，提升显示效果。第二凸起可以是向着阳极连接电极52凸出的矩形，配置为通过第二十一孔V21与阳极连接电极52连接。
(10)形成像素定义层图案。在示例性实施例中，形成像素定义层图案可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层图案，像素定义层图案可以包括暴露出阳极61的像素开口71，如图16所示。
在示例性实施例中，后续制备流程可以包括：采用蒸镀或喷墨打印工艺形成有机发光层，有机发光层通过像素开口与阳极连接，在有机发光层上形成阴极，阴极与有机发光层连接。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、 硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。第一平坦层和第二平坦层可以采用有机材料，如树脂等。第五导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
随着显示技术的发展，高扫描频率和高分辨率(Pixels Per Inch，简称PPI)显示已经成为趋势产品，具有更精细的画质显示，具有更高的显示品质。研究发现，现有显示基板中驱动晶体管存在工作性能不稳定的问题，而驱动晶体管的工作特性对高频和高分辨率显示的影响较大。本公开提供的显示基板，通过在第二导电层中设置第一屏蔽电极，在平行于基底的平面内，第一屏蔽电极遮挡第一连接电极与第一扫描信号线的交叠区域，在垂直于基底的平面内，第一屏蔽电极位于第一扫描信号线和第一连接电极之间，且第一屏蔽电极与第一电源线连接，因而第一屏蔽电极可以有效屏蔽第一扫描信号线上扫描信号电压跳变对第一连接电极的影响，进而有效避免第一扫描信号线上扫描信号电压跳变对第三晶体管T3的栅电极的影响，保证了驱动晶体管工作性能的稳定性，提高显示效果。
本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，第一电源线可以设置在第三导电层(SD1)中，第一电源线与数据信号线同层设置，且通过同一次构图工艺同时形成。又如，第一屏蔽电极可以单独设 置，不与第二极板连接，而通过过孔与后续形成的第一电源线连接。再如，第三导电层与第一平坦层可以设置第五绝缘层(PVX)等，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施例中，所述制备方法包括：
在基底上形成多个电路单元、向所述电路单元提供扫描信号的扫描信号线和提供电源信号的第一电源线，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括与所述第一电源线连接第一屏蔽电极，所述第一屏蔽电极在所述基底上的正投影与所述扫描信号线在基底上的正投影至少部分重叠。
本公开提供的显示基板的制备方法所制作的显示基板，其实现原理和实现效果类似，在此不再赘述。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种显示基板，包括多个电路单元、向所述电路单元提供扫描信号的扫描信号线和提供电源信号的第一电源线；至少一个电路单元包括像素驱动电路，所述像素驱动电路包括与所述第一电源线连接第一屏蔽电极，所述第一屏蔽电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括驱动晶体管以及形成存储电容的第一极板和第二极板，所述第一极板在所述显示基板平面上的正投影与所述第二极板在所述显示基板平面上的正投影至少部分重叠；所述第一屏蔽电极与所述第二极板连接，所述第二极板通过过孔与所述第一电源线连接。
  3. 根据权利要求2所述的显示基板，其中，所述像素驱动电路还包括补偿晶体管和第一连接电极，所述第一连接电极的第一端通过过孔与所述补偿晶体管中有源层的第一区连接，所述第一连接电极的第二端通过过孔与所述第一极板连接，所述第一连接电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影至少部分重叠。
  4. 根据权利要求3所述的显示基板，其中，所述第一屏蔽电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影具有第一重叠区域，所述第一连接电极在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影具有第二重叠区域，所述第二重叠区域与所述第一重叠区域至少部分交叠。
  5. 根据权利要求4所述的显示基板，其中，所述第二重叠区域位于所述第一重叠区域的范围之内。
  6. 根据权利要求4所述的显示基板，其中，所述第一重叠区域具有第一宽度，所述第二重叠区域具有第二宽度；所述第一宽度大于所述第二宽度，所述第一宽度和第二宽度为所述第一方向的尺寸。
  7. 根据权利要求6所述的显示基板，其中，所述第二宽度为所述第一宽度L1的40％至60％。
  8. 根据权利要求6所述的显示基板，其中，所述第一宽度为2.5μm至3.0μm。
  9. 根据权利要求6所述的显示基板，其中，所述第二宽度为1.3μm至2.0μm。
  10. 根据权利要求2所述的显示基板，其中，所述扫描信号线的主体部分沿着第一方向延伸，所述第一屏蔽电极的主体部分沿着第二方向延伸，所述第一方向与第二方向交叉；所述第一屏蔽电极设置在所述第二极板靠近所述扫描信号线的一侧，所述第一屏蔽电极远离所述第二极板的一端在所述显示基板平面上的正投影与所述扫描信号线在所述显示基板平面上的正投影至少部分重叠。
  11. 根据权利要求10所述的显示基板，其中，所述第一屏蔽电极和所述第二极板同层设置，且为相互连接的一体结构。
  12. 根据权利要求1至11任一项所述的显示基板，其中，在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层之间以及所述第三导电层和所述第四导电层之间均设置有绝缘层；所述第一屏蔽电极、第一连接电极和扫描信号线位于不同的导电层。
  13. 根据权利要求12所述的显示基板，其中，所述扫描信号线设置在所述第一导电层中，所述第一屏蔽电极设置在所述第二导电层中，所述第一连接电极在所述第三导电层中。
  14. 根据权利要求12所述的显示基板，其中，所述半导体层包括所述像素驱动电路中多个晶体管的有源层，所述第一导电层包括扫描信号线、多个晶体管的栅电极和存储电容的第一极板，所述第二导电层包括所述第一屏蔽电极和存储电容的第二极板，所述第三导电层包括数据信号线和第一连接电极，所述第四导电层包括第一电源线。
  15. 根据权利要求14所述的显示基板，其中，所述第二导电层还包括第二屏蔽电极，所述第二屏蔽电极包括相互连接的第一子电极和第二子电极， 所述第一子电极在基底上的正投影与所述数据信号线在基底上的正投影至少部分重叠，所述第二子电极在基底上的正投影位于所述数据信号线在基底上的正投影和所述第一连接电极在基底上的正投影之间。
  16. 根据权利要求15所述的显示基板，其中，所述第二屏蔽电极通过过孔与所述第一电源线连接。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，包括：
    在基底上形成多个电路单元、向所述电路单元提供扫描信号的扫描信号线和提供电源信号的第一电源线，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括与所述第一电源线连接第一屏蔽电极，所述第一屏蔽电极在所述基底上的正投影与所述扫描信号线在基底上的正投影至少部分重叠。
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