[go: up one dir, main page]

WO2022241747A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2022241747A1
WO2022241747A1 PCT/CN2021/095038 CN2021095038W WO2022241747A1 WO 2022241747 A1 WO2022241747 A1 WO 2022241747A1 CN 2021095038 W CN2021095038 W CN 2021095038W WO 2022241747 A1 WO2022241747 A1 WO 2022241747A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
emitting element
display substrate
pixel circuit
layer
Prior art date
Application number
PCT/CN2021/095038
Other languages
English (en)
French (fr)
Inventor
王蓉
董向丹
田东辉
何帆
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001231.2A priority Critical patent/CN115769296B/zh
Priority to PCT/CN2021/095038 priority patent/WO2022241747A1/zh
Priority to US17/772,151 priority patent/US12238991B2/en
Publication of WO2022241747A1 publication Critical patent/WO2022241747A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, especially to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • An embodiment of the present disclosure provides a display substrate, including a display area and a non-display area surrounding the display area, the display area includes a first display area, a second display area, and a fan-out wiring area, and the second display area The area is located between the first display area and the fan-out wiring area;
  • the first display area includes a plurality of first sub-pixels, the first sub-pixels include a first pixel circuit and a first light-emitting element, and the first pixel circuit and the first light-emitting element are on the display substrate
  • the orthographic projections of are at least partially overlapping;
  • the second display area includes a plurality of second sub-pixels, the second sub-pixels include a second pixel circuit and a second light-emitting element, and the second pixel circuit and the second light-emitting element are on the display substrate
  • the orthographic projections of are at least partially overlapping;
  • the first pixel circuit and the second pixel circuit are electrically connected to the plurality of data lines;
  • the fan-out wiring area includes a plurality of data fan-out lines and a plurality of third sub-pixels, the third sub-pixel includes a third light-emitting element, and at least one second pixel circuit is electrically connected to at least two light-emitting elements, so The at least two light emitting elements are selected from at least one of the second light emitting element and the third light emitting element, and the plurality of data fan-out lines are electrically connected to the plurality of data lines.
  • the orthographic projection of the second pixel circuit on the plane of the display substrate and the orthographic projection of the third light emitting element on the plane of the display substrate do not overlap.
  • the data fan-out line is a stepped line
  • the orthographic projection of the data fan-out line on the display substrate plane is the same as that of the first pixel circuit and the second pixel circuit on the Shows that the orthographic projections on the substrate plane do not overlap.
  • the display area includes a first connection line and a second connection line
  • the first connection line is configured to connect at least one of the following: the first pixel circuit and the first light emitting element the anode of the second pixel circuit and the second light-emitting element, the second pixel circuit and the anode of the third light-emitting element; the second connection line is configured to connect the at least two The anode of the light-emitting element.
  • the material of the first connection line and the second connection line is a transparent conductive material.
  • the fan-out wiring area includes a light emitting element of a first color, a light emitting element of a second color, and a light emitting element of a third color
  • the second connection line is configured to connect at least two light emitting elements of the third color The anode of the light-emitting element.
  • the third color light emitting element is a green light emitting element.
  • the third sub-pixel further includes a third pixel circuit
  • the orthographic projection of the third pixel circuit on the display substrate is in the same position as the light-emitting element of the first color or the light-emitting element of the second color.
  • the orthographic projection on the display substrate at least partially overlaps, and does not overlap with the orthographic projection of the third color light-emitting element on the display substrate.
  • the second connecting wire is further configured to connect at least one of the following: anodes of at least two light emitting elements of the first color, and anodes of at least two light emitting elements of the second color.
  • the data fan-out line includes at least one horizontal connection portion and at least one vertical connection portion
  • the orthographic projection of the horizontal connection portion on the plane of the display substrate is the same as that of the third light emitting element on the Orthographic projections on the plane of the display substrate do not overlap, and there is at least an overlapping area between the orthographic projections of the longitudinal connection portion on the plane of the display substrate and the orthographic projection of the third light-emitting element on the plane of the display substrate.
  • the at least one second pixel circuit is electrically connected to at least two light emitting elements, including any one or more of the following:
  • the two light-emitting elements are connected in series to one second pixel circuit, and the two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;
  • the three light-emitting elements are connected in series to one second pixel circuit, and the three light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;
  • the four light-emitting elements are connected in series to one second pixel circuit, and the four light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;
  • the five light-emitting elements are connected in series to one second pixel circuit, and the five light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element.
  • the display substrate includes a semiconductor layer stacked on a substrate, a first gate electrode layer, a second gate electrode layer, a first source-drain electrode layer, a second source-drain electrode layer, and an anode, wherein :
  • the semiconductor layer includes active layers of a plurality of transistors, the first gate electrode layer includes gate electrodes of a plurality of transistors and a plurality of first capacitor electrodes, and the second gate electrode layer includes a plurality of second capacitor electrodes,
  • the first source-drain electrode layer includes a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors, and the second source-drain electrode layer includes connection electrodes;
  • the multiple data fan-out lines are arranged in the same layer as one or more layers of the first gate electrode layer, the second gate electrode layer, and the second source-drain electrode layer.
  • the display substrate includes a light shielding layer stacked on a substrate, a first semiconductor layer, a first gate electrode layer, a second gate electrode layer, a second semiconductor layer, a third gate electrode layer, a source The drain electrode layer and the anode, wherein:
  • the first semiconductor layer includes an active layer of at least one polysilicon transistor, the first gate electrode layer includes a gate electrode of at least one polysilicon transistor and a plurality of first capacitor electrodes, and the second gate electrode layer includes a plurality of first capacitor electrodes.
  • Two capacitor electrodes the second semiconductor layer includes an active layer of at least one oxide transistor, the third gate electrode layer includes a gate electrode of at least one oxide transistor, and the source-drain electrode layer includes a plurality of data lines, source and drain electrodes of a plurality of transistors;
  • the plurality of data fan-out lines are arranged in the same layer as one or more layers of the light shielding layer, the first gate electrode layer, the second gate electrode layer, and the third gate electrode layer.
  • the display substrate further includes an electrode connection layer disposed between the source-drain electrode layer and the anode, and the material of the electrode connection layer is indium tin oxide or indium zinc oxide .
  • At least one of the third sub-pixels includes any one or more of the following dummy electrode lines: a dummy active layer, a dummy gate electrode, a dummy capacitor electrode, a dummy source-drain electrode, and the dummy electrode line Connect to fixed potential signal lines through signal traces.
  • At least one of the third sub-pixels includes a dummy data fan-out line connected to a fixed-potential signal line through a signal trace.
  • An embodiment of the present disclosure also provides a display device, including the display substrate described in any one of the above items.
  • An embodiment of the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a display area and a non-display area surrounding the display area.
  • the display area includes a first display area, a second display area, and a fan-out area. Line area, the second display area is located between the first display area and the fan-out wiring area; the preparation method includes:
  • a plurality of first sub-pixels are formed in the first display area, the first sub-pixels include a first pixel circuit and a first light-emitting element, and the first pixel circuit and the first light-emitting element are on the display substrate Orthographic projections on at least partially overlap; a plurality of second sub-pixels are formed in the second display area, the second sub-pixels include a second pixel circuit and a second light-emitting element, and the second pixel circuit and the first pixel circuit Orthographic projections of the two light-emitting elements on the display substrate at least partially overlap, the first pixel circuit and the second pixel circuit are electrically connected to the plurality of data lines; a plurality of first pixel circuits are formed in the fan-out wiring area Three sub-pixels and multiple data fan-out lines, the third sub-pixel includes a third light-emitting element, at least one second pixel circuit is electrically connected to at least two light-emitting elements, and the at least two light-emitting elements are selected from
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic plan view of a display area in a display substrate
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a working timing diagram of a pixel driving circuit
  • FIG. 7 is a schematic plan view showing a binding region in a substrate
  • FIG. 8 is a schematic diagram of a data fan-out line in a bound area
  • FIG. 9 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 10 is a side view of the substrate shown in Figure 9;
  • FIG. 11 is a schematic diagram of an enlarged structure of area A in FIG. 9;
  • FIG. 12 is a schematic diagram of a fan-out routing structure in the fan-out routing area in FIG. 9;
  • Fig. 13 is another enlarged structural schematic diagram of area A in Fig. 9;
  • Fig. 14 is a kind of cross-sectional structure schematic diagram of B-B' direction in Fig. 12;
  • Fig. 15 is another kind of cross-sectional structure schematic diagram of B-B' direction in Fig. 12;
  • Fig. 16 is a schematic cross-sectional structure diagram of C-C' in Fig. 12 .
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • FIG. 1 is a schematic structural diagram of a display device.
  • an OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data lines ( D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver.
  • a clock signal suitable for the specification of the light emission signal driver, an emission stop signal, etc. may be supplied to the light emission signal driver.
  • the data signal driver may generate data voltages to be supplied to the data lines D1, D2, D3, . . . , and Dn using grayscale values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan signal driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can generate scans in such a way that a scan start signal supplied in the form of a conduction level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal signal, m can be a natural number.
  • the lighting signal driver may generate emission signals to be supplied to the lighting signal lines E1, E2, E3, . . . , and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission signal driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting signal driver can be configured in the form of a shift register, and can generate the light emitting signal in a manner of sequentially transmitting the light emitting stop signal provided in the form of off-level pulses to the next-stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij, and each sub-pixel Pxij may be connected to a corresponding data line, a corresponding scanning signal line, and a corresponding light emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on the other side of the display area 100 .
  • the display area 100 may include a plurality of sub-pixels configured to display dynamic pictures or still images
  • the bonding area 200 may include data fan-out lines connecting a plurality of data lines to the integrated circuit
  • the frame area 300 may include power lines for transmitting voltage signals
  • the binding area 200 and the frame area 300 may include an isolation dam in a ring structure, at least one side of the frame area 300 may be a curled area formed by bending, or both the display area 100 and the frame area 300 are bent or curved areas , the present disclosure is not limited here.
  • the display area may include a plurality of pixel units arranged in a matrix.
  • FIG. 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first color sub-pixel P1 that emits light of the first color, and a sub-pixel P1 that emits light of the second color.
  • the second color sub-pixel P2 and the third color sub-pixel P3 emitting light of the third color, the first color sub-pixel P1, the second color sub-pixel P2 and the third color sub-pixel P3 all include a pixel driving circuit and a light emitting device.
  • the pixel driving circuits in the first color sub-pixel P1, the second color sub-pixel P2 and the third color sub-pixel P3 are respectively connected to the scanning signal line, the data line and the light emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light emitting signal line.
  • the data voltage transmitted by the data line is received, and a corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first color sub-pixel P1, the second-color sub-pixel P2, and the third-color sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting devices are configured to respond to the output of the pixel driving circuit of the sub-pixel.
  • the current emits light of corresponding brightness.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, and blue sub-pixels. and white sub-pixels, the present disclosure is not limited here.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely. Arrangement, the disclosure is not limited here.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the base 101, a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base 101, and a light emitting structure layer 103 disposed on the light emitting layer.
  • the structural layer 103 is away from the encapsulation layer 104 on the side of the substrate 101 .
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and only one transistor 102A and one storage capacitor 102B are taken as an example in FIG. 4 .
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the drive transistor 210 through a via hole, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 304.
  • the layers 303 are connected, and the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of a corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short), and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be A common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light-emitting layer of adjacent sub-pixels can have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 5, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, and the initial signal line INIT extend in the horizontal direction, and the second power line VSS, the first power line VDD, and the data line D Extend vertically.
  • the light emitting device may be an organic electroluminescent diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 6 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 5.
  • the pixel driving circuit in FIG. signal lines (data line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), 7 transistors are P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • Line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data line D is provided to the second node through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. N2, and charge the difference between the data voltage output by the data line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output from the data line D
  • Vdd is the power supply voltage output from the first power line VDD.
  • FIG. 7 is a schematic diagram showing a planar structure of a bonded area in a substrate
  • FIG. 8 is a schematic diagram of a data fan-out line in a bonded area.
  • the binding area 200 in a plane parallel to the display substrate, is located on one side of the display area 100 , and the binding area 200 may include first fan-out areas 201 sequentially arranged along a direction away from the display area 100 , bending area 202 , second fan-out area 203 , antistatic area 204 , driver chip area 205 and binding pin area 206 .
  • the first fan-out area 201 includes at least data fan-out lines, and a plurality of data fan-out lines are configured as data lines (Data Lines) connected to the display area in a fan-out (Fanout) routing manner, as shown in FIG. 8 .
  • the bending area 202 includes a composite insulating layer provided with grooves, configured to bend the binding area 200 to the back of the display area 100 .
  • the second fan-out area 203 includes a plurality of data fan-out lines led out in a fan-out routing manner.
  • the antistatic area 204 includes an antistatic circuit configured to prevent static electricity damage of the display substrate by eliminating static electricity.
  • the driver chip area 205 includes an integrated circuit (Integrated Circuit, IC for short), which is configured to be connected to a plurality of data fan-out lines.
  • the bonding pin area 206 includes a bonding pad (Bonding Pad), which is configured to be bonded and connected to an external flexible circuit board (Flexible Printed Circuit, FPC for short).
  • the left frame, right frame, and upper frame of the display device can be controlled within 1.0mm, but the narrow design of the lower frame (the frame on the side of the binding area) is more difficult, and has been maintained at about 2.0mm. This is because the data fan-out line is usually set in the fan-out area of the binding area, and the fan-out area occupies a large space.
  • the width of the bonding area is smaller than the width of the display area, and the signal lines of the integrated circuits and bonding pads in the bonding area need to be introduced into the wider display area in a fan-out manner through the fan-out area.
  • the display area and the bonding The larger the width difference of the area, the more oblique fan-out lines in the fan-shaped area, the greater the distance between the driver chip area and the display area, and the wider the lower border, resulting in the lower border being much larger than the left and right borders.
  • FIG. 9 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 10 is a side view of the display substrate in FIG. 9
  • the display substrate 10 may include a display area 100 , a binding area 500 located on the side opposite to the first direction D1 of the display area 100 , and a frame area 300 located on the other side of the display area 100 .
  • the display area 100 may be a planarized area, including a plurality of sub-pixels Pxij forming a pixel array to display dynamic pictures or still images
  • the display substrate may be a flexible substrate, so the display substrate may be deformable, For example curled, bent, folded or rolled up.
  • the binding area 500 may include a lead area 501, a bending area 502 and a composite circuit area 503 arranged in sequence along the opposite direction of the first direction D1 (a direction away from the display area), and the lead area 501 is connected to In the display area 100 , the bending area 502 is connected to the lead area 501 , and the composite circuit area 503 is connected to the bending area 502 .
  • the lead area 501 can be provided with a plurality of lead lines, one end of the lead lines is correspondingly connected to a plurality of data lines in the display area 100, and the other end is connected to the integrated circuit in the composite circuit area 503, so that the integrated circuit The data signal is applied to the data line through the pinout.
  • the bending region 502 can be bent with a curvature in the third direction D3, and the surface of the composite circuit region 503 can be reversed, that is, the upward facing surface of the composite circuit region 503 can pass through the bending region 502.
  • the bending is converted to face downward, and the third direction D3 intersects the first direction D1.
  • the composite circuit region 503 may overlap the display region 100 in the third direction D3 (thickness direction).
  • the composite circuit area 503 may include an antistatic area, a driver chip area, and a binding pin area, and an integrated circuit (Integrate Circuit, IC for short) 20 may be bonded and connected to the driver chip area, and a flexible circuit board ( Flexible Printed Circuit (FPC for short) 30 can be bonded and connected in the bonded pin area.
  • the integrated circuit 20 may generate driving signals required for driving the sub-pixels, and may provide the driving signals to the sub-pixels in the display area 100 .
  • the driving signal may be a data signal for driving the luminance of sub-pixels.
  • the integrated circuit 20 can be bonded and connected to the driver chip area through an anisotropic conductive film or other methods, and the width of the integrated circuit 20 in the second direction D2 can be smaller than that of the composite circuit area 503 in the second direction D2.
  • the width above, the second direction D2 intersects with the first direction D1.
  • the bonding pin area may be provided with pads including a plurality of pins (PINs), and the flexible circuit board 30 may be bonded to the pads.
  • the first direction D1 may be the extending direction (column direction) of the data lines in the display area
  • the second direction D2 may be the extending direction (row direction) of the scanning signal lines in the display area
  • the third direction D3 may be It may be a direction perpendicular to the plane of the display substrate, the first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.
  • the display area 100 includes a base, a first display area 100a, a second display area 100b, and a fan-out routing area 100c disposed on the base, and the second display area 100b is located on the first Between the display area 100a and the fan-out wiring area 100c.
  • FIG. 11 is an enlarged structural diagram of area A in FIG. 9
  • FIG. 12 is a schematic diagram of a fan-out wiring arrangement structure in the fan-out wiring area 100c in FIG. 9 .
  • the display area 100 may include a plurality of sub-pixels, a plurality of data lines DA and a plurality of data fan-out lines 700.
  • the projections are at least partially overlapping; the lead area 501 of the bonding area may include a plurality of lead wires 600 .
  • a plurality of sub-pixels in the display area 100 are arranged in a matrix to form a plurality of pixel rows and a plurality of pixel columns.
  • a plurality of data lines DA in the display area 100 extend along the first direction D1 or the opposite direction of the first direction D1, and are sequentially arranged at set intervals along the second direction D2, and each data line DA in the display area 100 Connects to all subpixels of a pixel column.
  • the multiple lead-out lines 600 of the lead-out area 501 are sequentially arranged at set intervals along the second direction D2, the first ends of the multiple lead-out lines 600 are located at the edge B of the display area, and the second ends of the multiple lead-out lines 600 are directed away from the display area.
  • the direction of the zone extends to the bend zone.
  • the first ends of the multiple data fan-out lines 700 in the display area 100 are located at the edge B of the display area, correspondingly connected to the first ends of a part of the lead-out lines 600 in the lead area 501, and the second ends of the multiple data fan-out lines 700 are directed away from the lead lines.
  • the direction of the area extends, and is correspondingly connected to a part of the data lines DA of the display area 100 .
  • a part of the lead-out lines 600 in the lead-out area 501 is connected to the data fan-out line 700 , and another part of the lead-out lines 600 is correspondingly connected to another part of the data lines DA extending to the lead-out area 501 .
  • the edge B of the display area may be an edge of the display area 100 on a side close to the lead area 501 .
  • the first display area 100a may include a plurality of first sub-pixels P11, the first sub-pixels P11 may include a first pixel circuit P11a and a first light emitting element P11b, the first pixel circuit P11a and a first light emitting element Orthographic projections of elements P11b on the display substrate at least partially overlap;
  • the second display area 100b may include a plurality of second sub-pixels P12, and the second sub-pixels P12 may include second pixel circuits P12a and second light-emitting elements P12b, the second pixel
  • the orthographic projections of the circuit P12a and the second light-emitting element P12b on the display substrate are at least partially overlapped, and the first pixel circuit P11a and the second pixel circuit P12a are electrically connected to multiple data lines DA;
  • the fan-out wiring area 100c may include multiple data fan lines Outline 700 and a plurality of third sub-pixels P13, the third sub-pixel P13 includes a third light
  • At least one second pixel circuit P12a is electrically connected to at least two light emitting elements, including any one or more of the following:
  • At least one second pixel circuit P12a is electrically connected to at least two second light emitting elements P12b;
  • At least one second pixel circuit P12a is electrically connected to at least two third light emitting elements P13b;
  • At least one second pixel circuit P12a is electrically connected to at least one second light emitting element P12b and at least one third light emitting element P13b.
  • the data line DA and the data fan-out line 700 may be disposed in different film layers, and an insulating layer is disposed between the data line DA and the data fan-out line 700 .
  • the lead-out line 600 and the data fan-out line 700 may be disposed in the same film layer and formed simultaneously through the same patterning process, and the lead-out line 600 and the data fan-out line 700 may be an integral structure connected to each other.
  • the lead-out line 600 and the data fan-out line 700 may be disposed in different film layers, an insulating layer is disposed between the two, and the two are connected through via holes.
  • the plurality of lead-out lines 600 may be arranged to be parallel to the first direction D1, that is, the lead-out lines 600 are parallel to the data line DA.
  • the orthographic projection of any lead-out line 600 on the substrate does not overlap with the orthographic projections of other lead-out lines 600 on the substrate, and the orthographic projection of any data fan-out line 700 on the base does not overlap with other data fan-out lines
  • the orthographic projection of 700 on the base has no overlapping areas.
  • the orthographic projection of the second pixel circuit P12a on the plane of the display substrate and the orthographic projection of the third light emitting element P13b on the plane of the display substrate do not overlap. That is, the third sub-pixel P13 has no pixel circuit but only light-emitting elements, and the third sub-pixel P13 is driven by the second pixel circuit P12a.
  • the data fan-out line 700 is a stepped line, and the orthographic projection of the data fan-out line 700 on the display substrate plane is different from the orthographic projection of the first pixel circuit P11a and the second pixel circuit P12a on the display substrate plane. overlapping.
  • the display area 100 includes a first connection line 31 and a second connection line 32
  • the first connection line 31 is configured to connect at least one of the following: the anode of the first light emitting element P11b and the first pixel circuit P11a , the anode of the second light emitting element P12b and the second pixel circuit P12a, the anode of the third light emitting element P13b and the second pixel circuit P12a;
  • the second connection line 32 is configured to connect the anodes of at least two light emitting elements, and the at least two The light emitting element is selected from at least one of the second light emitting element P12b and the third light emitting element P13b.
  • the material of the first connecting wire 31 and the second connecting wire 32 is a transparent conductive material.
  • the data fan-out line 700 includes at least one horizontal connecting portion 700a extending along the second direction D2 and at least one vertical connecting portion 700b extending along the first direction D1, and the second direction D2 Intersect with the first direction D1, the first direction D1 is parallel to the data line DA, the orthographic projection of the horizontal connection part 700a on the display substrate plane does not overlap with the orthographic projection of the third light-emitting element P13b on the display substrate plane, and the vertical connection part 700b There is at least an overlapping area between the orthographic projection on the display substrate plane and the orthographic projection of the third light emitting element P13b on the display substrate plane.
  • the fan-out wiring area includes light emitting elements of a first color, light emitting elements of a second color and light emitting elements of a third color, and the second connection line 32 is configured to connect anodes of at least two light emitting elements of a third color.
  • the third color light emitting element may be a green light emitting element or light emitting elements of other colors.
  • the third sub-pixel further includes a third pixel circuit
  • the orthographic projection of the third pixel circuit on the display substrate is at least partly the same as the orthographic projection of the first-color light-emitting element or the second-color light-emitting element on the display substrate. overlap, and do not overlap with the orthographic projection of the light-emitting element of the third color on the display substrate.
  • the second connecting wire 32 is further configured to connect at least one of: anodes of at least two light emitting elements of the first color, anodes of at least two light emitting elements of the second color.
  • the first color light emitting element may be a red light emitting element
  • the second color light emitting element may be a blue light emitting element
  • the first color light emitting element may be a blue light emitting element
  • the second color light emitting element may be a blue light emitting element. It is a red light emitting element.
  • FIG. 13 is a schematic diagram of another enlarged structure of area A in FIG. 9 .
  • at least one second pixel circuit P12a is electrically connected to at least two light emitting elements, including any one or more of the following:
  • Two light emitting elements are connected in series to a second pixel circuit P12a, and the two light emitting elements are selected from at least one of the second light emitting element and the third light emitting element;
  • the three light-emitting elements are connected in series to a second pixel circuit P12a, and the three light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;
  • the four light emitting elements are connected in series to a second pixel circuit P12a, and the four light emitting elements are selected from at least one of the second light emitting element and the third light emitting element;
  • the five light emitting elements are connected in series and connected to a second pixel circuit P12a, and the five light emitting elements are selected from at least one of the second light emitting element and the third light emitting element.
  • the number of data fan-out lines 700 is less than or equal to the number of data lines DA.
  • At least one third sub-pixel P13 includes a dummy data fan-out line 701 , and the dummy data fan-out line 701 is connected to a fixed potential signal line through a signal wire.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer stacked on a substrate, a first gate electrode layer, a second gate electrode layer, a source-drain electrode layer and an anode, the first gate An insulating layer is provided between the electrode layer and the second gate electrode layer, between the second gate electrode layer and the source-drain electrode layer, and between the source-drain electrode layer and the anode, wherein:
  • the semiconductor layer includes active layers of a plurality of transistors, the first gate electrode layer includes a plurality of scanning signal lines, gate electrodes of a plurality of transistors, and a plurality of first capacitor electrodes, and the second gate electrode layer includes a plurality of second capacitor electrodes,
  • the source-drain electrode layer includes a plurality of data lines DA, source electrodes and drain electrodes of a plurality of transistors; the first capacitor electrode and the second capacitor electrode form a capacitor, and the transistor and the capacitor form a pixel circuit;
  • a plurality of data fan-out lines 700 may be disposed on the same layer as one or more layers of the first gate electrode layer and the second gate electrode layer.
  • the display substrate includes a semiconductor layer stacked on a substrate, a first gate electrode layer, a second gate electrode layer, a first source-drain electrode layer, a second source-drain electrode layer and anode, where:
  • the semiconductor layer includes active layers of a plurality of transistors, the first gate electrode layer includes gate electrodes of a plurality of transistors and a plurality of first capacitor electrodes, the second gate electrode layer includes a plurality of second capacitor electrodes, and the first source-drain electrode layer Including a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors, the second source-drain electrode layer includes connection electrodes; the first capacitor electrode and the second capacitor electrode form a capacitor, and the transistor and the capacitor form a pixel circuit;
  • the plurality of data fan-out lines 700 may be arranged in the same layer as one or more layers of the first gate electrode layer, the second gate electrode layer and the second source-drain electrode layer.
  • the display substrate includes a light-shielding layer (not shown in the figure) stacked on the base, a first semiconductor layer, a first gate electrode layer, a second gate electrode layer, a second gate electrode layer, and a second gate electrode layer.
  • a light-shielding layer (not shown in the figure) stacked on the base, a first semiconductor layer, a first gate electrode layer, a second gate electrode layer, a second gate electrode layer, and a second gate electrode layer.
  • Two semiconductor layers, a third gate electrode layer, a source-drain electrode layer and an anode wherein:
  • the first semiconductor layer includes an active layer of at least one polysilicon transistor, the first gate electrode layer includes a gate electrode of at least one polysilicon transistor and a plurality of first capacitor electrodes, the second gate electrode layer includes a plurality of second capacitor electrodes, and the second gate electrode layer includes a plurality of second capacitor electrodes.
  • the semiconductor layer includes an active layer of at least one oxide transistor, the third gate electrode layer includes a gate electrode of at least one oxide transistor, and the source-drain electrode layer includes a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors;
  • the plurality of data fan-out lines 700 may be arranged in the same layer as one or more layers of the light shielding layer, the first gate electrode layer, the second gate electrode layer, and the third gate electrode layer.
  • At least one third subpixel P13 includes any one or more of the following dummy electrode lines 102C: dummy active layer, dummy gate electrode, dummy capacitor electrode, dummy Source-drain electrodes, virtual electrode lines 102C are connected to fixed potential signal lines through signal traces
  • the following is an exemplary description by showing a preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” needs to be patterned during the whole production process, it is called “thin film” before the patterning process, and it is called “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the edge of the display area of the orthographic projection of B falls within the range of A within the edge range of the display area of the orthographic projection, or the edge of the display area of the orthographic projection of A overlaps with the edge of the display area of the orthographic projection of B.
  • the manufacturing process of the display substrate may include the following operations.
  • a semiconductor layer pattern is formed on a substrate.
  • forming the semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, and forming a first insulating layer covering the entire substrate.
  • the semiconductor layer pattern at least includes active layers of a plurality of transistors.
  • the semiconductor layer pattern is formed in the first display area and the second display area.
  • the semiconductor layer pattern may also be formed in the fan-out line area, because the subsequently formed data fan-out line includes at least one section of lateral connection and at least one section of The vertical connection part, the horizontal connection part of the data fan-out line can be arranged between two adjacent sub-pixels, therefore, the horizontal connection part of the data fan-out line does not affect the pixel circuit row in the sub-pixel adjacent to the horizontal connection part In other words, the lateral connection portion of the data fan-out line has little influence on the arrangement of pixel circuits in the sub-pixels adjacent to the lateral connection portion.
  • each sub-pixel in the first display area and the second display area includes a semiconductor layer pattern, and some or all sub-pixels in the fan-out routing area do not include a semiconductor layer pattern.
  • the substrate may be a flexible substrate.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate forming the aforementioned pattern, and patterning the first metal film through a patterning process to form a covering
  • the second insulating layer of the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes a plurality of data fan-out lines, a plurality of scanning signal lines, and a plurality of transistors located in the display area
  • the gate electrode and the plurality of first capacitor electrodes, as well as the plurality of lead-out lines located in the lead-out area of the binding area, the data fan-out lines and the lead-out lines may be an integral structure connected to each other.
  • the data fan-out line is formed in the fan-out routing region, and in an exemplary embodiment, the first conductive layer may be referred to as a first gate electrode (GATE 1) layer.
  • GATE 1 first gate electrode
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate forming the aforementioned pattern, and patterning the second metal film through a patterning process to form a covering
  • the third insulating layer of the first conductive layer pattern, and the second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least includes a plurality of second capacitor electrodes located in the display area.
  • the second conductive layer may be referred to as a second gate electrode (GATE 2) layer.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate forming the aforementioned pattern, patterning the fourth insulating film through a patterning process, and forming a pattern covering the second conductive layer.
  • a plurality of via holes are opened on the fourth insulating layer, and the plurality of via holes may include: active via holes located at the positions of the plurality of active layers in the display area, and data fan-out terminals located in the display area A plurality of first vias and second vias in the section. The active via holes expose the active layer, the first via holes expose the data fan-out lines, and the second via holes expose the lead lines.
  • forming the third conductive layer pattern may include: depositing a third metal thin film on the substrate forming the aforementioned pattern, patterning the third metal thin film through a patterning process, and forming a third metal thin film on the fourth insulating layer.
  • the third conductive layer pattern at least includes: a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors, the source electrodes and drain electrodes are respectively connected to the corresponding active layer through active via holes, and the plurality of data lines
  • the wires extend to the lead area of the binding area, a part of the data wires are connected to the data fan-out wires through the first via holes, and the other part of the data wires are connected to the lead wires through the second via holes.
  • the third conductive layer may be referred to as a first source-drain electrode (SD1) layer.
  • forming the pattern of the electrode connection layer may include: sequentially depositing a fifth insulating film and an electrode connection layer film on the substrate on which the aforementioned pattern is formed; Patterning is performed to form a fifth insulating layer covering the pattern of the third conductive layer, and an electrode connection layer pattern disposed on the fifth insulating layer. A plurality of third via holes are opened on the fifth insulating layer, and the third via holes The fifth insulating layer is removed, exposing the surface of the drain electrodes of the plurality of transistors.
  • the electrode connection layer pattern includes at least a plurality of first and second connection lines insulated from each other, and one end of the first connection line is connected to the drain electrode of the transistor through a third via hole, and the first connection line is formed in the first display area , the second display area and the fan-out wiring area, the second connection line is formed in the second display area and the fan-out wiring area, and the first connection line is configured to make the anode of the first light-emitting element formed subsequently and a part of the second light-emitting element
  • the anode and a part of the anodes of the third light-emitting element are connected to the drain electrode of the transistor, and the second connection line is configured to connect the anodes of the second light-emitting element and the anodes of the third light-emitting element formed subsequently to each other.
  • Forming a flat layer pattern may include: coating a flat film on the substrate on which the aforementioned pattern is formed, patterning the flat film by a patterning process, forming a flat layer covering the electrode connection layer, and forming a flat layer on the flat layer.
  • a fourth via hole and a fifth via hole are provided, the fourth via hole exposes the other end of the first connection line, the fifth via hole exposes both ends of the second connection line, and the fourth via hole is configured so that the subsequently formed
  • the anode of the first light-emitting element, a part of the anode of the second light-emitting element, and a part of the anode of the third light-emitting element are connected to the other end of the first connection line through the via hole, and the fifth via hole is configured to make the subsequently formed second light-emitting element
  • the anode of the anode and the anode of the third light-emitting element are connected to the second connection line through the via hole.
  • An anode pattern is formed.
  • forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the foregoing pattern is formed, and patterning the transparent conductive film by a patterning process to form the anode disposed on the planar layer.
  • the anode of the first light-emitting element, a part of the anode of the second light-emitting element, and a part of the anode of the third light-emitting element are connected to the other end of the first connection line through the fourth via hole, and the anode of the second light-emitting element and the anode of the third light-emitting element The two are connected to the second connection line through the fifth via hole.
  • the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposed anode.
  • the organic light-emitting layer is formed by vapor deposition or ink-jet printing process, and the cathode is formed on the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer, as shown in FIG. 16 .
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, and the third conductive layer may use metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • One or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single layer structure, or a multilayer composite structure, such as Mo/Cu/Mo, etc.
  • the material of the electrode connection layer is a transparent conductive material, specifically indium tin oxide ITO or indium zinc oxide IZO.
  • any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) can be used for the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer.
  • One or more, can be a single layer, multi-layer or composite layer.
  • the first insulating layer is called the buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the flat layer can be made of organic material, and the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO.
  • the active layer can be made of polysilicon (p-Si), that is, the present disclosure is applicable to LTPS thin film transistors.
  • this embodiment shows that the preparation process of the substrate is described by taking the data fan-out line arranged on the first conductive layer and the data line arranged on the third conductive layer as an example, in this disclosure, the data fan-out line and the data line can be arranged on any layer In this case, as long as it is ensured that the data lines and the data fan-out lines are located in different conductive layers, the present disclosure is not limited here.
  • the structure of the display substrate and its preparation process shown in the present disclosure are only exemplary illustrations.
  • the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs, which is not limited in the present disclosure.
  • the binding area is provided with a fan-out area, and the data lines in the display area are led out through the data fan-out lines in the fan-out area. Since there are many oblique lines in the fan-shaped area, the lower frame is wider, which is not conducive to the realization of Narrow bezels.
  • the lead-out line is set in the lead-out area of the binding area, and the data fan-out line is set in the display area, and the lead-out line is connected to the corresponding data signal line through the data fan-out line, which not only realizes multiple lead-out lines Corresponding connection with multiple data signal lines, and makes it unnecessary to set fan-shaped oblique lines in the lead area, and multiple lead lines are vertical lines parallel to each other, which can be directly introduced into the composite circuit area of the bonding area, effectively reducing The length in the vertical direction of the lead area is reduced, and the width of the lower frame is greatly reduced, so that the width of the upper frame, lower frame, left frame and right frame of the display device is similar, all of which are less than 1.0 mm, which improves the screen ratio and is conducive to Realize full screen display.
  • the second pixel circuit by disposing the second pixel circuit in the sub-pixel of the second display region, no pixel circuit is disposed in the sub-pixel of the fan-out wiring region, and only the third light-emitting element is disposed, the second pixel circuit can Driving the second light-emitting element can also drive the third light-emitting element, so that enough space can be left in the fan-out wiring area for data fan-out wiring.
  • At least one third sub-pixel in the fan-out wiring area, can be provided with any one or more of the following dummy electrode lines 102C: dummy active layer, dummy gate electrode, The dummy capacitor electrodes, dummy source-drain electrodes, and dummy electrode lines can be connected to fixed potential signal lines through signal traces.
  • Exemplary embodiments of the present disclosure can improve the uniformity of the manufacturing process of the display substrate by arranging the dummy electrode lines in at least one third sub-pixel, thereby improving the manufacturing quality.
  • An exemplary embodiment of the present disclosure also provides a method for preparing a display substrate, the display substrate includes a display area and a non-display area surrounding the display area, and the display area includes a first display area, a second display area, and a fan-out wiring area , the second display area is located between the first display area and the fan-out wiring area; the preparation method includes:
  • a plurality of first sub-pixels are formed in the first display area, the first sub-pixels include a first pixel circuit and a first light-emitting element, and the orthographic projections of the first pixel circuit and the first light-emitting element on the display substrate at least partially overlap;
  • the second display area forms a plurality of second sub-pixels, the second sub-pixels include a second pixel circuit and a second light-emitting element, the orthographic projections of the second pixel circuit and the second light-emitting element on the display substrate are at least partially overlapped, and the first pixel circuit and the second pixel circuit are electrically connected to a plurality of data lines; a plurality of third sub-pixels and a plurality of data fan-out lines are formed in the fan-out wiring area, the third sub-pixel includes a third light-emitting element, at least one second pixel circuit is connected to at least one The two light emitting elements are electrically connected, at least two light emitting elements are selected from at least one of
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments.
  • the display device can be: mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, advertising panel, watch phone, e-book portable multimedia player or display screen of various products of the Internet of Things, etc. products or components.
  • the display device may be a wearable display device that can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板（10）及其制备方法、显示装置，显示基板（10）包括显示区域（100）以及包围显示区域（100）的非显示区域，显示区域（100）包括第一显示区（100a）、第二显示区（100b）和扇出走线区（100c），第二显示区（100b）位于第一显示区（100a）和扇出走线区（100c）之间；第一显示区（100a）包括多个第一子像素（P11），第一子像素（P11）包括第一像素电路（P11a）和第一发光元件（P11b）；第二显示区（100b）包括多个第二子像素（P12），第二子像素（P12）包括第二像素电路（P12a）和第二发光元件（P12b）；扇出走线区（100c）包括多条数据扇出线（700）和多个第三子像素（P13），第三子像素（P13）包括第三发光元件（P13b），至少一个第二像素电路（P12b）与至少两个发光元件电连接，至少两个发光元件选自第二发光元件（P12b）、第三发光元件（P13b）中的至少一种，多条数据扇出线（700）与多条数据线（DA）电连接。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括显示区域以及围绕所述显示区域的非显示区域，所述显示区域包括第一显示区、第二显示区和扇出走线区，所述第二显示区位于所述第一显示区和所述扇出走线区之间；
多条数据线，位于所述显示区域；
所述第一显示区包括多个第一子像素，所述第一子像素包括第一像素电路和第一发光元件，所述第一像素电路和所述第一发光元件在所述显示基板上的正投影至少部分重叠；
所述第二显示区包括多个第二子像素，所述第二子像素包括第二像素电路和第二发光元件，所述第二像素电路和所述第二发光元件在所述显示基板上的正投影至少部分重叠；
所述第一像素电路和所述第二像素电路与所述多条数据线电连接；
所述扇出走线区包括多条数据扇出线和多个第三子像素，所述第三子像素包括第三发光元件，至少一个所述第二像素电路与至少两个发光元件电连接，所述至少两个发光元件选自所述第二发光元件、所述第三发光元件中的至少一种，所述多条数据扇出线与所述多条数据线电连接。
在示例性实施方式中，所述第二像素电路在所述显示基板平面上的正投影和所述第三发光元件在所述显示基板平面上的正投影不重叠。
在示例性实施方式中，所述数据扇出线为阶梯状走线，所述数据扇出线在所述显示基板平面上的正投影与所述第一像素电路和所述第二像素电路在所述显示基板平面上的正投影不重叠。
在示例性实施方式中，所述显示区域包括第一连接线和第二连接线，所述第一连接线被配置为连接以下至少之一：所述第一像素电路与所述第一发光元件的阳极、所述第二像素电路与所述第二发光元件的阳极、所述第二像素电路与所述第三发光元件的阳极；所述第二连接线被配置为连接所述至少两个发光元件的阳极。
在示例性实施方式中，所述第一连接线和第二连接线的材料为透明导电材料。
在示例性实施方式中，所述扇出走线区包括第一颜色发光元件、第二颜色发光元件和第三颜色发光元件，所述第二连接线被配置为连接至少两个所述第三颜色发光元件的阳极。
在示例性实施方式中，所述第三颜色发光元件为绿色发光元件。
在示例性实施方式中，所述第三子像素还包括第三像素电路，所述第三像素电路在所述显示基板上的正投影与所述第一颜色发光元件或第二颜色发光元件在所述显示基板上的正投影至少部分重叠，且与所述第三颜色发光元件在所述显示基板上的正投影不重叠。
在示例性实施方式中，所述第二连接线还被配置为连接以下至少之一：至少两个所述第一颜色发光元件的阳极、至少两个所述第二颜色发光元件的阳极。
在示例性实施方式中，所述数据扇出线包括至少一个横向连接部和至少 一个纵向连接部，所述横向连接部在所述显示基板平面上的正投影与所述第三发光元件在所述显示基板平面上的正投影不重叠，所述纵向连接部在所述显示基板平面上的正投影与所述第三发光元件在所述显示基板平面上的正投影至少存在重叠区域。
在示例性实施方式中，所述至少一个第二像素电路与至少两个发光元件电连接，包括以下任意一种或多种：
两个所述发光元件串联连接后与一个所述第二像素电路连接，两个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种；
三个所述发光元件串联连接后与一个所述第二像素电路连接，三个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种；
四个所述发光元件串联连接后与一个所述第二像素电路连接，四个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种；
五个所述发光元件串联连接后与一个所述第二像素电路连接，五个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种。
在示例性实施方式中，所述显示基板包括在基底上叠设的半导体层、第一栅电极层、第二栅电极层、第一源漏电极层、第二源漏电极层和阳极，其中：
所述半导体层包括多个晶体管的有源层，所述第一栅电极层包括多个晶体管的栅电极和多个第一电容电极，所述第二栅电极层包括多个第二电容电极，所述第一源漏电极层包括多条数据线、多个晶体管的源电极和漏电极，所述第二源漏电极层包括连接电极；
所述多条数据扇出线与所述第一栅电极层、第二栅电极层、第二源漏电极层中的一层或多层同层设置。
在示例性实施方式中，所述显示基板包括在基底上叠设的遮光层、第一半导体层、第一栅电极层、第二栅电极层、第二半导体层、第三栅电极层、源漏电极层和阳极，其中：
所述第一半导体层包括至少一个多晶硅晶体管的有源层，所述第一栅电极层包括至少一个多晶硅晶体管的栅电极和多个第一电容电极，所述第二栅 电极层包括多个第二电容电极，所述第二半导体层包括至少一个氧化物晶体管的有源层，所述第三栅电极层包括至少一个氧化物晶体管的栅电极，所述源漏电极层包括多条数据线、多个晶体管的源电极和漏电极；
所述多条数据扇出线与所述遮光层、第一栅电极层、第二栅电极层、第三栅电极层中的一层或多层同层设置。
在示例性实施方式中，所述显示基板还包括电极连接层，所述电极连接层设置在源漏电极层和所述阳极之间，所述电极连接层的材料为氧化铟锡或氧化铟锌。
在示例性实施方式中，至少一个所述第三子像素包括以下任意一种或多种虚拟电极线：虚拟有源层、虚拟栅电极、虚拟电容电极、虚拟源漏电极，所述虚拟电极线通过信号走线连接至固定电位信号线。
在示例性实施方式中，至少一个所述第三子像素包括虚拟数据扇出线，所述虚拟数据扇出线通过信号走线连接至固定电位信号线。
本公开实施例还提供了一种显示装置，包括如以上任一项所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域以及围绕所述显示区域的非显示区域，所述显示区域包括第一显示区、第二显示区和扇出走线区，所述第二显示区位于所述第一显示区和所述扇出走线区之间；所述制备方法包括：
在所述第一显示区形成多个第一子像素，所述第一子像素包括第一像素电路和第一发光元件，所述第一像素电路和所述第一发光元件在所述显示基板上的正投影至少部分重叠；在所述第二显示区形成多个第二子像素，所述第二子像素包括第二像素电路和第二发光元件，所述第二像素电路和所述第二发光元件在所述显示基板上的正投影至少部分重叠，所述第一像素电路和所述第二像素电路与所述多条数据线电连接；在所述扇出走线区形成多个第三子像素和多条数据扇出线，所述第三子像素包括第三发光元件，至少一个所述第二像素电路与至少两个发光元件电连接，所述至少两个发光元件选自所述第二发光元件、所述第三发光元件中的至少一种，所述多条数据扇出线 与所述多条数据线电连接。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7为一种显示基板中绑定区域的平面结构示意图；
图8为一种绑定区域中数据扇出线的示意图；
图9为本公开示例性实施例一种显示基板的平面结构示意图；
图10为图9中显示基板的侧视图；
图11为图9中A区域的一种放大结构示意图；
图12为图9中扇出走线区的一种扇出走线排布结构示意图；
图13为图9中A区域的另一种放大结构示意图；
图14为图12中B-B’向的一种剖面结构示意图；
图15为图12中B-B’向的另一种剖面结构示意图；
图16为图12中C-C’向的一种剖面结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、 扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij，每个子像素Pxij可以连接到对应的数据线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据线的子像素。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。显示区域100可以包括配置为显示动态图片或静止图像的多个子像素，绑定区域200可以包括将多个数据线连接至集成电路的数据扇出线，边框区域300可以包括传输电压信号的电源线，绑定区域200和边框区域300可以包括环形结构的隔离坝，边框区域300的至少一侧可以是通过弯折形成的卷曲区域，或者，显示区域100和边框区域300均是弯折或弯曲的区域，本公开在此不做限定。
在示例性实施方式中，显示区域可以包括以矩阵方式排布的多个像素单 元。图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一颜色子像素P1、出射第二颜色光线的第二颜色子像素P2和出射第三颜色光线的第三颜色子像素P3，第一颜色子像素P1、第二颜色子像素P2和第三颜色子像素P3均包括像素驱动电路和发光器件。第一颜色子像素P1、第二颜色子像素P2和第三颜色子像素P3中的像素驱动电路分别与扫描信号线、数据线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据线传输的数据电压，向所述发光器件输出相应的电流。第一颜色子像素P1、第二颜色子像素P2和第三颜色子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的形状可以是矩形、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图4中仅以一个晶体管102A和一个存储电容102B作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304， 阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图5为一种像素驱动电路的等效电路示意图。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。 当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提 供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电 流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图7为一种显示基板中绑定区域的平面结构示意图，图8为一种绑定区域中数据扇出线的示意图。如图7所示，在平行于显示基板的平面内，绑定区域200位于显示区域100的一侧，绑定区域200可以包括沿着远离显示区域100的方向依次设置的第一扇出区201、弯折区202、第二扇出区203、防静电区204、驱动芯片区205和绑定引脚区206。第一扇出区201至少包括数据扇出线，多条数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据线(Data Line)，如图8所示。弯折区202包括设置有凹槽的复合绝缘层，被配置为使绑定区域200弯折到显示区域100的背面。第二扇出区203包括以扇出走线方式引出的多条数据扇出线。防静电区204包括防静电电路，被配置为通过消除静电防止显示基板的静电损伤。驱动芯片区205包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区206包括绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。目前，显示装置的左边框、右边框和上边框可以控制在1.0mm以内，但下边框(绑定区域一侧的边框)的窄化设计难度较大，一直维持在2.0mm左右。这是因为数据扇出线通常设置在绑定区域的扇出区，而扇出区占用空间较大。通常，绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，则下边框就越宽，导致下边框比左边框和右边框大很多。
图9为本公开示例性实施例一种显示基板的平面结构示意图，图10为图9中显示基板的侧视图。如图9和图10所示，显示基板10可以包括显示区域100、位于显示区域100第一方向D1的反方向一侧的绑定区域500以及位 于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦化区域，包括组成像素阵列的多个子像素Pxij，以显示动态图片或静止图像，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域500可以包括沿着第一方向D1的反方向(远离显示区域方向)依次设置的引线区501、弯折区502和复合电路区503，引线区501连接到显示区域100，弯折区502连接到引线区501，复合电路区503连接到弯折区502。
在示例性实施方式中，引线区501可以设置多条引出线，多条引出线的一端与显示区域100中的多条数据线对应连接，另一端连接复合电路区503的集成电路，使得集成电路通过引出线将数据信号施加到数据线。
在示例性实施方式中，弯折区502可以在第三方向D3上以一曲率弯曲，可以将复合电路区503的表面反转，即复合电路区503朝向上方的表面可以通过弯折区502的弯曲转换成面朝向下方，第三方向D3与第一方向D1交叉。在示例性实施方式中，当弯折区502被弯曲时，复合电路区503可以在第三方向D3(厚度方向)上与显示区域100重叠。
在示例性实施方式中，复合电路区503可以包括防静电区、驱动芯片区和绑定引脚区，集成电路(Integrate Circuit，简称IC)20可以绑定连接在驱动芯片区，柔性电路板(Flexible Printed Circuit，简称FPC)30可以绑定连接在绑定引脚区。在示例性实施方式中，集成电路20可以产生用于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是驱动子像素发光亮度的数据信号。在示例性实施方式中，集成电路20可以通过各向异性导电膜或者其它方式绑定连接在驱动芯片区，集成电路20在第二方向D2上的宽度可以小于复合电路区503在第二方向D2上的宽度，第二方向D2与第一方向D1交叉。在示例性实施方式中，绑定引脚区可以设置包括多个引脚(PIN)的焊盘，柔性电路板30可以绑定连接到焊盘上。
在示例性实施方式中，第一方向D1可以是显示区域中数据线的延伸方向(列方向)，第二方向D2可以是显示区域中扫描信号线的延伸方向(行 方向)，第三方向D3可以是垂直于显示基板平面的方向，第一方向D1和第二方向D2可以相互垂直，第一方向D1和第三方向D3可以相互垂直。
在示例性实施方式中，如图9所示，显示区域100包括基底以及设置在基底上的第一显示区100a、第二显示区100b和扇出走线区100c，第二显示区100b位于第一显示区100a和扇出走线区100c之间。图11为图9中A区域的一种放大结构示意图，图12为图9中扇出走线区100c的一种扇出走线排布结构示意图。如图11和图12所示，显示区域100可以包括多个子像素、多条数据线DA和多条数据扇出线700，多条数据线DA和多条数据扇出线700在显示基板平面上的正投影至少部分重叠；绑定区域的引线区501可以包括多条引出线600。在示例性实施方式中，显示区域100中的多个子像素以矩阵方式排布，形成多个像素行和多个像素列。显示区域100中的多条数据线DA沿着第一方向D1或者第一方向D1的反方向延伸，并沿着第二方向D2以设定的间隔顺序设置，每条数据线DA在显示区域100与一个像素列的所有子像素连接。引线区501的多条引出线600沿着第二方向D2以设定的间隔顺序设置，多条引出线600的第一端位于显示区域边缘B，多条引出线600的第二端向着远离显示区域的方向延伸到弯折区。显示区域100中的多条数据扇出线700的第一端位于显示区域边缘B，与引线区501的一部分引出线600的第一端对应连接，多条数据扇出线700的第二端向着远离引线区的方向延伸，并与显示区域100的一部分数据线DA对应连接。引线区501中的一部分引出线600与数据扇出线700连接，另一部分引出线600与延伸到引线区501的另一部分数据线DA对应连接。在示例性实施方式中，显示区域边缘B可以是显示区域100靠近引线区501一侧的边缘。
在示例性实施方式中，第一显示区100a可以包括多个第一子像素P11，第一子像素P11可以包括第一像素电路P11a和第一发光元件P11b，第一像素电路P11a和第一发光元件P11b在显示基板上的正投影至少部分重叠；第二显示区100b可以包括多个第二子像素P12，第二子像素P12可以包括第二像素电路P12a和第二发光元件P12b，第二像素电路P12a和第二发光元件P12b在显示基板上的正投影至少部分重叠，第一像素电路P11a和第二像素电路P12a与多条数据线DA电连接；扇出走线区100c可以包括多条数据扇 出线700和多个第三子像素P13，第三子像素P13包括第三发光元件P13b；至少一个第二像素电路P12a与至少两个发光元件电连接，所述至少两个发光元件选自第二发光元件P12b和第三发光元件P13b中的至少一种，多条数据扇出线700与多条数据线DA电连接。
在示例性实施方式中，至少一个第二像素电路P12a与至少两个发光元件电连接，包括以下任意一种或多种：
至少一个第二像素电路P12a与至少两个第二发光元件P12b电连接；
至少一个第二像素电路P12a与至少两个第三发光元件P13b电连接；
至少一个第二像素电路P12a与至少一个第二发光元件P12b以及至少一个第三发光元件P13b电连接。
在示例性实施方式中，数据线DA和数据扇出线700可以设置在不同的膜层中，且数据线DA与数据扇出线700之间设置有绝缘层。
在示例性实施方式中，引出线600和数据扇出线700可以设置在相同的膜层中，且通过同一次图案化工艺同时形成，引出线600和数据扇出线700可以是相互连接的一体结构。
在示例性实施方式中，引出线600和数据扇出线700可以设置在不同的膜层中，两者之间设置有绝缘层，两者通过过孔实现连接。
在示例性实施方式中，多条引出线600可以设置成均与第一方向D1平行，即引出线600与数据线DA平行。
在示例性实施方式中，任意一条引出线600在基底上的正投影与其它引出线600在基底上的正投影没有重叠区域，任意一条数据扇出线700在基底上的正投影与其它数据扇出线700在基底上的正投影没有重叠区域。
在示例性实施方式中，第二像素电路P12a在显示基板平面上的正投影和第三发光元件P13b在显示基板平面上的正投影不重叠。即，第三子像素P13没有像素电路，只有发光元件，第三子像素P13通过第二像素电路P12a驱动。
在示例性实施方式中，数据扇出线700为阶梯状走线，数据扇出线700 在显示基板平面上的正投影与第一像素电路P11a和第二像素电路P12a在显示基板平面上的正投影不重叠。
在示例性实施方式中，显示区域100包括第一连接线31和第二连接线32，第一连接线31被配置为连接以下至少之一：第一发光元件P11b的阳极与第一像素电路P11a、第二发光元件P12b的阳极与第二像素电路P12a、第三发光元件P13b的阳极与第二像素电路P12a；第二连接线32被配置为连接至少两个发光元件的阳极，该至少两个发光元件选自第二发光元件P12b和第三发光元件P13b中的至少一种。
在示例性实施方式中，第一连接线31和第二连接线32的材料为透明导电材料。
在示例性实施方式中，如图12所示，数据扇出线700包括至少一个沿第二方向D2延伸的横向连接部700a和至少一个沿第一方向D1延伸的纵向连接部700b，第二方向D2与第一方向D1交叉，第一方向D1与数据线DA平行，横向连接部700a在显示基板平面上的正投影与第三发光元件P13b在显示基板平面上的正投影不重叠，纵向连接部700b在显示基板平面上的正投影与第三发光元件P13b在显示基板平面上的正投影至少存在重叠区域。
在示例性实施方式中，扇出走线区包括第一颜色发光元件、第二颜色发光元件和第三颜色发光元件，第二连接线32被配置为连接至少两个第三颜色发光元件的阳极。
在示例性实施方式中，第三颜色发光元件可以为绿色发光元件或其他颜色的发光元件。
在示例性实施方式中，第三子像素还包括第三像素电路，第三像素电路在显示基板上的正投影与第一颜色发光元件或第二颜色发光元件在显示基板上的正投影至少部分重叠，且与第三颜色发光元件在显示基板上的正投影不重叠。
在示例性实施方式中，第二连接线32还被配置为连接以下至少之一：至少两个第一颜色发光元件的阳极、至少两个第二颜色发光元件的阳极。
在示例性实施方式中，第一颜色发光元件可以为红色发光元件，第二颜 色发光元件可以为蓝色发光元件，或者，第一颜色发光元件可以为蓝色发光元件，第二颜色发光元件可以为红色发光元件。
图13为图9中A区域的另一种放大结构示意图。在示例性实施方式中，如图13所示，至少一个第二像素电路P12a与至少两个发光元件电连接，包括以下任意一种或多种：
两个发光元件串联连接后与一个第二像素电路P12a连接，两个发光元件选自第二发光元件、第三发光元件中的至少一种；
三个所述发光元件串联连接后与一个第二像素电路P12a连接，三个发光元件选自第二发光元件、第三发光元件中的至少一种；
四个发光元件串联连接后与一个第二像素电路P12a连接，四个发光元件选自第二发光元件、第三发光元件中的至少一种；
五个发光元件串联连接后与一个第二像素电路P12a连接，五个发光元件选自第二发光元件、第三发光元件中的至少一种。
在示例性实施方式中，数据扇出线700的数量小于或等于数据线DA的数量。
在示例性实施方式中，如图12所示，至少一个第三子像素P13包括虚拟数据扇出线701，虚拟数据扇出线701通过信号走线连接至固定电位信号线。
在示例性实施方式中，在垂直于显示基板的平面内，显示基板包括在基底上叠设的半导体层、第一栅电极层、第二栅电极层、源漏电极层和阳极，第一栅电极层和第二栅电极层之间、第二栅电极层和源漏电极层之间、源漏电极层和阳极之间均设置有绝缘层，其中：
半导体层包括多个晶体管的有源层，第一栅电极层包括多条扫描信号线、多个晶体管的栅电极和多个第一电容电极，第二栅电极层包括多个第二电容电极，源漏电极层包括多条数据线DA、多个晶体管的源电极和漏电极；第一电容电极和第二电容电极组成电容，晶体管和电容组成像素电路；
多条数据扇出线700可以与第一栅电极层和第二栅电极层中的一层或多层同层设置。
在示例性实施方式中，如图14所示，显示基板包括在基底上叠设的半导体层、第一栅电极层、第二栅电极层、第一源漏电极层、第二源漏电极层和阳极，其中：
半导体层包括多个晶体管的有源层，第一栅电极层包括多个晶体管的栅电极和多个第一电容电极，第二栅电极层包括多个第二电容电极，第一源漏电极层包括多条数据线、多个晶体管的源电极和漏电极，第二源漏电极层包括连接电极；第一电容电极和第二电容电极组成电容，晶体管和电容组成像素电路；
多条数据扇出线700可以与第一栅电极层、第二栅电极层和第二源漏电极层中的一层或多层同层设置。
在示例性实施方式中，如图15所示，显示基板包括在基底上叠设的遮光层(图中未示出)、第一半导体层、第一栅电极层、第二栅电极层、第二半导体层、第三栅电极层、源漏电极层和阳极，其中：
第一半导体层包括至少一个多晶硅晶体管的有源层，第一栅电极层包括至少一个多晶硅晶体管的栅电极和多个第一电容电极，第二栅电极层包括多个第二电容电极，第二半导体层包括至少一个氧化物晶体管的有源层，第三栅电极层包括至少一个氧化物晶体管的栅电极，源漏电极层包括多条数据线、多个晶体管的源电极和漏电极；
多条数据扇出线700可以与遮光层、第一栅电极层、第二栅电极层、第三栅电极层中的一层或多层同层设置。
在示例性实施方式中，如图14或图15所示，至少一个第三子像素P13包括以下任意一种或多种虚拟电极线102C：虚拟有源层、虚拟栅电极、虚拟电容电极、虚拟源漏电极，虚拟电极线102C通过信号走线连接至固定电位信号线
下面通过显示基板的一种制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中 的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”或“B的正投影位于“A的正投影范围之内”，是指B的正投影的显示区域边缘落入A的正投影的显示区域边缘范围内，或者A的正投影的显示区域边缘与B的正投影的显示区域边缘重叠。
在一种示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括多个晶体管的有源层。半导体层图案形成在第一显示区和第二显示区，在示例性实施方式中，半导体层图案也可以形成在扇出走线区，由于后续形成的数据扇出线包括至少一段横向连接部和至少一段竖向连接部，数据扇出线的横向连接部可以设置在相邻的两个子像素之间，因此，数据扇出线的横向连接部不影响与该横向连接部相邻的子像素中的像素电路排布，或者说，数据扇出线的横向连接部对与该横向连接部相邻的子像素中的像素电路排布影响较小。因此，在扇出走线区中，在基底上的正投影与数据扇出线的竖向连接部在基底上的正投影存在交叠区域的子像素中不设置像素电路，而与数据扇出线的横向连接部相邻的子像素中可以设置像素电路。也即，第一显示区和第二显示区的各个子像素均包括半导体层图案，扇出走线区的部分子像素或所有子像素均不包括半导体层图案。在示例性实施方式中，基底可以是柔性基底。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案 可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括位于显示区域的多条数据扇出线、多条扫描信号线、多个晶体管的栅电极和多个第一电容电极，以及位于绑定区域引线区的多条引出线，数据扇出线和引出线可以是相互连接的一体结构。在示例性实施方式中，数据扇出线形成在扇出走线区，在示例性实施方式中，第一导电层可以称为第一栅电极(GATE 1)层。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层图案的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括位于显示区域的多个第二电容电极。在示例性实施例中，第二导电层可以称为第二栅电极(GATE 2)层。
(4)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层图案的第四绝缘层，第四绝缘层上开设有多个过孔，多个过孔可以包括：位于显示区域的多个有源层所在位置的有源过孔，以及位于显示区域的数据扇出线端部的多个第一过孔和第二过孔。有源过孔暴露出有源层，第一过孔暴露出数据扇出线，第二过孔暴露出引出线。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层上形成第三导电层图案，第三导电层图案至少包括：多条数据线、多个晶体管的源电极和漏电极，源电极和漏电极分别通过有源过孔与对应的有源层连接，多条数据线延伸到绑定区域引线区，一部分数据线通过第一过孔与数据扇出线连接，另一部分数据线通过第二过孔与引出线连接。在示例性实施例中，第三导电层可以称为第一源漏电极(SD1)层。
(6)形成电极连接层图案。在示例性实施方式中，形成电极连接层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和电极连接层薄膜，采用图案化工艺分别对第五绝缘薄膜和电极连接层薄膜进行图案化，形成覆盖第三导电层图案的第五绝缘层，以及设置在第五绝缘层上的电极连接层图案，第五绝缘层上开设有多个第三过孔，第三过孔内的第五绝缘层被去掉，暴露出多个晶体管的漏电极的表面。电极连接层图案至少包括多条相互绝缘的第一连接线和第二连接线，且第一连接线的一端通过第三过孔与晶体管的漏电极连接，第一连接线形成在第一显示区、第二显示区和扇出走线区，第二连接线形成在第二显示区和扇出走线区，第一连接线配置为使后续形成的第一发光元件的阳极、一部分第二发光元件的阳极和一部分第三发光元件的阳极与晶体管的漏电极连接，第二连接线配置为使后续形成的第二发光元件的阳极和第三发光元件的阳极两两之间相互连接。
(7)形成平坦层图案。在示例性实施方式中，形成平坦层图案可以包括：在形成前述图案的基底上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖电极连接层的平坦层，平坦层上设置有第四过孔和第五过孔，第四过孔暴露出第一连接线的另一端，第五过孔暴露出第二连接线的两端，第四过孔配置为使后续形成的第一发光元件的阳极、一部分第二发光元件的阳极和一部分第三发光元件的阳极通过该过孔与第一连接线的另一端连接，第五过孔配置为使后续形成的第二发光元件的阳极和第三发光元件的阳极两两之间通过该过孔与第二连接线连接。
(8)形成阳极图案。在示例性实施方式中，形成阳极图案可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在平坦层上的阳极。第一发光元件的阳极、一部分第二发光元件的阳极和一部分第三发光元件的阳极通过第四过孔与第一连接线的另一端连接，第二发光元件的阳极和第三发光元件的阳极两两之间通过第五过孔与第二连接线连接。
在示例性实施方式中，后续制备流程可以包括：涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。采用蒸镀或喷墨打印工 艺形成有机发光层，在有机发光层上形成阴极。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层，如图16所示。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。电极连接层的材料为透明导电材料，具体可以为氧化铟锡ITO或氧化铟锌IZO。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。有源层可以采用多晶硅(p-Si)，即本公开适用于LTPS薄膜晶体管。
虽然本实施例显示基板的制备过程以数据扇出线设置在第一导电层以及数据线设置在第三导电层为例进行了说明，但本公开中，数据扇出线和数据 线可以设置在任意层中，只要保证数据线与数据扇出线位于不同的导电层中即可，本公开在此不做限定。
本公开所示显示基板的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
一种显示基板中，绑定区域设置有扇出区，显示区域的数据线通过扇出区的数据扇出线引出，由于扇形区中斜向线较多，因而使得下边框较宽，不利于实现窄边框。本公开示例性实施例中，在绑定区域的引线区中设置引出线，在显示区域内设置数据扇出线，引出线通过数据扇出线与对应的数据信号线连接，不仅实现了多条引出线与多条数据信号线的对应连接，而且使得引线区中不需要设置扇形状的斜线，多条引出线为相互平行的竖直线，可以直接引入到绑定区域的复合电路区，有效减小了引线区竖直方向的长度，大大缩减了下边框宽度，使得显示装置的上边框、下边框、左边框和右边框的宽度相近，均为1.0mm以下，提高了屏占比，有利于实现全面屏显示。
本公开示例性实施例中，通过在第二显示区的子像素中设置第二像素电路，在扇出走线区的子像素中不设置像素电路，只设置第三发光元件，第二像素电路可以驱动第二发光元件，也可以驱动第三发光元件，从而可以在扇出走线区腾出足够的空间用于数据扇出线走线。
在示例性实施方式中，如图14或15所示，在扇出走线区，至少一个第三子像素可以设置以下任意一种或多种虚拟电极线102C：虚拟有源层、虚拟栅电极、虚拟电容电极、虚拟源漏电极，虚拟电极线可以通过信号走线连接至固定电位信号线。本公开示例性实施例通过在至少一个第三子像素内设置虚拟电极线，可以提高显示基板制备工艺的均匀性，进而提高制备质量。
本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域以及围绕显示区域的非显示区域，显示区域包括第一显示区、第二显示区和扇出走线区，第二显示区位于第一显示区和扇出走线区之间；所述制备方法包括：
在第一显示区形成多个第一子像素，第一子像素包括第一像素电路和第 一发光元件，第一像素电路和第一发光元件在显示基板上的正投影至少部分重叠；在第二显示区形成多个第二子像素，第二子像素包括第二像素电路和第二发光元件，第二像素电路和第二发光元件在显示基板上的正投影至少部分重叠，第一像素电路和第二像素电路与多条数据线电连接；在扇出走线区形成多个第三子像素和多条数据扇出线，第三子像素包括第三发光元件，至少一个第二像素电路与至少两个发光元件电连接，至少两个发光元件选自第二发光元件、第三发光元件中的至少一种，多条数据扇出线与多条数据线电连接。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、广告面板、手表电话、电子书便携式多媒体播放器或物联网各种产品的显示屏等任何具有显示功能的产品或部件。在示例性实施方式中，显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (18)

  1. 一种显示基板，包括显示区域以及围绕所述显示区域的非显示区域，所述显示区域包括第一显示区、第二显示区和扇出走线区，所述第二显示区位于所述第一显示区和所述扇出走线区之间；
    多条数据线，位于所述显示区域；
    所述第一显示区包括多个第一子像素，所述第一子像素包括第一像素电路和第一发光元件，所述第一像素电路和所述第一发光元件在所述显示基板上的正投影至少部分重叠；
    所述第二显示区包括多个第二子像素，所述第二子像素包括第二像素电路和第二发光元件，所述第二像素电路和所述第二发光元件在所述显示基板上的正投影至少部分重叠；
    所述第一像素电路和所述第二像素电路与所述多条数据线电连接；
    所述扇出走线区包括多条数据扇出线和多个第三子像素，所述第三子像素包括第三发光元件，至少一个所述第二像素电路与至少两个发光元件电连接，所述至少两个发光元件选自所述第二发光元件、所述第三发光元件中的至少一种，所述多条数据扇出线与所述多条数据线电连接。
  2. 根据权利要求1所述的显示基板，其中，所述第二像素电路在所述显示基板平面上的正投影和所述第三发光元件在所述显示基板平面上的正投影不重叠。
  3. 根据权利要求1所述的显示基板，其中，所述数据扇出线为阶梯状走线，所述数据扇出线在所述显示基板平面上的正投影与所述第一像素电路和所述第二像素电路在所述显示基板平面上的正投影不重叠。
  4. 根据权利要求1所述的显示基板，其中，所述显示区域包括第一连接线和第二连接线，所述第一连接线被配置为连接以下至少之一：所述第一像素电路与所述第一发光元件的阳极、所述第二像素电路与所述第二发光元件的阳极、所述第二像素电路与所述第三发光元件的阳极；所述第二连接线被配置为连接所述至少两个发光元件的阳极。
  5. 根据权利要求4所述的显示基板，其中，所述第一连接线和第二连接线的材料为透明导电材料。
  6. 根据权利要求4所述的显示基板，其中，所述扇出走线区包括第一颜色发光元件、第二颜色发光元件和第三颜色发光元件，所述第二连接线被配置为连接至少两个所述第三颜色发光元件的阳极。
  7. 根据权利要求6所述的显示基板，其中，所述第三颜色发光元件为绿色发光元件。
  8. 根据权利要求6所述的显示基板，其中，所述第三子像素还包括第三像素电路，所述第三像素电路在所述显示基板上的正投影与所述第一颜色发光元件或第二颜色发光元件在所述显示基板上的正投影至少部分重叠，且与所述第三颜色发光元件在所述显示基板上的正投影不重叠。
  9. 根据权利要求6所述的显示基板，其中，所述第二连接线还被配置为连接以下至少之一：至少两个所述第一颜色发光元件的阳极、至少两个所述第二颜色发光元件的阳极。
  10. 根据权利要求1所述的显示基板，其中，所述数据扇出线包括至少一个横向连接部和至少一个纵向连接部，所述横向连接部在所述显示基板平面上的正投影与所述第三发光元件在所述显示基板平面上的正投影不重叠，所述纵向连接部在所述显示基板平面上的正投影与所述第三发光元件在所述显示基板平面上的正投影至少存在重叠区域。
  11. 根据权利要求1所述的显示基板，其中，所述至少一个第二像素电路与至少两个发光元件电连接，包括以下任意一种或多种：
    两个所述发光元件串联连接后与一个所述第二像素电路连接，两个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种；
    三个所述发光元件串联连接后与一个所述第二像素电路连接，三个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种；
    四个所述发光元件串联连接后与一个所述第二像素电路连接，四个所述 发光元件选自所述第二发光元件、所述第三发光元件中的至少一种；
    五个所述发光元件串联连接后与一个所述第二像素电路连接，五个所述发光元件选自所述第二发光元件、所述第三发光元件中的至少一种。
  12. 根据权利要求1至11任一项所述的显示基板，其中，所述显示基板包括在基底上叠设的半导体层、第一栅电极层、第二栅电极层、第一源漏电极层、第二源漏电极层和阳极，其中：
    所述半导体层包括多个晶体管的有源层，所述第一栅电极层包括多个晶体管的栅电极和多个第一电容电极，所述第二栅电极层包括多个第二电容电极，所述第一源漏电极层包括多条数据线、多个晶体管的源电极和漏电极，所述第二源漏电极层包括连接电极；
    所述多条数据扇出线与所述第一栅电极层、第二栅电极层、第二源漏电极层中的一层或多层同层设置。
  13. 根据权利要求1至11任一项所述的显示基板，其中，所述显示基板包括在基底上叠设的遮光层、第一半导体层、第一栅电极层、第二栅电极层、第二半导体层、第三栅电极层、源漏电极层和阳极，其中：
    所述第一半导体层包括至少一个多晶硅晶体管的有源层，所述第一栅电极层包括至少一个多晶硅晶体管的栅电极和多个第一电容电极，所述第二栅电极层包括多个第二电容电极，所述第二半导体层包括至少一个氧化物晶体管的有源层，所述第三栅电极层包括至少一个氧化物晶体管的栅电极，所述源漏电极层包括多条数据线、多个晶体管的源电极和漏电极；
    所述多条数据扇出线与所述遮光层、第一栅电极层、第二栅电极层、第三栅电极层中的一层或多层同层设置。
  14. 根据权利要求12或13所述的显示基板，还包括电极连接层，所述电极连接层设置在源漏电极层和所述阳极之间，所述电极连接层的材料为氧化铟锡或氧化铟锌。
  15. 根据权利要求12或13所述的显示基板，其中，至少一个所述第三子像素包括以下任意一种或多种虚拟电极线：虚拟有源层、虚拟栅电极、虚 拟电容电极、虚拟源漏电极，所述虚拟电极线通过信号走线连接至固定电位信号线。
  16. 根据权利要求12或13所述的显示基板，其中，至少一个所述第三子像素包括虚拟数据扇出线，所述虚拟数据扇出线通过信号走线连接至固定电位信号线。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，所述显示基板包括显示区域以及围绕所述显示区域的非显示区域，所述显示区域包括第一显示区、第二显示区和扇出走线区，所述第二显示区位于所述第一显示区和所述扇出走线区之间；所述制备方法包括：
    在所述第一显示区形成多个第一子像素，所述第一子像素包括第一像素电路和第一发光元件，所述第一像素电路和所述第一发光元件在所述显示基板上的正投影至少部分重叠；在所述第二显示区形成多个第二子像素，所述第二子像素包括第二像素电路和第二发光元件，所述第二像素电路和所述第二发光元件在所述显示基板上的正投影至少部分重叠，所述第一像素电路和所述第二像素电路与所述多条数据线电连接；在所述扇出走线区形成多个第三子像素和多条数据扇出线，所述第三子像素包括第三发光元件，至少一个所述第二像素电路与至少两个发光元件电连接，所述至少两个发光元件选自所述第二发光元件、所述第三发光元件中的至少一种，所述多条数据扇出线与多条数据线电连接。
PCT/CN2021/095038 2021-05-21 2021-05-21 显示基板及其制备方法、显示装置 WO2022241747A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202180001231.2A CN115769296B (zh) 2021-05-21 2021-05-21 显示基板及其制备方法、显示装置
PCT/CN2021/095038 WO2022241747A1 (zh) 2021-05-21 2021-05-21 显示基板及其制备方法、显示装置
US17/772,151 US12238991B2 (en) 2021-05-21 2021-05-21 Display substrate comprising sub-pixels in fan-out wiring region and preparation method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/095038 WO2022241747A1 (zh) 2021-05-21 2021-05-21 显示基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2022241747A1 true WO2022241747A1 (zh) 2022-11-24

Family

ID=84141064

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/095038 WO2022241747A1 (zh) 2021-05-21 2021-05-21 显示基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US12238991B2 (zh)
CN (1) CN115769296B (zh)
WO (1) WO2022241747A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115938236A (zh) * 2022-12-12 2023-04-07 湖北长江新型显示产业创新中心有限公司 显示面板、拼接显示装置及其制备方法
WO2024046040A1 (zh) * 2022-08-29 2024-03-07 京东方科技集团股份有限公司 显示面板和显示装置
TWI871129B (zh) * 2023-12-11 2025-01-21 錼創顯示科技股份有限公司 顯示裝置及其製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951892B (zh) * 2021-02-26 2024-04-19 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
KR20230010081A (ko) * 2021-07-08 2023-01-18 삼성디스플레이 주식회사 표시 장치
JP2025501418A (ja) * 2021-12-17 2025-01-20 京東方科技集團股▲ふん▼有限公司 表示パネル及び表示装置
US12316377B2 (en) * 2022-11-30 2025-05-27 Microsoft Technology Licensing, Llc Methods for transmitting data via free space spatiotemporal patterns

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140117320A1 (en) * 2012-10-26 2014-05-01 Samsung Display Co., Ltd. Display apparatus and organic light-emitting display apparatus
CN109541865A (zh) * 2018-12-26 2019-03-29 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN110491915A (zh) * 2019-08-02 2019-11-22 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111584587A (zh) * 2020-05-20 2020-08-25 京东方科技集团股份有限公司 一种显示面板及其制备方法和拼接屏
CN111897167A (zh) * 2020-08-18 2020-11-06 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN212516405U (zh) * 2020-09-24 2021-02-09 合肥鑫晟光电科技有限公司 一种驱动背板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000152B (zh) * 2012-11-29 2015-04-22 北京京东方光电科技有限公司 控制栅极线信号值方法和设备、栅极驱动电路、显示装置
KR102483894B1 (ko) * 2016-04-05 2023-01-02 삼성디스플레이 주식회사 표시 장치
CN109449169B (zh) * 2018-12-06 2021-04-13 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN109599031B (zh) * 2018-12-13 2021-03-26 合肥鑫晟光电科技有限公司 一种显示基板及其制作方法、显示装置
US11069302B2 (en) * 2019-06-05 2021-07-20 Samsung Display Co., Ltd. Display apparatus having extended connecting lines
CN111916488A (zh) * 2020-09-11 2020-11-10 京东方科技集团股份有限公司 一种显示基板、显示装置
US20220392964A1 (en) * 2021-06-03 2022-12-08 Wuhan Tianma Microelectronics Co., Ltd. Display panel and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140117320A1 (en) * 2012-10-26 2014-05-01 Samsung Display Co., Ltd. Display apparatus and organic light-emitting display apparatus
CN109541865A (zh) * 2018-12-26 2019-03-29 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN110491915A (zh) * 2019-08-02 2019-11-22 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111584587A (zh) * 2020-05-20 2020-08-25 京东方科技集团股份有限公司 一种显示面板及其制备方法和拼接屏
CN111897167A (zh) * 2020-08-18 2020-11-06 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN212516405U (zh) * 2020-09-24 2021-02-09 合肥鑫晟光电科技有限公司 一种驱动背板及显示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024046040A1 (zh) * 2022-08-29 2024-03-07 京东方科技集团股份有限公司 显示面板和显示装置
CN115938236A (zh) * 2022-12-12 2023-04-07 湖北长江新型显示产业创新中心有限公司 显示面板、拼接显示装置及其制备方法
TWI871129B (zh) * 2023-12-11 2025-01-21 錼創顯示科技股份有限公司 顯示裝置及其製造方法

Also Published As

Publication number Publication date
CN115769296A (zh) 2023-03-07
US12238991B2 (en) 2025-02-25
US20240147785A1 (en) 2024-05-02
CN115769296B (zh) 2025-06-24

Similar Documents

Publication Publication Date Title
CN114730538B (zh) 显示基板及其制备方法、显示装置
WO2022241747A1 (zh) 显示基板及其制备方法、显示装置
WO2022160491A1 (zh) 显示基板及其制备方法、显示装置
CN115004376B (zh) 显示基板及显示装置
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2023016341A1 (zh) 显示基板及其制备方法、显示装置
WO2022227005A1 (zh) 显示基板及其制备方法、显示装置
WO2023039886A1 (zh) 显示基板及其制备方法、显示装置
US20240423051A1 (en) Display substrate and manufacturing method therefor, and display apparatus
WO2023279333A1 (zh) 显示基板及显示装置
WO2022170547A1 (zh) 显示基板及其制备方法、显示装置
CN116322168A (zh) 显示基板及其制作方法、显示装置
WO2022226815A1 (zh) 显示基板及其制备方法、显示装置
CN115424570A (zh) 像素电路及其驱动方法、显示基板和显示装置
WO2022193315A1 (zh) 触控显示基板及其制备方法、触控显示装置
US20240324333A1 (en) Display Substrate and Preparation Method therefor, and Display Apparatus
CN115394201A (zh) 显示面板和显示装置
WO2023184352A1 (zh) 显示基板及显示装置
US20240381725A1 (en) Display Substrate and Preparation Method therefor, and Display Apparatus
US20240381709A1 (en) Display Substrate, Preparation Method Therefor, and Display Apparatus
US20250081760A1 (en) Display Substrate, Manufacturing Method Therefor, and Display Apparatus
WO2023115457A1 (zh) 显示基板及其驱动方法、显示装置
WO2023051103A1 (zh) 显示基板及其制备方法、显示装置
WO2023159511A1 (zh) 显示基板及其制备方法、显示装置
CN118973311A (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17772151

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21940201

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.03.2024)

122 Ep: pct application non-entry in european phase

Ref document number: 21940201

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 17772151

Country of ref document: US