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US6768357B1 - PLL circuit which compensates for stoppage of PLL operations - Google Patents

PLL circuit which compensates for stoppage of PLL operations Download PDF

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Publication number
US6768357B1
US6768357B1 US09/806,054 US80605401A US6768357B1 US 6768357 B1 US6768357 B1 US 6768357B1 US 80605401 A US80605401 A US 80605401A US 6768357 B1 US6768357 B1 US 6768357B1
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United States
Prior art keywords
signal
frequency
voltage control
control oscillator
pll circuit
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Application number
US09/806,054
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English (en)
Inventor
Takushi Kimura
Masamichi Nakajima
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Canon Inc
Original Assignee
Fujitsu General Ltd
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Assigned to FUJITSU GENERAL LTD. reassignment FUJITSU GENERAL LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIMURA, TAKUSHI, NAKAJIMA, MASAMICHI
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Assigned to CANON INC. reassignment CANON INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU GENERAL LIMITED
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Definitions

  • the present invention relates to a PLL circuit which generates and outputs a frequency signal which has a predetermined relationship with a reference frequency signal, and in particular, to a PLL circuit which enacts countermeasures in cases in which PLL operation stops.
  • phase comparator 101 which is formed by an exclusive OR circuit or the like.
  • the signal of the results of comparison is smoothed at a loop filter 102 to become a control voltage Vc.
  • the frequency oscillated by a voltage control oscillator (VCO) 103 is controlled by this control voltage Vc, and the frequency signal fck obtained thereat is the output frequency signal.
  • This output frequency signal fck is inputted to a frequency divider 104 , and there, the frequency is made to be 1/N and the resulting signal is inputted as the comparison signal fc to the phase comparator 101 .
  • the entire circuit is operated such that, given that the frequency of the reference signal fr is fr, the frequency of the comparison signal fc is fc, and the frequency of the oscillation frequency signal fck is fck, in a synchronized state, the relational formulas
  • a PLL circuit such as that described above is used in order to generate a sampling clock.
  • the frequency of the sampling clock extends over a wide range of from 10 MHz to 100 MHz or more depending on the type of image signal.
  • the frequency dividing operation of the frequency dividing circuit 104 is not able to follow, and the output signal, i.e., the comparison signal fc, disappears.
  • the phase comparator 101 judges that the oscillation frequency of the voltage control oscillator 103 has fallen, operates such that the oscillation frequency is increased, and boosts the control voltage Vc to the maximum oscillation frequency.
  • a voltage limiting circuit 105 such as that illustrated in FIG. 8 was inserted between the voltage control oscillator 103 and the loop filter 102 , so as to provide an upper limit for the control voltage Vc.
  • the maximum value of the control voltage Vc is limited by a voltage-regulator diode ZD, and, as illustrated in FIG. 9, the oscillation frequency of the voltage control oscillator 103 is limited to fd which is sufficiently lower than the maximum value fmax.
  • the frequency fck which oscillates at the voltage control oscillator 103 , is in the range from the minimum frequency fmin to the upper limit frequency fd, and the above-described problem can be avoided.
  • an object of the present invention is to provide a PLL circuit which can easily return to normal, even if the voltage control oscillator oscillates abnormally and PLL operation stops.
  • a PLL circuit in which a phase comparator, a loop filter, a voltage control oscillator and a frequency divider are successively loop-connected, comprises: operation stoppage detecting means for detecting that PLL operation has stopped; and control means for, when said operation stoppage detecting means detects stoppage of operation, controlling the voltage control oscillator such that an oscillation frequency of the voltage control oscillator is low.
  • operation stoppage detecting means for detecting that PLL operation has stopped
  • control means for, when said operation stoppage detecting means detects stoppage of operation, controlling the voltage control oscillator such that an oscillation frequency of the voltage control oscillator is low.
  • FIG. 1 is a block diagram of a PLL circuit of a first embodiment of the present invention.
  • FIG. 2 is a block diagram of a comparison signal presence/absence detector.
  • FIG. 3 is a timing chart of operation of the comparison signal presence/absence detector.
  • FIG. 4 is a block diagram of a phase comparator.
  • FIG. 5 is an operation characteristic diagram of forced return of a voltage control oscillator at the time of abnormal oscillation.
  • FIG. 6 is a block diagram of a PLL circuit of a second embodiment of the present invention.
  • FIG. 7 is a block diagram of a conventional, general PLL circuit.
  • FIG. 8 is a circuit diagram of a voltage limiting circuit.
  • FIG. 9 is a characteristic diagram of oscillation frequency with respect to control voltage of the voltage control oscillator.
  • FIG. 1 is a block diagram of a PLL circuit of an embodiment of the present invention.
  • 1 is a phase comparator which compares phases of a reference signal fr and a comparison signal fc and outputs a signal which corresponds to the results of the comparison
  • 2 is a loop filter which smoothes the comparison signal
  • 3 is a voltage control oscillator which oscillates a signal fck of a frequency which is proportional to an inputted control voltage Vc
  • 4 is a frequency divider which frequency-divides the frequency of an inputted signal into 1/N
  • 5 is a comparison signal presence/absence detector (operation stoppage detecting means) which detects the presence/absence of the comparison signal fc.
  • the comparison signal presence/absence detector 5 is connected to the output side of the frequency divider 4 .
  • the signal outputted from the phase comparator 1 is a signal which controls the oscillation frequency fck of the voltage control oscillator 3 to a low frequency.
  • FIG. 2 is a block diagram which illustrates the internal structure of the comparison signal presence/absence detector 5 .
  • 51 , 52 are DFF circuits, and 53 , 54 are inverters.
  • a high level signal is inputted to the D terminal of the DFF circuit 51
  • a test signal ft generated independently (and having a frequency less than or equal to 1 ⁇ 2 of the comparison signal fc and a duty ratio of 50%) is inputted to the CK terminal of the DFF circuit 51 .
  • the comparison signal fc is inputted to the R (reset) terminal of the DFF circuit 51 via the inverter 54 .
  • a signal from the Q 1 terminal of the DFF circuit 51 is inputted to the D terminal of the DFF circuit 52 , and the test signal ft is inverted at the inverter 53 and inputted to the CK terminal of the DFF circuit 52 .
  • FIG. 3 is a timing chart of operation of the comparison signal presence/absence detector 5 .
  • the Q 1 terminal of the DFF circuit 51 senses a high level of the D terminal and becomes a high level.
  • the comparison signal fc rises, the Q 1 terminal of the DFF circuit 51 is reset and becomes a low level.
  • the DFF circuit 52 outputs, to the Q 2 terminal, data of the D terminal at the time the electric potential of the CK terminal rises.
  • the comparison signal fc changes from H ⁇ L ⁇ H ⁇ . . . at a predetermined period, even if the Q 1 terminal of the DFF circuit 51 becomes a high level at the rise of the test signal ft, thereafter, the Q 1 terminal of the DFF circuit 51 is reset at the rise of the comparison signal fc. Thus, thereafter, even if the test signal ft falls, the Q 2 terminal of the DFF circuit 52 does not become a high level.
  • the DFF circuit 51 when there is no comparison signal fc, in other words, when the comparison signal fc does not change to a high level, the DFF circuit 51 is not reset.
  • the DFF circuit 52 senses the high level signal of the Q 1 terminal and outputs it as a high level signal to the Q 2 terminal, and thereafter continues this operation. Note that, thereafter, when the comparison signal fc starts to change again, the Q 2 terminal of the DFF circuit 52 returns to a low level.
  • FIG. 4 is a block diagram which illustrates the internal structure of the phase comparator 1 which is controlled by the signal detected at the comparison signal presence/absence detector 5 .
  • 11 is a phase comparing portion which is formed by an exclusive OR gate or the like
  • 12 is a three state buffer
  • 13 is an OR gate
  • 14 is a switch circuit.
  • the three state buffer 12 , the OR gate 13 and the switch circuit 14 form a control means.
  • the phase comparing portion 11 makes an output terminal 11 a a low level.
  • the phase comparing portion 11 makes the output terminal 11 a a high level.
  • the level is indefinite at times other than the times of phase comparison. Moreover, when there is a phase difference between the comparison signal fc and the reference signal fr, a control terminal 11 b of the phase comparing portion 11 is a high level, and at other times, is a low level.
  • the OR gate 13 takes the logical sum of a control signal outputted from the control terminal 11 b of the phase comparing portion 11 and a detection signal Va detected at the comparison signal presence/absence detector 5 , and sends the logical sum to the control terminal of the buffer 12 . Further, a signal of the output terminal 11 a of the phase comparing portion 11 is inputted to the input side of the buffer 12 via the switch circuit 14 . Moreover, the switch circuit 14 switches to the ground side (low level) when the detection signal Va becomes a high level.
  • the buffer 12 is controlled according to the signal of the control terminal 11 b of the phase comparing portion 11 . Namely, during the time in which there is a phase offset between the comparison signal fc and the reference signal fr, the control terminal 11 b is high level. Therefore, the buffer 12 is ON such that a signal can pass between the input and the output, and the signal of the output terminal 11 a of the phase comparing portion 11 is outputted as it is via the switch circuit 14 , and normal operation is carried out.
  • the signal of the control terminal 11 b When there is no phase offset (at times of PLL lock), the signal of the control terminal 11 b is at a low level, and the output of the buffer 12 is high impedance. Due to the signal held at the loop filter 2 which is downstream of the phase comparator 1 , thereafter, the voltage control oscillator 3 oscillates a constant frequency signal.
  • the detection signal Va of the comparison signal presence/absence detector 5 is a signal-does-not-exist signal
  • the detection signal Va when the detection signal Va is high level, the output of the switch circuit 14 is low level, and the buffer 12 turns ON such that a signal can pass between the input and the output. Therefore, the low level signal outputted from the switch circuit 14 is outputted as it is. Accordingly, the low level signal is inputted to the loop filter 2 , and the control voltage Vc which is inputted to the voltage control oscillator 4 is low level, and the frequency oscillated thereat is low.
  • FIG. 5 is a diagram which illustrates an operation characteristic of the voltage control oscillator 3 .
  • fo is a target frequency of the frequency signal fck
  • fmax is an oscillation upper limit frequency
  • fmin is a oscillation lower limit frequency
  • flimit is an input frequency which is an operating limit of the frequency divider 4 .
  • the comparison signal fc disappears.
  • the output signal of the phase comparator 1 is controlled to a low level, and the oscillation frequency of the voltage control oscillator 3 is controlled to a low frequency.
  • the frequency divider 4 starts to operate again, and the PLL circuit returns to original operation, and the oscillation frequency fck settles to the target frequency fo.
  • FIG. 6 is a block diagram which illustrates the structure of a PLL circuit of another embodiment.
  • a switch circuit 6 is connected between the frequency divider 4 and the phase comparator 1 .
  • the switch circuit 6 is controlled such that the frequency divider 4 and the phase comparator 1 are connected to each other by the switch circuit 6 .
  • the switch circuit 6 is controlled so that a dummy pulse is inputted from a dummy pulse generator 7 as the comparison signal fc which is inputted to the phase comparator 1 .
  • the switch circuit 6 and the dummy pulse generator 7 form the control means.
  • the dummy pulse maybe a signal which is a higher frequency than a frequency of the frequency signal outputted from the frequency divider 4 .
  • the voltage control oscillator 3 oscillates abnormally and the operation of the frequency divider 4 stops, operation can be returned to normal immediately.
  • the output signal of the phase comparator 1 is forcibly made to be a special signal (low level signal) by the detection signal Va of the comparison signal presence/absence detector 5 , or a special dummy pulse is inputted as the comparison signal to the phase comparator 1 .
  • the above-described embodiments are not limited to the same.
  • the control voltage Vc of the voltage control oscillator 3 may be controlled directly by the detection signal Va of the comparison signal presence/absence detector 5 such that the oscillation frequency of the voltage control oscillator 3 is controlled to a specific low frequency. No special accuracy is demanded of this specific low frequency at this time.
  • the operation stoppage state of the PLL circuit is judged by the presence/absence of an output signal of the frequency divider 4 .
  • the operation stoppage state of the PLL circuit may be judged by detecting whether or not the oscillation frequency fck of the voltage control oscillator 3 is a frequency of a predetermined value or more.
  • the signal of the frequency fck may be converted into a voltage signal by a frequency/voltage converter, and this voltage signal compared with a predetermined value by a voltage comparator.
  • the present invention there is the advantage that, when an oscillation frequency of a voltage control oscillator exceeds a predetermined value and a PLL circuit stops operating, operation can return to normal quickly with a simple structure.
  • the present invention is suitable for generation of a sampling clock of a wide range which is used when digitally processing analog image signals, and for the like.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US09/806,054 1999-09-21 2000-08-23 PLL circuit which compensates for stoppage of PLL operations Expired - Lifetime US6768357B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11-267168 1999-09-21
JP26716899A JP3849368B2 (ja) 1999-09-21 1999-09-21 Ｐｌｌ回路
PCT/JP2000/005629 WO2001022593A1 (fr) 1999-09-21 2000-08-23 Boucle a phase asservie

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US (1) US6768357B1 (ja)
EP (1) EP1143622B1 (ja)
JP (1) JP3849368B2 (ja)
KR (1) KR100534196B1 (ja)
CN (1) CN1321360A (ja)
AT (1) ATE252292T1 (ja)
AU (1) AU771267B2 (ja)
CA (1) CA2351759C (ja)
DE (1) DE60005924T2 (ja)
ES (1) ES2204675T3 (ja)
RU (1) RU2235421C2 (ja)
TW (1) TW456107B (ja)
WO (1) WO2001022593A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030140286A1 (en) * 2002-01-18 2003-07-24 Kenichi Shinbo Pulse generation circuit and semiconductor tester that uses the pulse generation circuit
US20070146553A1 (en) * 2005-12-28 2007-06-28 Matsushita Electric Industrial Co., Ltd. Receiving circuit, receiving apparatus, and receiving method
US20070288817A1 (en) * 2001-04-24 2007-12-13 Toshihiro Tanaka Semiconductor integrated circuit and a method of testing the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006254122A (ja) * 2005-03-10 2006-09-21 Fujitsu Ltd Ｐｌｌ回路およびｐｌｌ回路の発振動作制御方法
KR100862509B1 (ko) 2007-03-09 2008-10-08 삼성전기주식회사 저전력용 스택 구조 위상 동기 루프
JP4667525B2 (ja) * 2007-06-22 2011-04-13 富士通セミコンダクター株式会社 Ｐｌｌ制御回路、ｐｌｌ装置及びｐｌｌ制御方法
CN109379076A (zh) * 2018-10-24 2019-02-22 佛山市秀声电子科技有限公司 一种模数结合的低频锁相环

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4037165A (en) * 1975-04-01 1977-07-19 Nippon Gakki Seizo Kabushiki Kaisha Synchronous signal generating system with phase-locked loop circuit
US4461990A (en) * 1982-10-01 1984-07-24 General Electric Company Phase control circuit for low voltage load
US4769704A (en) * 1985-06-04 1988-09-06 Matsushita Electric Industrial Co., Ltd. Synchronization signal generator
US5105273A (en) * 1989-07-12 1992-04-14 Mitsubishi Denki Kabushiki Kaisha Video intermediate frequency signal processing circuit
JPH06338786A (ja) 1993-05-31 1994-12-06 Sanyo Electric Co Ltd マイクロコンピュータ
US5589801A (en) * 1994-11-21 1996-12-31 Sony Corporation Phase comparator circuit and phase synchronization circuit
US5598396A (en) * 1995-02-15 1997-01-28 Matsushita Electric Industrial Co., Ltd. Optical disk reproducing apparatus
JPH107627A (ja) 1996-01-11 1998-01-13 Bayer Ag 場合により置換された４−アミノジフエニルアミン類の調製方法
JPH10107627A (ja) 1996-10-01 1998-04-24 Kawasaki Steel Corp Ｐｌｌ回路
JPH11122102A (ja) 1997-10-14 1999-04-30 Kawasaki Steel Corp Ｐｌｌ回路
US5982239A (en) * 1995-08-14 1999-11-09 Hitachi, Ltd. Phase locked loop circuit and a picture reproducing device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4037165A (en) * 1975-04-01 1977-07-19 Nippon Gakki Seizo Kabushiki Kaisha Synchronous signal generating system with phase-locked loop circuit
US4461990A (en) * 1982-10-01 1984-07-24 General Electric Company Phase control circuit for low voltage load
US4769704A (en) * 1985-06-04 1988-09-06 Matsushita Electric Industrial Co., Ltd. Synchronization signal generator
US5105273A (en) * 1989-07-12 1992-04-14 Mitsubishi Denki Kabushiki Kaisha Video intermediate frequency signal processing circuit
JPH06338786A (ja) 1993-05-31 1994-12-06 Sanyo Electric Co Ltd マイクロコンピュータ
US5589801A (en) * 1994-11-21 1996-12-31 Sony Corporation Phase comparator circuit and phase synchronization circuit
US5598396A (en) * 1995-02-15 1997-01-28 Matsushita Electric Industrial Co., Ltd. Optical disk reproducing apparatus
US5982239A (en) * 1995-08-14 1999-11-09 Hitachi, Ltd. Phase locked loop circuit and a picture reproducing device
JPH107627A (ja) 1996-01-11 1998-01-13 Bayer Ag 場合により置換された４−アミノジフエニルアミン類の調製方法
JPH10107627A (ja) 1996-10-01 1998-04-24 Kawasaki Steel Corp Ｐｌｌ回路
JPH11122102A (ja) 1997-10-14 1999-04-30 Kawasaki Steel Corp Ｐｌｌ回路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070288817A1 (en) * 2001-04-24 2007-12-13 Toshihiro Tanaka Semiconductor integrated circuit and a method of testing the same
US7447959B2 (en) * 2001-04-24 2008-11-04 Renesas Technology Corp. Semiconductor integrated circuit and a method of testing the same
US20030140286A1 (en) * 2002-01-18 2003-07-24 Kenichi Shinbo Pulse generation circuit and semiconductor tester that uses the pulse generation circuit
US7085982B2 (en) * 2002-01-18 2006-08-01 Hitachi, Ltd. Pulse generation circuit and semiconductor tester that uses the pulse generation circuit
US20070146553A1 (en) * 2005-12-28 2007-06-28 Matsushita Electric Industrial Co., Ltd. Receiving circuit, receiving apparatus, and receiving method

Also Published As

Publication number Publication date
CA2351759C (en) 2004-03-09
EP1143622B1 (en) 2003-10-15
DE60005924T2 (de) 2004-05-06
JP3849368B2 (ja) 2006-11-22
EP1143622A4 (en) 2002-05-15
AU771267B2 (en) 2004-03-18
EP1143622A1 (en) 2001-10-10
WO2001022593A1 (fr) 2001-03-29
DE60005924D1 (de) 2003-11-20
KR20010093790A (ko) 2001-10-29
KR100534196B1 (ko) 2005-12-08
CN1321360A (zh) 2001-11-07
AU6725700A (en) 2001-04-24
TW456107B (en) 2001-09-21
JP2001094416A (ja) 2001-04-06
RU2235421C2 (ru) 2004-08-27
ATE252292T1 (de) 2003-11-15
CA2351759A1 (en) 2001-03-29
ES2204675T3 (es) 2004-05-01

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