TWI754554B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes data lines, gate lines, pixel structures and transfer lines. Each of the pixel structures includes a thin film transistor, a pixel electrode and a bridge element. The pixel structures are arranged in pixel rows. Each of the data line has a first side and a second side opposite to each other. A source of the thin film transistor of a pixel structure of a pixel row and a source of the thin film transistor of a pixel structure of a next pixel row are electrically connected to the same data line. A drain of the thin film transistor of the pixel structure of the pixel row and a drain of the thin film transistor of the pixel structure of the next pixel row are located on the first side of the same data line. A pixel electrode of the thin film transistor of the pixel structure of the pixel row and a pixel electrode of the thin film transistor of the pixel structure of the next pixel row are respectively located on the second side and the first side of the same data line. The bridge element of the thin film transistor of the pixel structure of the pixel row crosses over the same data line and one of the transfer lines.

Description

pixel array substrate

The present invention relates to a pixel array substrate.

With the development of display technology, people's demands for display devices are no longer satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect a display device with a narrow bezel or even no bezel.

Generally speaking, a display device includes a pixel array disposed in the display area, a data driving circuit disposed below the display area, and a gate driver circuit disposed on the left, right or left and right sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, both the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is arranged on the lower side of the display area, the gate line extending in the horizontal direction can be electrically connected to the gate driving circuit arrangement through the connecting wire extending in the vertical direction. However, when the patch cable is set in the active area, the patch cable is bound to be adjacent to the data line; the coupling effect between the patch cable and the data cable will cause the data signal on the data cable to shift, thereby causing diagonal lines. The problem

The invention provides a pixel array substrate with good performance and high aperture ratio.

The pixel array substrate of the present invention includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of transfer lines. A plurality of data lines are disposed on the substrate and arranged in the first direction. A plurality of gate lines are disposed on the substrate and are arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are arranged on the substrate, wherein each pixel structure includes a thin film transistor, a pixel electrode and a bridge element, and a source electrode and a gate electrode of the thin film transistor are respectively electrically connected to a corresponding one The data line and a corresponding gate line, the pixel electrode is arranged outside the drain electrode of the thin film transistor, and the bridge element is electrically connected to the drain electrode and the pixel electrode of the thin film transistor. The plurality of transfer wires are disposed on the substrate, are arranged in the first direction, and are electrically connected to the plurality of gate wires. A plurality of pixel structures are arranged in a plurality of pixel columns. The plurality of pixel structures of each pixel row are arranged in the first direction, and the plurality of pixel rows are arranged in the second direction. Each data line has opposite first and second sides. The source electrode of the thin film transistor with the pixel structure in one pixel row and the source electrode of the thin film transistor with the pixel structure in the next pixel row are electrically connected to the same data line. The drain electrodes of the thin film transistors of the pixel structure of the pixel row and the drain electrodes of the thin film transistors of the pixel structure of the next pixel row are located on the first side of the same data line. The pixel electrodes of the pixel structure of the pixel row and the pixel electrodes of the pixel structure of the next pixel row are respectively located on the second side and the first side of the same data line. The bridging elements of the pixel structure of the pixel row span the same data line and a transfer line.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes a first insulating layer, a common electrode layer and a second insulating layer. The first insulating layer is disposed on a plurality of on multiple thin-film transistors with a pixel structure. The common electrode layer is disposed on the first insulating layer. The second insulating layer is disposed on the common electrode layer. The bridging element of the pixel structure of the pixel row is arranged on the second insulating layer, and the common electrode layer is arranged between the bridging element of the pixel structure of the pixel row and the connecting wire.

In an embodiment of the present invention, the pixel electrodes of the pixel structure of the pixel row are disposed on the second insulating layer, and the common electrode layer is disposed on the pixel electrodes of the pixel structure of the pixel row and the connection between the lines.

In an embodiment of the present invention, the bridging elements of the pixel structure of the above-mentioned pixel row are interleaved with the same data line, and the bridging elements of the pixel structure of the next pixel row are arranged outside the same data line and do not overlap the same data line. data line.

In an embodiment of the present invention, the plurality of pixel electrodes of the above-mentioned plurality of pixel structures are arranged in a plurality of pixel electrode rows, and the plurality of pixel electrodes of each pixel electrode row are arranged in the second direction, and a plurality of pixel electrode rows are arranged in the first direction; the plurality of pixel electrode rows include a first pixel electrode row and a second pixel electrode row for displaying red and blue respectively; In a plan view, the transition line is disposed between the first pixel electrode row and the second pixel electrode row.

In an embodiment of the present invention, the plurality of pixel electrodes of the above-mentioned plurality of pixel structures are arranged in a plurality of pixel electrode rows, and the plurality of pixel electrodes of each pixel electrode row are arranged in the second direction, and a plurality of pixel electrode rows are arranged in the first direction; the plurality of pixel electrode rows include a second electrode pixel row and a third electrode pixel row for displaying blue and green respectively; in the top view of the pixel array substrate , the transfer wire is arranged between the second electrode pixel row and the third pixel electrode row.

In an embodiment of the present invention, the plurality of pixel electrodes of the above-mentioned plurality of pixel structures are arranged in a plurality of pixel electrode rows, and the plurality of pixel electrodes of each pixel electrode row are arranged in the second direction, and a plurality of pixel electrode rows are arranged in the first direction; the plurality of pixel electrode rows include a first pixel electrode row and a third pixel electrode row for displaying red and green respectively; the top view of the pixel array substrate , the connecting wire is arranged between the first pixel electrode row and the third pixel electrode row.

In an embodiment of the present invention, the above-mentioned thin film transistor further includes a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source electrode and the drain electrode respectively, and the semiconductor pattern is disposed between the gate electrode and the substrate.

In an embodiment of the present invention, the above-mentioned thin film transistor further includes a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source electrode and the drain electrode respectively, and the gate electrode is disposed between the semiconductor pattern and the substrate.

100, 100A, 100B: pixel array substrate

110: Base

120: Buffer layer

130: Gate insulating layer

132, 134, 142, 144: Contact windows

140: Interlayer dielectric layer

150: first insulating layer

160: Common electrode layer

170: Second insulating layer

182: Pixel electrode

182a: Slit

184: Bridging element

190: The third insulating layer

C: pixel electrode row

Cr: first pixel electrode row

Cb: second pixel electrode row

Cg: third pixel electrode row

DL: data line

GL: gate line

gl: transfer cable

PX: pixel structure

PXA: Type 1 Pixel Structure

PXB: Type 2 Pixel Structure

R, Rn, Rn+1: pixel row

SM: Shading Pattern

T: thin film transistor

Ta: source

Tb: drain

Tc: gate

Td: Semiconductor pattern

x: first direction

y: the second direction

I-I', II-II', III-III', IV-IV': cross-section

FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention.

3 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 4 is a schematic top view of a pixel array substrate 100A according to an embodiment of the present invention.

FIG. 5 is a schematic top view of a pixel array substrate 100B according to an embodiment of the present invention.

6 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention.

7 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention picture.

FIG. 2 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention. Fig. 2 corresponds to the section line I-I' of Fig. 1 .

3 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention. Fig. 2 corresponds to line II-II' of Fig. 1 .

Referring to FIG. 1 , FIG. 2 and FIG. 3 , the pixel array substrate 100 includes a base 110 . In this embodiment, the material of the substrate 110 is, for example, glass. However, the present invention is not limited thereto, and according to other embodiments, the material of the substrate 110 may also be quartz, organic polymer, or opaque/reflective material (eg, wafer, ceramic, etc.), or other applicable materials Material.

Referring to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate 110 . Referring to FIG. 1 , a plurality of data lines DL are arranged in a first direction x, and a plurality of gate lines GL are arranged in a second direction y, wherein the first direction x and the second direction y are staggered. For example, in this embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited to this.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 , in addition, the data line DL and the gate line GL belong to different layers. For example, in this embodiment, the gate line GL can selectively belong to the first metal layer, and the data line DL can selectively belong to the second metal layer, but the invention is not limited thereto.

Based on the consideration of conductivity, in this embodiment, the data line DL and the gate line GL are made of metal materials. However, the present invention is not limited to this. According to other embodiments, the data lines DL and the gate lines GL can also use other conductive materials, such as alloys, Nitride of metal material, oxide of metal material, oxynitride of metal material, or a stacked layer of metal material and other conductive materials.

Referring to FIG. 1 , the pixel array substrate 100 further includes a plurality of pixel structures PX disposed on the substrate 110 . A plurality of pixel structures PX can be arranged into a plurality of pixel rows R. The plurality of pixel structures PX of each pixel row R are arranged in the first direction x, and the plurality of pixel rows R are arranged in the second direction y.

Referring to FIG. 1 , each pixel structure PX includes a thin film transistor T, a pixel electrode 182 and a bridge element 184 . 1 and 2, the thin film transistor T includes a source electrode Ta, a drain electrode Tb, a gate electrode Tc, a semiconductor pattern Td and a gate insulating layer 130, and the gate insulating layer 130 is disposed between the gate electrode Tc and the semiconductor pattern Td, Different two regions of the semiconductor pattern Td are respectively electrically connected to the source electrode Ta and the drain electrode Tb, and the source electrode Ta and the gate electrode Tc are respectively electrically connected to a corresponding data line DL and a corresponding gate line GL. Referring to FIG. 2 , in this embodiment, the thin film transistor T may optionally include an interlayer dielectric layer 140 , wherein the interlayer dielectric layer 140 is disposed on the gate insulating layer 130 and covers the gate electrode Tc, the source electrode Ta and the The drain electrode Tb can be electrically connected to two different regions of the semiconductor pattern Td through the plurality of contact windows 142 of the interlayer dielectric layer 140 and the plurality of contact windows 132 of the gate insulating layer 130 . Referring to FIG. 1 , the pixel electrode 182 is disposed outside the drain electrode Tb of the thin film transistor T, and the bridge element 184 is electrically connected to the drain electrode Tb of the thin film transistor T and the pixel electrode 182 .

Referring to FIG. 2 , in this embodiment, the semiconductor pattern Td of the thin film transistor T can be selectively disposed between the gate electrode Tc and the substrate 110 . In other words, the thin film transistor T of this embodiment can be a top gate thin film transistor (top gate TFT), but The present invention is not limited to this.

In this embodiment, the gate electrode Tc can selectively belong to the first metal layer, and the source electrode Ta and the drain electrode Tb can selectively belong to the second metal layer, but the invention is not limited to this. In this embodiment, the material of the semiconductor pattern Td is, for example, low temperature polysilicon (LTPS). However, the present invention is not limited to this. In other embodiments, the material of the semiconductor pattern Td can also be amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (for example: indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination of the above), or other suitable materials.

Referring to FIGS. 1 and 2 , in this embodiment, the pixel array substrate 100 may optionally include a light-shielding pattern SM and a buffer layer 120 . The light-shielding pattern SM is disposed on the substrate 110 , and the buffer layer 120 covers the light-shielding pattern SM. The semiconductor pattern Td of the thin film transistor T can be selectively disposed on the buffer layer 120 and overlapped with the light shielding pattern SM, but the invention is not limited thereto.

Referring to FIG. 2 , in this embodiment, the pixel array substrate 100 further includes a first insulating layer 150 , a common electrode layer 160 and a second insulating layer 170 . 1 and 2, the first insulating layer 150 is disposed on the plurality of thin film transistors T of the plurality of pixel structures PX, the common electrode layer 160 is disposed on the first insulating layer 150, and the second insulating layer 170 is disposed on the On the common electrode layer 160 , the pixel electrode 182 of each pixel structure PX can be disposed on the second insulating layer 170 and has a plurality of slits 182 a , and the plurality of slits 182 a overlap the common electrode layer 160 .

For example, in this embodiment, the common electrode layer 160 may belong to the first transparent conductive layer, which includes metal oxides, such as indium tin oxide, indium zinc oxide compound, aluminum-tin oxide, aluminum-zinc oxide, indium-germanium-zinc oxide, other suitable oxides, or a stacked layer of at least the above two, but the invention is not limited to this; the pixel electrode 182 may belong to the first Two transparent conductive layers, which include metal oxides, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or at least two of the above However, the present invention is not limited to this. In addition, in this embodiment, the bridge element 184 and the pixel electrode 182 may belong to the same film layer and be directly connected, but the invention is not limited to this.

Referring to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of switching wires gl, which are disposed on the substrate 110 . Referring to FIG. 1 , a plurality of transition lines gl are arranged in a first direction x and are electrically connected to a plurality of gate lines GL arranged in a second direction y.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 . For example, in this embodiment, a plurality of gate lines GL can selectively belong to the first metal layer, and a plurality of transition lines gl can selectively belong to the second metal layer. Metal layer, an interlayer dielectric layer 140 is arranged between the first metal layer and the second metal layer, the interlayer dielectric layer 140 has a plurality of contact windows 144 (marked in FIG. 1 ), and a plurality of wirings gl can pass through the interlayer dielectric The plurality of contact windows 144 of the electrical layer 140 are electrically connected to the plurality of gate lines GL, but the invention is not limited thereto.

Please refer to FIG. 1 , each data line DL has an opposite first side (eg, right side) and a second side (eg, left side), and a source electrode of a thin film transistor T of a pixel structure PX of a pixel row Rn Ta and the source Ta of the thin film transistor T of the pixel structure PX in the next pixel row Rn+1 are electrically connected to the same data line DL, and the drain of the thin film transistor T of the pixel structure PX of the pixel row Rn is electrically connected to the same data line DL. The electrode Tb and the drain electrode Tb of the thin film transistor T of the pixel structure PX of the next pixel row Rn are located at the first position of the same data line DL. On the side (for example: right side), the pixel electrode 182 of the pixel structure PX of the pixel row Rn and the pixel electrode 182 of the pixel structure PX of the next pixel row Rn+1 are respectively located on the second side of the same data line DL (eg: left side) and first side (eg: right side), and the bridge element 184 of the pixel structure PX of the pixel row Rn spans the same data line DL and a transition line gl. In short, in this embodiment, the plurality of pixel electrodes 182 of the plurality of pixel structures PX electrically connected to the same data line DL are substantially arranged in a zigzag shape. Thereby, the aperture ratio of the pixel array substrate 100 can be improved.

1 and FIG. 3, in this embodiment, the bridge element 184 of the pixel structure PX of the pixel row Rn is disposed on the second insulating layer 170, and the common electrode layer 160 is disposed on the pixel of the pixel row Rn Between the bridge element 184 of the structure PX and the patch line gl. The common electrode layer 160 can be used as a shielding layer to reduce the coupling effect between the patch cord gl and the bridging element 184 and prevent the gate drive signal of the patch cord gl from excessively affecting the pixel electrode electrically connected to the bridge element 184 182 potential. In this way, the pixel array substrate 100 not only has a high aperture ratio, but also can improve the problem of diagonal stripes.

In this embodiment, the pixel electrodes 182 of the pixel structure PX of the pixel row Rn are disposed on the second insulating layer 170 , and the common electrode layer 160 is disposed on the pixel electrodes 182 of the pixel structure PX of the pixel row Rn and the patch cord gl. In other words, the common electrode layer 160 may be a shielding layer between the pixel electrode 182 and the patch cord gl, so as to reduce the influence of the gate driving signal of the patch cord gl on the potential of the pixel electrode 182 .

Referring to FIG. 1 , in this embodiment, the bridging elements 184 of the pixel structure PX of the pixel row Rn are interlaced with the data lines DL, and the bridging elements 184 of the pixel structure PX of the next pixel row Rn+1 are arranged on the data line DL. The line DL is outside and does not overlap the data line DL. Change In other words, in this embodiment, the plurality of pixel structures PX can be divided into a plurality of first-type pixel structures PXA and a plurality of second-type pixel structures PXB, wherein each first-type pixel structure PXA bridges The element 184 crosses the data line DL, and the bridge element 184 of each second-type pixel structure PXB does not cross the data line DL. For example, in this embodiment, the pixel structure PX of the odd-numbered pixel rows R (eg, Rn) can be the first-type pixel structure PXA, and the even-numbered pixel rows R (eg, Rn+1) The pixel structure PX can be the second type pixel structure PXB. In other words, the first-type pixel structures PXA and the second-type pixel structures PXB are alternately arranged in the second direction y.

Referring to FIG. 1 , in this embodiment, a plurality of pixel electrodes 182 of a plurality of pixel structures PX are arranged in a plurality of pixel electrode rows C, and the plurality of pixel electrodes 182 of each pixel electrode row C are in the first Arranged in two directions y, and a plurality of pixel electrode rows C are arranged in the first direction x, and the plurality of pixel electrode rows C include first pixel electrode rows Cr, The second pixel electrode row Cb and the third pixel electrode row Cg. In this embodiment, in the top view of the pixel array substrate 100 , the transition wires gl can be selectively disposed on the first pixel electrode row Cr and the second pixel electrode row Cb for displaying red and blue respectively. between, but the present invention is not limited to this.

It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 4 is a schematic top view of a pixel array substrate 100A according to an embodiment of the present invention.

The pixel array substrate 100A of FIG. 4 is similar to the pixel array substrate 100 of FIG. 1 , and the difference between the two is that the arrangement positions of the transition wires gl are different.

Please refer to FIG. 4 . Specifically, in the present embodiment, in the top view of the pixel array substrate 100A, the plurality of transition wires gl are disposed on the first pixel electrode row Cr and the first pixel electrode row Cr for displaying red and blue. Besides between the second pixel electrode row Cb, it is further disposed between the second pixel electrode row Cb and the third pixel electrode row Cg for displaying blue and green, and the first picture for displaying red and green between the pixel electrode row Cr and the third pixel electrode row Cg.

FIG. 5 is a schematic top view of a pixel array substrate 100B according to an embodiment of the present invention.

6 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention. Fig. 6 corresponds to line III-III' of Fig. 5 .

7 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention. Fig. 7 corresponds to line IV-IV' of Fig. 5 .

The pixel array substrate 100B of FIGS. 5 , 6 and 7 is similar to the pixel array substrate 100 of FIGS. 1 , 2 and 3 , and the difference between the two is that the thin film transistors T of the two are different.

Please refer to FIGS. 5 , 6 and 7 . Specifically, in this embodiment, the gate electrode Tc of the thin film transistor T is disposed between the semiconductor pattern Td of the thin film transistor T and the substrate 110 . In other words, the thin film transistor T of this embodiment may be a bottom gate type thin film transistor (bottom gate TFT). In addition, in this embodiment, the material of the semiconductor pattern Td of the thin film transistor T is, for example, amorphous silicon.

In addition, in this embodiment, the pixel array substrate 100B may not include the light shielding pattern SM, the buffer layer 120 and the interlayer dielectric layer 140 of the pixel array substrate 100 . In this embodiment, the pixel array substrate 100B includes a third insulating layer 190 (drawn in FIG. 6 and FIG. 7 ), which is disposed between the second metal layer and the first insulating layer 150 to which the patch lines gl and the data lines DL belong. between. In addition, in this embodiment, the transition line gl of the pixel array substrate 100B is electrically connected to the gate line GL through the contact window 134 (shown in FIG. 5 and FIG. 7 ) of the gate insulating layer 130 .

The pixel array substrate 100B has similar functions and advantages as the aforementioned pixel array substrate 100, and will not be repeated here.

100: pixel array substrate

144: Contact window

182: Pixel electrode

182a: Slit

184: Bridging element

C: pixel electrode row

Cr: first pixel electrode row

Cb: second pixel electrode row

Cg: third pixel electrode row

DL: data line

GL: gate line

gl: transfer cable

PX: pixel structure

PXA: Type 1 Pixel Structure

PXB: Type 2 Pixel Structure

R, Rn, Rn+1: pixel row

SM: Shading Pattern

T: thin film transistor

Ta: source

Tb: drain

Tc: gate

Td: Semiconductor pattern

x: first direction

y: the second direction

I-I', II-II': section line

Claims (9)

A pixel array substrate, comprising: a base; a plurality of data lines arranged on the base and arranged in a first direction; a plurality of gate lines arranged on the base and arranged in a second direction arrangement, wherein the first direction and the second direction are interlaced; a plurality of pixel structures are arranged on the substrate, wherein each pixel structure includes a thin film transistor, a pixel electrode and a bridge element, the thin film A source electrode and a gate electrode of the transistor are electrically connected to a corresponding data line and a corresponding gate line respectively, the pixel electrode is arranged outside the drain electrode of the thin film transistor, and the bridge element a drain electrode of the thin film transistor is electrically connected to the pixel electrode; and a plurality of transfer wires are disposed on the substrate, arranged in the first direction, and electrically connected to the gate lines; the The pixel structures are arranged in a plurality of pixel rows, the pixel structures of each pixel row are arranged in the first direction, and the pixel rows are arranged in the second direction; each of the data The line has a first side and a second side opposite; the source of the thin film transistor of the pixel structure of one of the pixel rows and the thin film of the pixel structure of the next pixel row the source electrode of the transistor is electrically connected to the same data line; the drain electrode of the thin film transistor of the pixel structure of one of the pixel rows and the pixel structure of the next pixel row The drain of the thin film transistor is located on the first side of the same data line; The pixel electrode of the pixel structure of the pixel row and the pixel electrode of the pixel structure of the next pixel row are respectively located on the second side and the first side of the same data line; the picture The bridging element of the pixel structure of the pixel row spans the same data line and one of the switching lines. The pixel array substrate of claim 1, further comprising: a first insulating layer disposed on the plurality of thin film transistors of the pixel structures; a common electrode layer disposed on the first insulating layer; and a second insulating layer disposed on the common electrode layer, wherein the bridging element of the pixel structure of the pixel row is disposed on the second insulating layer, and the common electrode layer is disposed on the pixel row between the bridge element of the pixel structure and the patch line. The pixel array substrate of claim 2, wherein the pixel electrode of the pixel structure of the pixel row is disposed on the second insulating layer, and the common electrode layer is disposed on the picture of the pixel row between the pixel electrode of the pixel structure and the patch cord. The pixel array substrate of claim 1, wherein the bridging element of the pixel structure of the pixel row is interlaced with the same data line, and the bridging element of the pixel structure of the next pixel row is disposed at Outside the same data line and not overlapping the same data line. The pixel array substrate of claim 1, wherein a plurality of pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, and a plurality of pixel electrodes of each pixel electrode row are in the second arranged in the first direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows include a first one for displaying red and blue respectively a pixel electrode row and a second pixel electrode row; in the top view of the pixel array substrate, the connecting wire is arranged between the first pixel electrode row and the second pixel electrode row. The pixel array substrate of claim 1, wherein a plurality of pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, and a plurality of pixel electrodes of each pixel electrode row are in the second are arranged in the direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows include a second electrode pixel row and a third electrode pixel row for displaying blue and green respectively; in In a plan view of the pixel array substrate, the connecting wire is disposed between the second electrode pixel row and the third pixel electrode row. The pixel array substrate of claim 1, wherein a plurality of pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, and a plurality of pixel electrodes of each pixel electrode row are in the second arranged in the direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows include a first pixel electrode row and a third pixel electrode row for displaying red and green respectively; In a top view of the pixel array substrate, the connecting wire is disposed between the first pixel electrode row and the third pixel electrode row. The pixel array substrate of claim 1, wherein the thin film transistor further comprises a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source electrode and the drain electrode respectively, and the semiconductor pattern is disposed on the between the gate and the substrate. The pixel array substrate of claim 1, wherein the thin film transistor further comprises a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source electrode and the drain electrode respectively, and the gate electrode is disposed on the between the semiconductor pattern and the substrate.

Images