CN105988255B - Display panel - Google Patents

Abstract

The present invention relates to a display panel, which includes a first substrate, which includes: a base substrate; a semiconductor layer, which is located on the base substrate; a first insulating layer, which is located on the semiconductor layer; a first scanning line and a second scanning line, which are located on the first insulating layer and extend respectively along a first direction, and parts of the first and second scanning lines overlap with the semiconductor layer; a second insulating layer, which is located on the first scanning line, the second scanning line and the first insulating layer; a data line, which is located on the second insulating layer and extends along a second direction, and the data line is electrically connected to the semiconductor layer through a first contact hole, wherein the second direction is different from the first direction; and a first metal pad and a second metal pad, which are located on the second insulating layer, and the first and second metal pads are electrically connected to the semiconductor layer through two second contact holes respectively; wherein the first contact hole and the two second contact holes are located between the first and second scanning lines.

Description

display panel

technical field

The present invention relates to a display panel, in particular to a display panel which can improve the aperture ratio by adjusting the wiring position and structure of the array substrate.

Background technique

Generally speaking, a liquid crystal display panel is composed of an array substrate including active elements such as thin film transistors, a color filter substrate including elements such as color filters, and a liquid crystal sandwiched therein. In the wiring area and the transistor area, the display panel usually includes a black matrix to prevent color mixing, improve the contrast ratio, and prevent the transistor from causing uneven alignment of the alignment film. With the increasing demand for high-resolution liquid crystal displays, reducing the black matrix to improve the aperture ratio of the liquid crystal display has become an important issue in the development of this technical field.

However, based on the design of the known transistors and wirings, the effect of reducing the black matrix to improve the aperture ratio of the display is limited while maintaining the premise of avoiding color mixing and maintaining the contrast ratio. Therefore, it is necessary to develop a liquid crystal display having a high aperture ratio and having the above-mentioned black matrix function by adjusting the wiring position and structure of the array substrate.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to provide a display panel so that the aperture ratio of the display panel can be improved by adjusting the wiring position and structure of the array substrate.

In order to achieve the above object, the present invention provides a display panel, which includes a first substrate, a display layer and a second substrate, wherein the display layer is located between the first substrate and the second substrate, and the first substrate is located between the first substrate and the second substrate. A substrate includes: a base substrate; a semiconductor layer on the base substrate; a first insulating layer on the semiconductor layer; a first scan line and a second scan line on the first insulating layer, and respectively extend along a first direction, and a part of the first and second scan lines overlap with the semiconductor layer; a second insulating layer is located on the first scan line, the second scan line and the first insulating layer upper; a data line located on the second insulating layer and extending along a second direction, the data line is electrically connected to the semiconductor layer through a first contact hole, wherein the second direction is different from the first direction; and a first metal pad and a second metal pad are located on the second insulating layer, the first metal pad and the second metal pad are respectively electrically connected to the semiconductor layer through two second contact holes; wherein , the first contact hole and the two second contact holes are located between the first scan line and the second scan line.

In one embodiment, the display panel may further include: a third insulating layer on the first metal pad, the second metal pad and the second insulating layer; a first pixel electrode layer on the first metal pad On the three insulating layers, the first pixel electrode layer is electrically connected to the first metal pad through a third contact hole; and a second pixel electrode layer is located on the third insulating layer, and the second pixel electrode layer passes through Another third contact hole is electrically connected to the second metal pad.

In one embodiment, the first pixel electrode layer and the second pixel electrode layer may be adjacent to the same side of the data line.

In one embodiment, the first pixel electrode layer and the second pixel electrode layer may be adjacent to different sides of the data line, and the first scan line includes a first inner edge and a first outer edge, The second scan line includes a second inner edge and a second outer edge, wherein the first inner edge is adjacent to the second inner edge.

In one embodiment, the first pixel electrode layer may overlap the first inner edge and the first outer edge of the first scan line, and the second pixel electrode layer may overlap the second scan line. The second inner edge and the second outer edge.

In one embodiment, the first pixel electrode layer and the second pixel electrode layer may be located between the first outer edge of the first scan line and the second outer edge of the second scan line.

In one embodiment, the display panel may further include a plurality of light shielding layers located between the base substrate and the semiconductor layer, and the positions of the light shielding layers respectively correspond to the overlapping regions of the first scan line and the semiconductor layer. , and the area where the second scan line overlaps the semiconductor layer.

In one embodiment, the display panel may further include a buffer layer located between the base substrate and the semiconductor layer, and the light shielding layer is located between the base substrate and the buffer layer.

In one embodiment, the display panel may further include a first black matrix layer and a second black matrix layer located between the first substrate and the second substrate, the first black matrix layer covering at least the first black matrix layer. A scan line or the second scan line, and the second black matrix layer at least covers the data line.

In one embodiment, the width of the first black matrix layer is between 5 μm and 50 μm.

In one embodiment, the second substrate can be a color filter substrate, and the second substrate includes at least four pixel groups of different colors, wherein each pixel group includes four adjacent pixel groups of the same color. The first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit, wherein the first black matrix layer or the second black matrix layer is located between pixel groups of different colors.

In one embodiment, the second substrate can be a color filter substrate, the second substrate includes at least three rows of pixel groups with different colors, and each pixel group includes a plurality of pixel groups that are arranged along the second direction and are the same. A pixel unit of a color, wherein, in the pixel group, the first black matrix layer is located between two adjacent pixel units and two other adjacent pixel units.

In one embodiment, the display panel may further include a first black matrix layer and a second black matrix layer located between the first substrate and the second substrate, the first black matrix layer covering at least the first black matrix layer. A scan line or the second scan line, and the second black matrix layer covers at least a part of the data line.

In one embodiment, the second substrate can be a color filter substrate, the second substrate includes at least three pixel groups of different colors, and each pixel group includes two adjacent ones in the first direction. And pixel units of the same color, wherein the first black matrix layer or the second black matrix layer is located between pixel groups of different colors.

Description of drawings

In order to further illustrate the technical content of the present invention, the following detailed description is as follows in conjunction with the embodiments and the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a display panel according to Embodiment 1 of the present invention.

FIG. 2 is a schematic diagram of the circuit configuration of the first substrate according to Embodiment 1 of the present invention.

FIG. 3 is a schematic diagram of the circuit structure of the first substrate according to Embodiment 1 of the present invention.

FIG. 4 is a schematic top view of the first substrate according to Embodiment 1 of the present invention.

Fig. 5 is a schematic cross-sectional view of the first substrate unfolded along the A-A' cutting line of Fig. 4 .

FIG. 6A is a schematic diagram of the second substrate of Embodiment 1 of the present invention.

FIG. 6B is a schematic diagram of the second substrate of Embodiment 2 of the present invention.

FIG. 7 is a schematic diagram of the circuit configuration of the first substrate according to Embodiment 3 of the present invention.

FIG. 8 is a schematic diagram of the circuit structure of the first substrate according to Embodiment 3 of the present invention.

FIG. 9 is a schematic plan view of the first substrate according to Embodiment 3 of the present invention.

FIG. 10 is a schematic diagram of the second substrate of Embodiment 3 of the present invention.

FIG. 11 is a schematic diagram of the circuit structure of the first substrate according to Embodiment 4 of the present invention.

FIG. 12 is a schematic plan view of the first substrate according to Embodiment 4 of the present invention.

FIG. 13A is a schematic diagram of a known pixel polarity.

FIG. 13B is a schematic diagram of the pixel polarity of the first substrate according to Embodiment 4 of the present invention.

FIG. 14 is a schematic diagram of a first substrate and a second substrate overlapping each other according to Embodiment 4 of the present invention.

Detailed ways

With the increasing demand for high-resolution liquid crystal displays, reducing the black matrix to improve the aperture ratio of the liquid crystal display has become an important issue in the development of this technical field. Therefore, in order to improve the above-mentioned problems, the present invention achieves the purpose of improving the aperture ratio of the display panel by adjusting the wiring position and structure of the array substrate.

In the present invention, as long as the above-mentioned purpose of the present invention can be achieved, the present invention does not particularly limit the materials used for each element of the array substrate, and any materials known in the art can be used. For example, in one embodiment of the present invention, the base substrate can be a transparent substrate, such as a transparent plastic substrate or a glass substrate; the buffer layer can be composed of silicon nitride, silicon oxide or a combination thereof; the semiconductor layer Can be composed of amorphous silicon, low temperature polysilicon, or metal oxide; the second insulating layer (or can be called passivation layer) can be silicon nitride, silicon oxide or a combination thereof; the first insulating layer material can be silicon oxide , silicon nitride, silicon oxynitride or hafnium oxynitride; the first scan line, the second scan line (or can be called a gate layer), the first metal pad and the second metal pad (or The third insulating layer can be made of perfluoroalkoxy polymer resin (PFA), fluoroelastomer (fluoroelastomer), etc. Lastomers) and other materials; and the first pixel electrode and the second pixel electrode can be composed of transparent conductive oxides, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide and the like.

The following are specific examples to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. In addition, the present invention can also be implemented or applied through other different specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention.

Example 1

Please refer to FIG. 1 , which is a schematic diagram of a display panel 100 according to Embodiment 1, wherein the display panel 100 includes a first substrate 10 , a display layer 5 and a second substrate 20 , wherein the display layer 5 is located in the first substrate 10 . Between a substrate 10 and the second substrate 20, and the first substrate 10 and the second substrate 20 are respectively an array substrate and a color filter substrate, the display layer 5 can be a liquid crystal layer.

Please refer to FIG. 2 , which is a schematic diagram of the circuit configuration of the first substrate 10 of the first embodiment. As shown in FIG. 2 , in the first embodiment, the opaque elements (such as the first scan line 105 , the second scan line 105 ′, and the thin film) of adjacent pixels are adjusted by adjusting the circuit arrangement on the first substrate 10 . The transistor elements T) are centrally arranged. Further, please refer to FIG. 3 , which is a schematic diagram of the circuit structure of the first substrate 10 of the first embodiment, wherein FIG. 3 only shows the semiconductor layer 103 , the first scan line 105 , the second scan line 105 ′, and the data line 107 The relative positional relationship between the first contact hole 108 , the second contact hole 111 , the first pixel electrode layer 113 , and the second pixel electrode layer 115 that are electrically connected (or can be referred to as the drain layer) is more The technical features of the present invention are clearly presented. In FIG. 3 , the data line 107 is electrically connected to the semiconductor layer 103 through a first contact hole 108 . The semiconductor layer 103 is electrically connected to the first pixel electrode layer 113 and the second pixel electrode layer 115 through two second contact holes 111 and two third contact holes 114, 114' (shown in FIG. 5).

The first contact hole 108 and the two second contact holes 111 are located between a first scan line 105 and a second scan line 105'. The first pixel electrode layer 113 and the second pixel electrode layer 115 are located on different sides of the data line 107, and the first scan line 105 includes a first inner edge 1051 and a first outer edge 1052. The second scan line 105 includes a first inner edge 1051 and a first outer edge 1052. The line 105' includes a second inner edge 1051' and a second outer edge 1052', wherein the first inner edge 1051 is adjacent to the second inner edge 1051', and the first pixel electrode layer 113 overlaps the first The first inner edge 1051 and the first outer edge 1052 of the scan line 105, and the second pixel electrode layer 115 overlaps the second inner edge 1051' and the second outer edge 1052' of the second scan line 105'.

Please refer to FIG. 4 and FIG. 5 together, which are schematic top views of the first substrate 10 according to Embodiment 1 (corresponding to the position of the dotted frame in FIG. 3 ) and the first substrate unfolded along the AA' cutting line in FIG. 4 , respectively. A schematic cross-sectional view of the substrate 10 , in which, in order to more clearly present the technical features of the present invention, some components (such as pixel electrodes and third insulating layers, etc.) shown in FIG. 5 are omitted from FIG. 4 . Therefore, as shown in FIGS. 4 and 5 , the first substrate 10 of the first embodiment includes: a base substrate 101 ; a buffer layer 102 located on the base substrate 101 ; a semiconductor layer 103 located on the buffer layer 102 a first insulating layer 104 on the buffer layer 102 and the semiconductor layer 103; a first scan line 105 and a second scan line 105' on the first insulating layer 104 and along a first It extends in one direction (X direction in FIG. 4 ), and a part of the first scan line 105 and the second scan line 105 ′ overlap with the semiconductor layer 103 ; a second insulating layer 106 is located on the first scan line 105 , On the second scan line 105 ′ and the first insulating layer 104 ; a data line 107 is located on the second insulating layer 106 and extends along a second direction (Y direction in FIG. 4 ), the data line 107 The semiconductor layer 103 is electrically connected through a first contact hole 108, wherein the second direction is different from the first direction; and a first metal pad 109 and a second metal pad 110 are located in the second insulating layer 106, the first metal pad 109 and the second metal pad 110 are respectively electrically connected to the semiconductor layer 103 through two second contact holes 111; wherein, as shown in FIG. 4, the first contact hole 108 and the two The second contact hole 111 is located between the first scan line 105 and the second scan line 105'.

Please continue to refer to FIG. 4 and FIG. 5 , the first substrate 10 further includes: a third insulating layer 112 located on the first metal pad 109 , the second metal pad 110 and the second insulating layer 106 ; a first The pixel electrode layer 113 is located on the third insulating layer 112, and the first pixel electrode layer 113 is electrically connected to the first metal pad 109 through a third contact hole 114; a second pixel electrode layer 115 is located on the third contact hole 114. On the three insulating layers 112 , the second pixel electrode layer 115 is electrically connected to the second metal pad 110 through another third contact hole 114 ′; and a plurality of light shielding layers 116 are located on the base substrate 101 and the semiconductor layer 103 In between, the position of the light shielding layer 116 corresponds to the area where the first scan line 105 overlaps with the semiconductor layer 103 and the area where the second scan line 105 ′ overlaps with the semiconductor layer 103 .

In addition, in the present embodiment 1, the semiconductor layer 103 may be composed of a low temperature polysilicon material, and it includes a source/electrode doped with a suitable dopant (eg, nitrogen or phosphorus) or formed by doping with a metal such as aluminum. The drain region 103A and a line region 103B and an undoped channel region 103C disposed therebetween.

Please continue to refer to FIG. 6A , since the first embodiment 1 adjusts the wiring position and structure of the first substrate 10 , the active elements serving as sub-pixel switches are centrally arranged, and the second substrate 20 serving as the color filter substrate The width of the black matrix layer corresponding to the first substrate 10 with the opaque active elements can be appropriately increased and the width of the black matrix layer corresponding to the first substrate 10 without the opaque active elements can be reduced to achieve The efficiency of reducing the proportion of the overall black matrix layer and increasing the aperture ratio of the display panel. Therefore, please refer to FIG. 1 and FIG. 6A together, the display panel 100 further includes a first black matrix layer II' and a second black matrix layer II-II' located on the second substrate 20, the The position of the first black matrix layer II' corresponds to at least the first scan line 105 and the second scan line 105' in FIG. 4 and the first black matrix layer II' is an extension along the X direction The strip-shaped shield has a width sufficient to cover both the first scan line 105 and the second scan line 105 ′, and the position of the second black matrix layer II-II′ corresponds to at least the data line 107 in FIG. 4 . In Embodiment 1, the width of the first black matrix layer I-I' is about 5-50 μm, and the width of the second black matrix layer II-II’ is about 2-20 μm. In addition, as shown in FIG. 6A , the display panel further includes a third black matrix layer III-III' with a width of about 2-20 μm, which is parallel to the first black matrix layer to avoid different colors on the second substrate Color mixing occurs between adjacent pixel units.

Therefore, as shown in FIG. 1 , FIGS. 2 to 5 and FIG. 6A , by adjusting the wiring position and structure of the first substrate 10 serving as the array substrate, the display substrate 100 of the present embodiment 1 can reduce the amount of the black matrix layer. proportion to increase the aperture ratio of the display panel.

Example 2

Embodiment 2 is substantially similar to Embodiment 1, and the only difference is that the pixel units of the color filters included in the second substrate 20' serving as the color filter substrate of Embodiment 2 are different. Referring to FIG. 6B , in the second embodiment, the second substrate 20 ′ includes at least four pixel groups 201 of different colors, wherein each pixel group 201 includes four adjacent first pixel units of the same color 201A, the second pixel unit 201B, the third pixel unit 201C, and the fourth pixel unit 201D, wherein the first black matrix layer II' or the second black matrix layer II-II' is located in pixel groups of different colors between. Since adjacent pixel units (such as 201A, 201B, 201C or 201D) are of the same color, it is not necessary to avoid color mixing, so it is not necessary to set a black matrix layer between adjacent pixel units of the same color (as shown by the dotted line) , further reducing the proportion of the black matrix layer, thereby further improving the aperture ratio of the display panel. In addition to the pixel groups included in the second substrate 40 of the second embodiment, the pixel groups of four colors of red, green, blue and white can be adjusted to other four colors of pixels according to requirements by those with ordinary knowledge in the art. group, the present invention is not particularly limited to this.

Other structures and configurations that are the same as those in Embodiment 1 will not be repeated in Embodiment 2.

Example 3

The difference between Example 3 and Example 1 is that the circuit arrangement of the first substrate as the array substrate and the arrangement of the pixel units of the second substrate as the color filter substrate are different.

Please refer to FIG. 7 , which is a schematic diagram of the circuit configuration of the first substrate 30 according to the third embodiment. As shown in FIG. 7 , the third embodiment also adjusts the circuit arrangement on the first substrate 30 to separate the opaque elements of adjacent pixels (such as the first scan line 305 , the second scan line 305 ′ and the thin film transistors). Element T) is set centrally. Further, please refer to FIG. 8 , which is a schematic diagram of a circuit structure of the first substrate 30 of the third embodiment. Similar to Embodiment 1, FIG. 8 only shows the semiconductor layer 303 , the first scan line 305 , the second scan line 305 ′, the data line 307 , the first contact hole 308 , the second contact hole 311 , the first pixel electrode layer 313 and the The relative positional relationship of elements such as the second pixel electrode layer 315 is to more clearly present the technical features of the present invention. The third embodiment is similar to the first embodiment, in that a data line 307 is electrically connected to the semiconductor layer 303 through a first contact hole 308, the difference is that the first pixel electrode layer 313 and the second pixel electrode layer 315 are located in the Same side of data line 307. The first contact hole 308 and the two second contact holes 311 are also located between a first scan line 305 and a second scan line 305'. As for the structures and configurations of other elements that are substantially similar to those in Embodiment 1, detailed descriptions will not be given here.

Please also refer to FIG. 9 , which is a schematic top view of the first substrate 30 according to Embodiment 3 (corresponding to the position of the dotted line frame in FIG. 8 ), wherein some elements (such as the pixel electrode and the third insulating layer, etc.) are omitted in FIG. The technical features of the present invention are more clearly presented. As shown in FIG. 9 , the first metal pad 309 and the second metal pad 310 are respectively electrically connected to the semiconductor layer 303 through two second contact holes 311 , and the first contact hole 308 and the two second contact holes 311 are located in the between the first scan line 305 and the second scan line 305'. The structure and configuration of other components in the third embodiment are substantially similar to those in the first embodiment. The cross-sectional schematic diagram of the first substrate 30 unfolded along the BB' cutting line in FIG. 9 is the same as that in FIG. 5 , which will not be repeated here. .

Please continue to refer to FIG. 10 , because in the third embodiment, by adjusting the wiring position and structure of the first substrate 30 , the active elements serving as the sub-pixel switches are centrally arranged, so, as shown in FIG. 10 , as the color filter The second substrate 40 of the sheet substrate can appropriately increase the width of the black matrix layer corresponding to the first substrate 30 with the opaque active elements and reduce the black matrix layer corresponding to the first substrate 30 without the opaque active elements. The width of the matrix layer can reduce the proportion of the overall black matrix layer and improve the aperture ratio of the display panel. Therefore, as shown in FIG. 10 , in Embodiment 3, the second substrate 40 serving as a color filter substrate includes four rows of pixel groups 401 of different colors (eg, red, green, blue, and white), and each pixel The group 401 includes a plurality of pixel units (401A, 401B, 401C) arranged along the second direction (the Y direction in FIG. 9 ) and of the same color, wherein, in the pixel group 401, the first black matrix layer I- I' is located between two adjacent pixel units and another two adjacent pixel units (eg, between 401A and 401B or between 401B and 401C). In Embodiment 3, the second substrate 40 also includes a second black matrix layer II-II' located between pixel groups of different colors. In Embodiment 3, the width of the first black matrix layer I-I' is about 5-50 μm, and the width of the second black matrix layer II-II’ is about 2-20 μm. In addition, since adjacent pixel units (as shown in 401A, 401B, and 401C) are of the same color, it is not necessary to avoid color mixing. Therefore, there is no need to set adjacent pixel units of the same color except for the active elements that are opaque. The black matrix layer (as shown by the dotted line) reduces the proportion of the overall black matrix layer and increases the aperture ratio of the display panel. Furthermore, the pixel groups included in the second substrate 40 of the third embodiment can be not only pixel groups with four colors of red, green, blue, and white, but those with ordinary knowledge in the art can also adjust the pixel groups to red and green according to requirements. and blue three-color pixel groups, the present invention is not particularly limited to this.

Therefore, as shown in FIG. 7 to FIG. 10 , by adjusting the wiring position and structure of the first substrate 30 as the array substrate, the proportion of the black matrix layer can also be reduced, and the aperture ratio of the display panel can be improved.

Example 4

The difference between Example 4 and Example 1 lies in the circuit arrangement of the first substrate as the array substrate and the arrangement of the pixel units of the second substrate as the color filter substrate.

Please refer to FIG. 11 , which is a schematic diagram of a circuit structure of the first substrate 50 of the fourth embodiment. Similar to Embodiment 1, FIG. 11 only shows the semiconductor layer 503 , the first scan line 505 , the second scan line 505 ′, the data line 507 , the first contact hole 508 , the second contact hole 511 , the first pixel electrode layer 513 and the The relative positional relationship of elements such as the second pixel electrode layer 515 is to more clearly present the technical features of the present invention. The difference between the fourth embodiment and the first embodiment is that the first pixel electrode layer 513 and the second pixel electrode layer 515 are not only on different sides of the data line 507 but also on the first scan line 505 when viewed from the top view direction. and the second scan line 505'. More specifically, the first scan line 505 includes a first inner edge 5051 and a first outer edge 5052, the second scan line 505' includes a second inner edge 5051' and a second outer edge 5052', The first inner edge 5051 is adjacent to the second inner edge 5051'. The first pixel electrode layer 513 and the second pixel electrode layer 515 are located between the first outer edge 5052 of the first scan line 505 and the second outer edge 5052' of the second scan line 505'. As for the structures and configurations of other elements that are substantially similar to those in Embodiment 1, detailed descriptions will not be given here.

Please also refer to FIG. 12 , which is a schematic top view of the first substrate 50 according to the fourth embodiment (corresponding to the position of the dotted frame in FIG. 11 ), wherein some elements (such as the pixel electrode and the third insulating layer, etc.) are omitted in FIG. The technical features of the present invention are more clearly presented. As shown in FIG. 12 , Embodiment 4 is similar to Embodiment 1. The first metal pad 509 and the second metal pad 510 are respectively electrically connected to the semiconductor layer 503 through two second contact holes 511 , and the first contact hole 508 is connected to the semiconductor layer 503 . The two second contact holes 511 are located between the first scan line 505 and the second scan line 505'. The structure and configuration of other components in the fourth embodiment are similar to those in the first embodiment. The schematic cross-sectional view of the first substrate 50 unfolded along the CC' cutting line in FIG. 12 is the same as that in FIG. 5 , which will not be repeated here. .

Please refer to FIG. 13A, which is a schematic diagram of the pixel polarity of the first substrate 50' designed with a known circuit structure. As shown in FIG. 13A , since the same data line 507 ′ inputs electrical signals to each pixel with a fixed positive and negative polarity, the pixels in each row have the same polarity, and the pixels in different rows have different polarities. polarity. Since the polarities of the adjacent pixels in the same column are opposite to each other, each pixel is prone to cross-talk with each other. On the contrary, please refer to FIG. 13B , which is a schematic diagram of the pixel polarity of the first substrate 50 according to Embodiment 4 of the present invention. Although the data line 507 of this embodiment 4 still inputs signals to each pixel with a fixed positive and negative polarity, due to the circuit configuration design of this embodiment 4, the pixels are driven in a column inversion manner, and adjacent pixels are The polarities of the pixels in the same column are the same as each other, and crosstalk is not easy to occur. Therefore, the first substrate 50 of the fourth embodiment has the advantages of low power consumption and low crosstalk.

Please continue to refer to FIG. 14 , which is a second substrate 60 corresponding to the first substrate 50 of FIG. 11 , wherein FIG. 14 shows the second substrate 60 in a manner of overlapping the partial circuits of the first substrate 50 of FIG. 11 for better clarity The relative positional relationship between the black matrix layer and the pixel group of the second substrate and the lines of the first substrate is displayed. In the fourth embodiment, by adjusting the wiring position and structure of the first substrate 50, the active elements of the sub-pixel switches are reduced. Therefore, as shown in FIG. 14, the second substrate 60 as the color filter substrate can be appropriately Adjust the position of the black matrix layer corresponding to the first substrate 50 having the opaque active elements, and configure the pixel units corresponding to the sub-pixel switches that are adjacent and do not share the same first contact hole as pixel groups of the same color , so as to reduce the proportion of the overall black matrix layer and improve the aperture ratio of the display panel. Therefore, as shown in FIG. 14 , in Embodiment 4, the second substrate 60 serving as a color filter substrate includes at least three pixel groups 601 of different colors (eg, red, green, and blue), and each pixel group 601 includes two adjacent pixel units (601A, 601B, and 601C) of the same color and arranged in the first direction, wherein, in the pixel group 601, the first black matrix layer II' is Located between the pixel groups 601 and extending along the first direction (X direction in the figure), the second black matrix layer II-II' is located between two adjacent pixel groups 601 . In addition, since adjacent pixel units (601A, 601B, or 601C) are of the same color, it is not necessary to avoid color mixing, so the second black color need not be set between adjacent pixel units (601A, 601B, or 601C) of the same color The matrix layer II-II' (eg, between the pixel units 601A) reduces the proportion of the overall black matrix layer and increases the aperture ratio of the display panel. Furthermore, although the pixel unit 601A is shown in a rectangle in the fourth embodiment, any shape of the black matrix layer can be used as long as the requirements of the known black matrix layer and the effect of improving the aperture ratio of the present invention can be met. Therefore, the present invention The shape of the pixel unit is not particularly limited. Furthermore, the pixel groups included in the second substrate 60 of the fourth embodiment can be not only pixel groups with three colors of red, green, and blue, but those with ordinary knowledge in the art can also adjust the pixel groups to red, green, and blue according to requirements. The pixel groups of four colors, blue and white, are not particularly limited in the present invention.

The above-mentioned embodiments are only examples for convenience of description, and the scope of the rights claimed in the present invention should be based on the scope of the claims, rather than being limited to the above-mentioned embodiments.

Claims (13)

1. a kind of display panel comprising a first substrate, a display layer and a second substrate, wherein the display layer is located at should Between first substrate and the second substrate, which includes:

One substrate；

Semi-conductor layer is located on the substrate；

One first insulating layer is located on the semiconductor layer；

One first scan line and one second scan line are located on first insulating layer, and extend respectively along a first direction, and one Partial first and second scan line is Chong Die with the semiconductor layer；

One second insulating layer is located on first scan line, second scan line and first insulating layer；

One data line, be located at the second insulating layer on, and along a second direction extend, the data line by one first contact hole with The semiconductor layer is electrically connected, wherein the second direction difference and the first direction；

One first metal gasket and one second metal gasket are located in the second insulating layer, first metal gasket and second metal gasket It is electrically connected respectively by two second contact holes and the semiconductor layer；

One third insulating layer is located in first metal gasket, second metal gasket and the second insulating layer；

One first pixel electrode layer is located on the third insulating layer, and first pixel electrode layer is by a third contact hole and is somebody's turn to do First metal gasket is electrically connected；And

One second pixel electrode layer is located on the third insulating layer, second pixel electrode layer by another third contact hole and Second metal gasket is electrically connected；

Wherein, first contact hole and two second contact hole are located between first scan line and second scan line.

2. display panel as described in claim 1, wherein first pixel electrode layer is adjacent to second pixel electrode layer The same side of the data line.

3. display panel as described in claim 1, wherein first pixel electrode layer is adjacent to second pixel electrode layer The data line it is not ipsilateral, and first scan line includes one first inside edge and one first outer ledge, this second is swept Retouching line includes one second inside edge and one second outer ledge, wherein adjacent second inner side edge in first inside edge Edge.

4. display panel as claimed in claim 3, wherein first pixel electrode layer be overlapped in first scan line this One inside edge and first outer ledge, and second pixel electrode layer is overlapped in second inner side edge of second scan line Edge and second outer ledge.

5. display panel as claimed in claim 3, wherein first pixel electrode layer is located at second pixel electrode layer should Between first outer ledge of the first scan line and the second outer ledge of second scan line.

6. display panel as described in claim 1 further includes multiple light shield layers, be located at the substrate and the semiconductor layer it Between, the position of the light shield layer corresponds respectively to first scan line region Chong Die with the semiconductor layer and this second is swept Retouch the line region Chong Die with the semiconductor layer.

7. display panel as claimed in claim 6 further includes a buffer layer, between the substrate and the semiconductor layer, And the light shield layer is located between the substrate and the buffer layer.

8. display panel as described in claim 1 further includes one first black-matrix layer and one second black-matrix layer, is located at Between the first substrate and the second substrate, which at least covers first scan line or second scanning Line, and second black-matrix layer at least covers the data line.

9. display panel as claimed in claim 8, wherein the width of first black-matrix layer is between 5 μm to 50 μm.

10. display panel as claimed in claim 8, wherein the second substrate is a colored filter substrate, the second substrate Pixel group including at least four different colours, wherein each pixel group includes four adjacent to each other and same color first Pixel unit, the second pixel unit, third pixel unit, with the 4th pixel unit, wherein first black-matrix layer or this Two black-matrix layers are located between the pixel group of different colours.

11. display panel as claimed in claim 8, wherein the second substrate is a colored filter substrate, the second substrate It include the pixel group of at least three row different colours, each pixel group includes multiple along second direction arrangement and same color Pixel unit, wherein in the pixel group, which is located at two adjacent pixel units and another two adjacent pixel Between unit.

12. display panel as described in claim 1 further includes one first black-matrix layer and one second black-matrix layer, position Between the first substrate and the second substrate, which at least covers first scan line or second scanning Line, and second black-matrix layer at least covers the data line of a part.

13. display panel as claimed in claim 12, wherein the second substrate is a colored filter substrate, second base Plate includes the pixel group of at least three different colours, and each pixel group includes two adjacent in the first direction and identical face The pixel unit of color, wherein first black-matrix layer or second black-matrix layer are located between the pixel group of different colours.