CN215895193U - Display panel and display device - Google Patents
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- CN215895193U CN215895193U CN202121720371.9U CN202121720371U CN215895193U CN 215895193 U CN215895193 U CN 215895193U CN 202121720371 U CN202121720371 U CN 202121720371U CN 215895193 U CN215895193 U CN 215895193U
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Abstract
本公开提供了一种显示面板和显示装置，属于显示技术领域。该显示面板包括衬底基板；多条数据线，设于衬底基板的一侧；多条栅线，设于数据线靠近衬底基板的一侧，数据线和栅线相互交叉界定出多个像素区；像素电极，位于像素区内，像素电极设于数据线靠近衬底基板的一侧；屏蔽电极，设于数据线靠近衬底基板的一侧，位于相邻两个像素区之间，屏蔽电极和像素电极位于数据线靠近衬底基板的同一层，屏蔽电极和像素电极绝缘，且屏蔽电极与栅线绝缘；屏蔽电极在衬底基板上的正投影与数据线在衬底基板上的正投影至少部分重叠。该显示面板使数据线与像素电极之间的耦合电容Cpd大幅度减小，进而降低串扰值，使显示画面更趋向于“臻品”画面。
The present disclosure provides a display panel and a display device, which belong to the technical field of display. The display panel includes a base substrate; a plurality of data lines, which are arranged on one side of the base substrate; the pixel area; the pixel electrode is located in the pixel area, and the pixel electrode is located on the side of the data line close to the base substrate; the shield electrode is located on the side of the data line close to the base substrate, located between two adjacent pixel areas, The shield electrode and the pixel electrode are located in the same layer of the data line close to the base substrate, the shield electrode is insulated from the pixel electrode, and the shield electrode is insulated from the grid line; the orthographic projection of the shield electrode on the base substrate is the same as that of the data line on the base substrate. The orthographic projections overlap at least partially. The display panel greatly reduces the coupling capacitance Cpd between the data line and the pixel electrode, thereby reducing the crosstalk value, so that the display image tends to be a "premium" image.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
In the field of Display technology, for example, Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs), the displays have advantages of lightness, thinness, low power consumption, high brightness, high image quality, and the like, and thus occupy an important position in the field of Display technology.
At present, for display products, various manufacturers strive to "fine" pictures. However, in an actual display screen, a certain display area is often affected by an adjacent area, so that abnormal screen display, namely Crosstalk (Crosstalk), is caused.
The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
The present disclosure provides a display panel and a display device, in which the coupling capacitance Cpd between a data line and a pixel electrode is greatly reduced, so as to reduce crosstalk, and make a display screen more trend to a "fine" screen.
In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:
according to a first aspect of the present disclosure, there is provided a display panel including:
a substrate base plate;
the data lines are arranged on one side of the substrate base plate, extend along the column direction and are arranged at intervals along the row direction;
the grid lines are arranged on one side, close to the substrate, of the data lines, extend along the row direction and are arranged at intervals along the column direction, and the data lines and the grid lines are intersected with each other to define a plurality of pixel regions;
the pixel electrode is positioned in the pixel area, the pixel electrode is arranged on one side of the data line close to the substrate base plate, and the pixel electrode and the grid line are positioned on the same layer of the data line close to the substrate base plate;
the shielding electrode is arranged on one side, close to the substrate base plate, of the data line and is positioned between two adjacent pixel regions, the shielding electrode and the pixel electrode are positioned on the same layer, close to the substrate base plate, of the data line, the shielding electrode and the pixel electrode are insulated, and the shielding electrode and the grid line are insulated;
the orthographic projection of the shielding electrode on the substrate base plate is at least partially overlapped with the orthographic projection of the data line on the substrate base plate.
In an exemplary embodiment of the present disclosure, an extending direction of the shielding electrode is the same as an extending direction of the data line, and an orthogonal projection of the shielding electrode on the substrate base plate completely covers an orthogonal projection of the data line on the substrate base plate in a direction perpendicular to the extending direction of the data line.
In an exemplary embodiment of the present disclosure, an orthogonal projection of the shield electrode on the substrate base plate in a direction perpendicular to an extending direction of the data line is at least partially located at a periphery of an orthogonal projection of the data line on the substrate base plate.
In an exemplary embodiment of the present disclosure, further comprising:
the grid layer is arranged at the same layer as the grid line;
the grid electrode insulating layer is arranged on one side, away from the substrate, of the grid electrode layer and the grid line, and covers the surface of the grid electrode layer;
the active layer is arranged on one side, away from the substrate, of the gate insulating layer;
the source drain layer is arranged on the same layer as the data line and is positioned on one side of the active layer, which is far away from the substrate;
the passivation layer is arranged on one side of the data line, which is deviated from the substrate base plate;
the common electrode is arranged on one side of the passivation layer, which is far away from the substrate base plate;
the pixel region comprises a first pixel region and a second pixel region which are arranged at intervals, the data line and the shielding electrode which are positioned between the first pixel region and the second pixel region are arranged adjacently, the data line is connected with the source drain electrode layer positioned in the first pixel region, and the shielding electrode is connected with the common electrode positioned in the second pixel region.
In an exemplary embodiment of the present disclosure, the shielding electrode includes:
an extension section extending in a first direction, the first direction being parallel to an extending direction of the data line;
the connecting section, connect in the one end of extension section, just the connecting section by the extension section is close to one side court in second pixel district the second pixel district direction extends out, the shielding electrode passes through the connecting section with common electrode connects.
In an exemplary embodiment of the present disclosure, an orthogonal projection of the shielding electrode on the substrate base plate is located at a periphery of an orthogonal projection of the pixel electrode on the substrate base plate.
In an exemplary embodiment of the present disclosure, the connection segment is formed with a first corner near an outer edge of the second pixel region, and an outer edge of the pixel electrode located in the second pixel region near the connection segment is formed with a second corner, and shapes of the first corner and the second corner match.
In an exemplary embodiment of the present disclosure, further comprising:
the color film substrate is arranged on one side, away from the substrate, of the common electrode and comprises a plurality of shading parts and a plurality of filter regions divided by the shading parts, the filter regions and the pixel regions are arranged in a one-to-one correspondence mode in the direction perpendicular to the substrate, and the orthographic projection of the filter regions on the substrate is located in the orthographic projection region of the pixel regions on the substrate;
the shielding electrode is connected with the common electrode through hole, and the orthographic projection of the shading part on the substrate completely covers the orthographic projection of the shielding electrode and the orthographic projection of the through hole on the substrate.
In an exemplary embodiment of the present disclosure, the display panel further includes a thin film transistor, the thin film transistor being located in the pixel region, the thin film transistor including the gate electrode layer, the gate insulating layer, the active layer, and the source drain layer;
the through hole is located in the second pixel area, the through hole is arranged on one side of the thin film transistor in the first pixel area along a second direction, and the second direction is parallel to the extending direction of the grid line.
In an exemplary embodiment of the present disclosure, a size of the shielding electrode is 2-4 μm larger than a dimension of the data line in a direction perpendicular to an extending direction of the data line.
In an exemplary embodiment of the present disclosure, the shielding electrode is a transparent electrode.
According to a first aspect of the present disclosure, there is provided a display device comprising the display panel of the first aspect.
The display panel provided by the disclosure comprises a substrate, a plurality of data lines, a plurality of grid lines, a pixel electrode and a shielding electrode. The shielding electrode is insulated from the grid line, the shielding electrode is arranged on one side of the data line close to the substrate and is positioned between two adjacent pixel regions, the shielding electrode and the pixel electrode are positioned on the same layer of the data line close to the substrate, and the shielding electrode and the pixel electrode are insulated; the orthographic projection of the shielding electrode on the substrate base plate is at least partially overlapped with the orthographic projection of the data line on the substrate base plate. The shielding electrode can shield most electric field lines generated around the data lines, and the electric field lines generated by the shielding electrode can be offset with the data lines, so that the coupling capacitance Cpd between the data lines and the pixel electrode is greatly reduced, the crosstalk value is further reduced, and the display picture tends to be a 'fine' picture.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 is a schematic diagram of crosstalk failure simulation;
FIG. 2 is a schematic diagram of a display panel according to the related art;
FIG. 3 is a cross-sectional view A-A of FIG. 2;
fig. 4 is a diagram illustrating an equivalent principle of coupling capacitance between a data line and a pixel electrode in the related art;
FIG. 5 is a schematic structural diagram in an exemplary embodiment of the present disclosure;
FIG. 6 is a cross-sectional view B-B of FIG. 4;
FIG. 7 is a cross-sectional view C-C of FIG. 4;
fig. 8 is a diagram of an equivalent principle of a coupling capacitance between a data line and a pixel electrode and a fringe field capacitance in an exemplary embodiment of the present disclosure;
fig. 9 is a schematic diagram of a structure of forming a pixel electrode in an exemplary embodiment of the present disclosure;
fig. 10 is a schematic diagram of a structure for forming a gate layer, a gate line and a shield electrode in an exemplary embodiment of the disclosure;
FIG. 11 is a schematic diagram of an active layer structure formed in an exemplary embodiment of the present disclosure;
FIG. 12 is a schematic diagram of a structure for forming source and drain layers and a data line in an exemplary embodiment of the disclosure;
fig. 13 is a schematic diagram of a structure for forming a passivation layer and a via in an exemplary embodiment of the disclosure.
The reference numerals of the main elements in the figures are explained as follows:
01-data line; 02-gate layer; 03-pixel electrode; 04-a common electrode; 05-a gate insulating layer; 06-a passivation layer; 07-a substrate base plate; 08-a grid line;
1-a substrate base plate; 2-a data line; 3-a grid line; 4-pixel region; 4 a-a first pixel region; 4 b-a second pixel region; 41-pixel electrode; 411-a second corner; 42-a common electrode; 5-a shield electrode; 51-an extension; 52-a connecting segment; 521-a first corner; 6-gate layer; 7-a gate insulating layer; 8-an active layer; 9-source drain layer; 10-a passivation layer; 101-a via hole; 20-a color film substrate; 201-a light shielding portion; 202-a filter zone; 30-a thin film transistor; x-a first direction; y-second direction.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.
In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.
When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.
In the field of thin film transistor liquid crystal display, various manufacturers have pursued "fine" pictures as much as possible: and in different display areas, the display requirements of different pictures are met according to preset conditions. As shown in fig. 1 (taking the middle L255 and the surrounding L127 gray-white pictures as an example), it is required to display the L255 picture in the middle region (the fifth region), and display the L127 picture in the surrounding regions (the fourth region/the sixth region/the ninth region).
The display device at least comprises an array substrate provided with a pixel array, and the array substrate generally comprises a grid line and a data line which are positioned in two adjacent pixel regions, a pixel electrode, a common electrode and the like which are positioned in the pixel regions. In the related art, in order to meet the display requirements of the "fine" picture, a conventional ADS (Advanced Super Dimension Switch) display mode is used as a basic design, and different column inversion signals are respectively input into a data line and a gate line to achieve a dot inversion display effect, so as to achieve the purpose of better controlling different display areas.
The corresponding pixel structure (taking 6mask design as an example) in the conventional ADS display mode is shown in fig. 2: the data lines 01 and the gate lines 08 cross to define a pixel region, the gate lines 08 are connected to the gate electrode layer 02, and the data lines 01 and the gate lines 08 supply driving signals for displaying pictures. The structure shown in fig. 3 is a cross-sectional view a-a in fig. 2, from which it can be seen that: the gate layer 02 and the pixel electrode 03 are located on the same layer of the substrate 07, and the gate layer 02 and the pixel electrode 03 belong to the same layer of metal; the data line 01 is a metal material, above the two and separated by a gate insulating layer 05; and the common electrode 04 belongs to the top metal and is separated from the data line 01 by the passivation layer 06.
As shown in fig. 4, in this structure, when different pixel regions input different electrical signals, a certain pixel region is affected by the input signals of its neighboring pixel regions due to the difference of the input signals. For example, when a large electrical signal passes through the data line in the region (v) shown in fig. 1 and a small electrical signal passes through the peripheral pixel region (v), the pixel electrode in the peripheral pixel region is affected by the electric field of the data line in the region (v), i.e., the coupling capacitance Cpd is generated, thereby affecting the normal display of the peripheral pixel region, which is known as Crosstalk (Crosstalk) failure.
As shown in fig. 5 to 7, the display panel provided in the embodiment of the present disclosure includes a substrate 1, a plurality of data lines 2, a plurality of gate lines 3, a pixel electrode 41, and a shielding electrode 5. The data lines 2 are arranged on one side of the substrate base plate 1, and the data lines 2 extend along the column direction and are arranged at intervals along the row direction; the plurality of gate lines 3 are arranged on one side of the data lines 2 close to the substrate base plate 1, the plurality of gate lines 3 extend along the row direction and are arranged at intervals along the column direction, and the data lines 2 and the gate lines 3 are crossed with each other to define a plurality of pixel regions 4; the pixel electrode 41 is positioned in the pixel region 4, the pixel electrode 41 is arranged on one side of the data line 2 close to the substrate 1, and the pixel electrode 41 and the gate line 3 are positioned on the same layer of the data line 2 close to the substrate 1; and the shielding electrode 5 is arranged on one side of the data line 2 close to the substrate base plate 1 and positioned between two adjacent pixel regions 4, the shielding electrode 5 and the pixel electrode 41 are positioned on the same layer of the data line 2 close to the substrate base plate 1, the shielding electrode 5 is insulated from the pixel electrode 41, and the shielding electrode 5 is insulated from the grid line 3.
The display panel provided by the present disclosure includes a substrate 1, a plurality of data lines 2, a plurality of gate lines 3, a pixel electrode 41, and a shielding electrode 5. The shielding electrode 5 is insulated from the gate line 3, the shielding electrode 5 is arranged on one side of the data line 2 close to the substrate base plate 1 and is positioned between two adjacent pixel regions 4, the shielding electrode 5 and the pixel electrode 41 are positioned on the same layer of the data line 2 close to the substrate base plate 1, and the shielding electrode 5 is insulated from the pixel electrode 41; the orthographic projection of the shielding electrode 5 on the substrate 1 is at least partially overlapped with the orthographic projection of the data line 2 on the substrate 1. The shielding electrode 5 can shield most of the electric field lines generated around the data line 2, and the electric field lines generated by the shielding electrode 5 cancel the data line 2, so that the coupling capacitance Cpd between the data line 2 and the pixel electrode 41 is greatly reduced, and the crosstalk value is reduced, so that the display image tends to be a 'fine' image.
The components of the display panel provided in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings:
as shown in fig. 5 to 7, a Display panel is provided in the embodiment of the present disclosure, and the Display panel may be a TFT-LCD (Thin Film Transistor Liquid Crystal Display) Display panel.
The base substrate 1 may be an inorganic base substrate 1 or an organic base substrate 1. For example, in one embodiment of the present disclosure, the material of the substrate base plate 1 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, or sapphire glass, or may be a metal material such as stainless steel, aluminum, or nickel. In another embodiment of the present disclosure, the material of the substrate 1 may be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. The substrate 1 may also be a flexible substrate 1, for example, in one embodiment of the present disclosure, the material of the substrate 1 may be Polyimide (PI). The substrate 1 may also be a composite of multiple layers of materials, for example, in an embodiment of the present disclosure, the substrate 1 may include a Bottom Film layer (Bottom Film), a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.
The gate line 3 and the data line 2 may be a layer of conductive material or a stack of multiple layers of conductive material. For example, in one embodiment of the present disclosure, the gate line 3 may include a first conductive material layer, a second conductive material layer, and a first conductive material layer stacked in sequence, that is, in a sandwich structure. The first conductive material layer may be made of corrosion-resistant metal or alloy, such as molybdenum; the second conductive material layer may be made of a metal or an alloy having high conductivity, such as copper, aluminum, silver, or the like. As another example, in another embodiment of the present disclosure, the gate line 3 may include a layer of conductive material, for example, the material of the gate line 3 may be molybdenum. The data line 2 may include the same conductive material as the gate line 3.
In some embodiments, the display panel further includes a gate layer 6 disposed on a side of the data line 2 close to the substrate 1, and disposed on a same layer as the gate line 3. The gate layer 6 may comprise a metal material or an alloy material to ensure good electrical conductivity. Of course, the gate layer 6 may also be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), and the like.
The gate electrode layer 6 and the gate line 3 may be formed by a photolithography process, and the gate line 3 and the gate electrode layer 6 may be formed by the same photolithography process. For example, a conductive material layer may be deposited on one side of the substrate 1 and then patterned to obtain the desired gate lines 3 and gate electrode layers 6.
The display panel further comprises a gate insulating layer 7, which is arranged on one side of the gate layer 6 and the gate line 3 away from the substrate 1, wherein the gate insulating layer 7 covers the surface of the gate layer 6. The gate insulating layer 7 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, or a plurality of layers formed by a combination thereof. The gate insulating layer 7 may be formed by a deposition method, for example, a silicon oxide layer may be formed by a vapor chemical deposition method as a gate insulating material layer, and the gate insulating layer 7 may be formed after patterning the gate insulating material layer.
The display panel further comprises an active layer 8 arranged on the side of the gate insulating layer 7 facing away from the substrate 1. The material of the active layer 8 may be polysilicon or IGZO (indium gallium zinc oxide), which may change the conductivity at different positions through processes such as doping.
The display panel further comprises a source drain layer 9, which is arranged on the same layer as the data line 2 and is located on one side of the active layer 8, which is far away from the substrate base plate 1. The source-drain layer 9 includes a source and a drain connected to the active layer 8.
The gate layer 6, the gate insulating layer 7, the active layer 8, and the source-drain layer 9 may be used to form the thin film transistor 30. In some embodiments of the present disclosure, the display panel further includes a thin film transistor 30, the thin film transistor 30 is located in the pixel region 4, and the thin film transistor 30 includes a gate electrode layer 6, a gate insulating layer 7, an active layer 8, and a source drain layer 9. The thin film transistor 30 serves as a constituent structure of a pixel driving circuit to drive the liquid crystal pixel region.
The pixel electrode 41 is located in the pixel region 4, the pixel electrode 41 is located on one side of the data line 2 close to the substrate 1, and the pixel electrode 41 and the gate line 3 are located on the same layer of the data line 2 close to the substrate 1. The pixel electrode 41 may be a plate electrode or a slit electrode. In some embodiments of the present disclosure, the pixel electrode 41 is a plate electrode. The pixel electrode 41 may be formed before the gate electrode layer 6 and the gate line 3 are formed. Specifically, the required pixel electrode 41 can be obtained by depositing a pixel electrode material layer on the surface of the base substrate 1, and then patterning the pixel electrode material layer. The pixel electrode 41 may be made of a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), or the like.
The shielding electrode 5 is insulated from the gate line 3, the shielding electrode 5 is arranged on one side of the data line 2 close to the substrate 1 and is positioned between two adjacent pixel regions 4, the shielding electrode 5 and the pixel electrode 41 are positioned on the same layer of the data line 2 close to the substrate 1, the shielding electrode 5 is insulated from the pixel electrode 41, and the shielding electrode 5 is insulated from the gate line 3. The orthographic projection of the shielding electrode 5 on the substrate 1 is at least partially overlapped with the orthographic projection of the data line 2 on the substrate 1.
The shielding electrode 5 and the pixel electrode 41 are located on the same layer of the data line 2 near the substrate 1, and may be located on the same surface of one side of the substrate 1. When no other film layer is arranged on one side of the substrate base plate 1, the shielding electrode 5 and the pixel electrode 41 can be positioned on the same surface of the substrate base plate 1; when the substrate base plate 1 is provided with other film layers, such as a planarization layer, the shielding electrode 5 and the pixel electrode 41 may be located on the same surface of the planarization layer facing away from the substrate base plate 1. The shielding electrode 5 and the pixel electrode 41 are insulated.
In some embodiments, the shield electrode 5, the gate line 3, or the gate layer 6 are disposed in the same layer. The shield electrode 5, the gate line 3 and the gate electrode layer 6 may be formed through the same patterning process. For example, a conductive material layer may be deposited on one side of the substrate 1 and then patterned to obtain the desired shielding electrode 5, gate line 3 and gate layer 6. The shield electrode 5 is formed to be insulated from the gate line 3.
The shielding electrode 5 may comprise a metallic material or an alloy material to ensure good electrical conductivity thereof. Of course, the shielding electrode 5 may be a transparent electrode, and a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), or the like may be used.
As shown in fig. 8, an orthogonal projection of the shield electrode 5 on the substrate 1 at least partially overlaps an orthogonal projection of the data line 2 on the substrate 1. When the positions of the shielding electrode 5 and the data line 2 correspond to each other, most of the electric field lines generated around the data line 2 can be shielded by the shielding electrode 5, and the electric field lines generated by the shielding electrode 5 and the data line 2 cancel each other out, so that the coupling capacitance Cpd between the data line 2 and the pixel electrode 41 is greatly reduced, and further, the crosstalk value is reduced, and the display picture tends to be a "fine" picture.
As shown in fig. 5, in some embodiments of the present disclosure, the extending direction of the shielding electrode 5 is the same as the extending direction of the data line 2, and the orthogonal projection of the shielding electrode 5 on the substrate base plate 1 completely covers the orthogonal projection of the data line 2 on the substrate base plate 1 in the direction perpendicular to the extending direction of the data line 2. In this embodiment, perpendicular to the extending direction of the data line 2, that is, the width direction of the data line 2, and perpendicular to the extending direction of the data line 2, the orthographic projection of the shielding electrode 5 on the substrate base 1 completely covers the orthographic projection of the data line 2 on the substrate base 1, that is, in the width direction of the data line 2, the orthographic projection of the shielding electrode 5 on the substrate base 1 completely covers the orthographic projection of the data line 2 on the substrate base 1. It is specifically understood that the width of the shield electrode 5 is equal to or greater than the width of the data line 2. It should be noted that, in this embodiment, the width of the shielding electrode 5 is only required to be greater than or equal to the width of the data line 2, and other directions are not required.
Specifically, since the shielding electrode 5 and the gate line 3 may be disposed on the same layer, and the shielding electrode 5 and the gate line 3 need to be insulated, a gap may be formed between the shielding electrode 5 and the gate line 3 in the extending direction of the data line 2, and the size of the gap may be set according to actual conditions.
Further, in the direction perpendicular to the extending direction of the data line 2, the orthographic projection of the shielding electrode 5 on the substrate base 1 is at least partially located at the periphery of the orthographic projection of the data line 2 on the substrate base 1. That is, in the width direction of the data line 2, the orthographic projection of the shield electrode 5 on the base substrate 1 is at least partially located at the periphery of the orthographic projection of the data line 2 on the base substrate 1. It is understood that the width of the shielding electrode 5 is greater than the width of the data line 2. In this embodiment, since the width of the shielding electrode 5 is greater than the width of the data line 2, the shielding electrode 5 can substantially shield all the electric field lines generated around the data line 2, and a part of the electric field lines generated by the shielding electrode 5 will cancel each other out with the data line 2, so that the coupling capacitance Cpd between the data line 2 and the pixel electrode 41 is greatly reduced, thereby better reducing the crosstalk value and ensuring the "good" picture of the display screen.
In a specific embodiment, the size of the shield electrode 5 is 2-4 μm larger than the size of the data line 2 in a direction perpendicular to the extension direction of the data line 2. It is understood that the width of the shield electrode 5 is 2-4 μm larger than the width of the data line 2.
As shown in fig. 6 and 7, in some embodiments of the present disclosure, the display panel further includes a passivation layer 10 and a common electrode 42 disposed on a side of the data line 2 facing away from the substrate base plate 1. The passivation layer 10 may be made of silicon oxide, silicon oxynitride, or the like. The common electrode 42 is provided on a side of the passivation layer 10 facing away from the substrate base plate 1. The common electrode 42 may be a plate electrode or a slit electrode. In some embodiments of the present disclosure, the common electrode 42 is a slit electrode and is located on a side of the pixel electrode 41 facing away from the substrate base plate 1. The common electrode 42 may be formed after the passivation layer 10 is formed. Specifically, the common electrode 42 can be obtained by depositing a common electrode 42 material layer on the surface of the substrate 1 and then patterning the common electrode 42 material layer. The common electrode 42 may be made of a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), or the like.
As shown in fig. 5 to 7, the pixel region 4 includes first and second pixel regions 4a and 4b arranged at intervals, and among the data line 2 and the shielding electrode 5 located between the adjacent first and second pixel regions 4a and 4b, the data line 2 is connected to the source drain layer 9 located in the first pixel region 4a, and the shielding electrode 5 is connected to the common electrode 42 located in the second pixel region 4 b. Specifically, the common electrode 42 is via-connected to the shield electrode 5, and the connection via 101 extends through the passivation layer 10 and the gate insulating layer 41 to the shield electrode 5.
In the field of liquid crystal display of the tft 30, a technical means for improving the cross defect of the liquid crystal display screen can be implemented by changing other conditions in addition to reducing the coupling capacitance Cpd between the data line 2 and the pixel electrode 41.
The crosstalk simulation formula is: the Crosstalk value is approximately equal to the change percentage of the Pixel voltage, in the formula, V1 is the voltage after the jump of the data line 2, V2 is the initial voltage of the data line 2, and Cpd/Cst _ min is the jump ratio of the Pixel due to the capacitance coupling voltage. From this equation, it can be seen that the storage capacitor Cst and the coupling capacitor Cpd are important factors affecting the magnitude of Crosstalk. Therefore, in addition to reducing the coupling capacitance Cpd, increasing the storage capacitance Cst between the common electrode 42 and the pixel electrode 41 is also an important means for improving the cross defect and promoting the uniformity of the image display.
As shown in fig. 7 and 8, in the embodiment of the present disclosure, the shielding electrode 5 is connected to the pixel electrode 41 of the second pixel region 4b through the via 101, which is equivalent to increasing the area of the common electrode 42, that is, increasing the storage capacitance Cst between the common electrode 42 and the pixel electrode 41 of the second pixel region 4 b. In addition, although the shielding electrode 5 is located at the same layer as the pixel electrode 41, when an electrical signal changes in the conductive line, a fringe field capacitance is generated between the two, which also corresponds to an increase in a portion of the storage capacitance Cst. Therefore, the embodiment can further improve the crossbar defect, so that the display frame further tends to be a 'good' frame.
As shown in fig. 5 and 10, in some embodiments, the shielding electrode 5 includes an extension 51 and a connection 52, the extension 51 extends along a first direction X, and the first direction X is parallel to the extending direction of the data line 2; the connecting segment 52 is connected to one end of the extending segment 51, the connecting segment 52 extends from one side of the extending segment 51 close to the second pixel region 4b toward the second pixel region 4b, and the shielding electrode 5 is connected to the common electrode 42 through the connecting segment 52. In this embodiment the shielding electrode 5 is substantially L-shaped.
The orthographic projection of the shielding electrode 5 on the substrate base plate 1 is positioned at the periphery of the orthographic projection of the pixel electrode 41 on the substrate base plate 1, namely, a gap is formed between the shielding electrode 5 and the pixel electrode 41, so that short circuit between the two electrodes is avoided. Meanwhile, when an electrical signal in the wire changes, a fringe field capacitance is generated between the two.
As shown in fig. 9 and 10, in particular, the connection segment 52 is formed with a first corner 521 near the outer edge of the second pixel region 4b, and a second corner 411 near the outer edge of the connection segment 52 of the pixel electrode 41 located in the second pixel region 4b, and the shapes of the first corner 521 and the second corner 411 are matched. In this embodiment, the corner arrangement can increase the positive opposing area between the shielding electrode 5 and the pixel electrode 41, so that the fringe field capacitance between the two is increased, thereby further increasing the storage capacitance Cst and improving the crosstalk phenomenon.
The shape of the first corner 521 and the second corner 411 match. For example, the first corner 521 is a convex corner, and the second corner 411 is a concave corner. The first corner 521 can form an angle with an angle size larger than 0, such as 50 °, 80 °, or 90 °, and the second corner 411 forms an angle matching the first corner 521.
As shown in fig. 5, in some embodiments of the present disclosure, the display panel further includes a color filter substrate 20 disposed on a side of the common electrode 42 away from the substrate 1, where the color filter substrate 20 includes a plurality of light-shielding portions 201 and a plurality of filter regions 202 partitioned by the light-shielding portions 201, the filter regions 202 and the pixel regions 4 are disposed in a one-to-one correspondence in a direction perpendicular to the substrate 1, and an orthographic projection of the filter regions 202 on the substrate 1 is located in an orthographic projection region of the pixel regions 4 on the substrate 1. The filter region 202 is provided with color filters, which may include R (red), G (green), and B (blue) filters, each corresponding to one pixel region 4, and each being spaced apart by the light shielding portion 201.
The shielding electrode 5 is connected with the common electrode 42 through a via hole, and the orthographic projection of the light shielding part 201 on the substrate 1 completely covers the orthographic projection of the shielding electrode 5 and the via hole 101 on the substrate 1.
In the pixel structure corresponding to the conventional ADS display mode, the data line 2 and the gate line 3 are metal lines, which can provide a driving signal for a display screen, but since a stable horizontal electric field cannot be provided near the two signal lines to control liquid crystal deflection, the light shielding portion 201bm (black matrix) of the color film substrate 20 needs to be used for shielding. In the embodiment of the present disclosure, the shielding electrode 5 and the via hole 101 may be located in an original shading portion 201 region of the color filter substrate 20, so as not to affect the aperture ratio of the display panel. It should be noted that the via 101 is formed on the surface of the passivation layer 10 and further extends through the passivation layer 10 to the shielding electrode 5. In particular, it may extend to the connection section 52 of the shielding electrode 5.
As described above, the display panel further includes the thin film transistor 30, the thin film transistor 30 is located in the pixel region 4, and the thin film transistor 30 includes the gate electrode layer 6, the gate insulating layer 7, the active layer 8, and the source drain layer 9. The thin film transistor 30 serves as a constituent structure of a pixel driving circuit to drive the liquid crystal pixel region. In some embodiments of the present disclosure, the via hole 101 is located in the second pixel region 4b, and the via hole 101 is disposed at one side of the thin film transistor 30 in the first pixel region 4a along a second direction Y, which is parallel to the extending direction of the gate line 3.
In the related art, a stable horizontal electric field cannot be provided near the data lines 2 and the gate lines 3 to control liquid crystal deflection, and therefore, a light-shielding layer bm (black matrix) of the color film substrate 20 is required to perform shielding, and a shielding region is shown by a dotted line region in fig. 5.
In the present disclosure, the extending direction of the shielding electrode 5 is parallel to the extending direction of the data line 2, and the via 101 connection structure is disposed at one side of the thin film transistor 30 of the first pixel region 4a along the second direction Y, which is parallel to the extending direction of the gate line 3. The structural design does not influence the aperture ratio of the display panel in the related art in the row direction or the column direction
The display panel provided by the present disclosure can effectively reduce the coupling capacitance Cpd between the data line 2 and the pixel electrode 41, and increase the storage capacitance between the common electrode 42 and the pixel electrode 41, on the basis of not increasing the original process steps, thereby effectively improving the poor crosstalk.
As shown in fig. 9 to 13 and fig. 5, the display panel provided by the present disclosure may be formed by a manufacturing process in the related art, which is as follows:
(1) as shown in fig. 9, a pixel electrode 41 is formed on one side of the base substrate 1;
(2) as shown in fig. 10, a gate layer 6, a gate line 3 and a shielding electrode 5 are formed on one side of a substrate 1, specifically, a conductive material layer is deposited on one side of the substrate 1, and then the conductive material layer is patterned to obtain the gate layer 6, the gate line 3 and the shielding electrode 5, wherein the gate layer 6, the gate line 3, the shielding electrode 5 and the pixel electrode 41 are located in the same layer;
(3) as shown in fig. 11, an active layer 8 is formed on the side of the gate layer 6 facing away from the substrate base plate 1;
(4) as shown in fig. 12, a source/drain layer 9 and a data line 2 are formed on the side of the active layer 8 away from the substrate base plate 1;
(5) as shown in fig. 13, a passivation layer 10 and a via hole 101 are formed on one side of the source drain layer 9 away from the substrate base plate 1, and the passivation layer 10 covers the surface of the source drain layer 9;
(6) as shown in fig. 5, a common electrode 42 layer is formed on the side of the passivation layer 10 facing away from the substrate base plate 1, and the common electrode 42 is connected to the shielding electrode 5 through a via 101.
The embodiment of the present disclosure further provides a display device, which includes a display panel, where the display panel may be the display panel of any of the above embodiments, and the specific structure and the beneficial effects of the display device may refer to the above embodiments of the display panel, which are not described herein again. The display device disclosed by the disclosure can be an electronic device such as a mobile phone, a tablet computer, a television and the like, which are not listed.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.
Claims (12)
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|---|---|---|---|
| CN202121720371.9U CN215895193U (en) | 2021-07-27 | 2021-07-27 | Display panel and display device |
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| CN202121720371.9U CN215895193U (en) | 2021-07-27 | 2021-07-27 | Display panel and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114660857A (en) * | 2022-03-22 | 2022-06-24 | Tcl华星光电技术有限公司 | Display panel and mobile terminal |
| WO2024011858A1 (en) * | 2022-07-12 | 2024-01-18 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
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2021
- 2021-07-27 CN CN202121720371.9U patent/CN215895193U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114660857A (en) * | 2022-03-22 | 2022-06-24 | Tcl华星光电技术有限公司 | Display panel and mobile terminal |
| WO2024011858A1 (en) * | 2022-07-12 | 2024-01-18 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
| US12235556B2 (en) | 2022-07-12 | 2025-02-25 | Beijing Boe Display Technology Co., Ltd. | Display substrate, display panel and display device |
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