TW202209294A - Pixel array - Google Patents

Abstract

A pixel array includes a substrate, a plurality of transverse signal lines, a plurality of first vertical signal lines, a plurality of second vertical signal lines, and a plurality of pixel structures. The transverse signal line and the pixel structure are disposed on the active area of the substrate. The first vertical signal line is extended from the peripheral area of the substrate into the active area and intersected the transverse signal line. The second vertical signal line is electrically connected to one of the plurality of transverse signal lines, and adjacent to at least one of the first vertical signal lines, one of the plurality of second vertical signal lines includes a transverse pattern, wherein the transverse pattern is adjacent to the other one of the plurality of transverse signal lines. The pixel structure is electrically connected with the transverse signal line and the first vertical signal line.

Description

pixel array

The present invention relates to a pixel array, and more particularly, to a pixel array having a lateral pattern.

With the advancement of science and technology, large-size panels are mostly developed towards the design of narrow bezels. At present, TGP (Tracking Gate-line in Pixel) narrow frame technology is mostly used, so that the gate line extending in the horizontal direction is electrically connected to the gate driving circuit through the switching element extending in the vertical direction, so as to further reduce the panel frame. width.

However, when the switching element is arranged in the active area, the switching element is bound to be adjacent to the data line, which is prone to problems such as coupling with the adjacent data line or generating gate-drain capacitance (Cgd). It often affects the quality of signal transmission, resulting in the final function not meeting expectations. For example, the coupling between the switching element and the data line tends to cause the voltage of the pixel to be higher than a predetermined value, and a bright spot with a diagonal line appears on the display screen, which affects the user's viewing experience. Therefore, how to solve the above problems has become a topic that researchers are concerned about at present.

The present invention provides a pixel array, the design of which can help meet the requirements of narrow frame design, and can reduce the coupling between lines and improve the quality of the pixel array.

At least one embodiment of the present invention provides a pixel array including a substrate, a plurality of horizontal signal lines, a plurality of first vertical signal lines, a plurality of second vertical signal lines, and a plurality of pixel structures. The substrate has an active area and a peripheral area outside the active area. The horizontal signal line is arranged in the active area. The first vertical signal line extends from the peripheral area into the active area and intersects with the horizontal signal line. The second vertical signal line is electrically connected to one of the plurality of horizontal signal lines, and is adjacent to the at least one first vertical signal line, and one of the plurality of second vertical signal lines includes a horizontal pattern, wherein the horizontal pattern is the same as the one of the horizontal pattern. adjacent to the other of the plurality of lateral signal lines. The pixel structure is arranged in the active area and is electrically connected with the horizontal signal line and the first vertical signal line. One of the plurality of pixel structures is connected by two adjacent horizontal signal lines and two adjacent first vertical signal lines. around.

In an embodiment of the present invention, the length of the lateral pattern is greater than or equal to the lateral width of one of the plurality of pixel structures.

In an embodiment of the present invention, at least one of the plurality of second vertical signal lines includes a horizontal pattern, and at least one of the plurality of second vertical signal lines does not include a horizontal pattern.

In an embodiment of the present invention, each of the plurality of second vertical signal lines includes a horizontal pattern.

In an embodiment of the present invention, the second vertical signal line including the horizontal pattern further includes a first vertical pattern and a second vertical pattern, wherein the first vertical pattern and the second vertical pattern are respectively adjacent to both ends of the horizontal pattern, and are respectively adjacent to the two first vertical signal lines. Moreover, the first vertical pattern, the horizontal pattern and the second vertical pattern are electrically connected in sequence.

In an embodiment of the present invention, the first longitudinal pattern and the second longitudinal pattern are located in the same film layer, and the film layer where the transverse pattern is located is different from the film layer where the first longitudinal pattern and the second longitudinal pattern are located.

In an embodiment of the present invention, the pixel array further includes a first switching structure and a second switching structure, wherein the first switching structure is disposed in the active area, and in a top view of the pixel array, the first switching structure is The connection structure is arranged at the intersection of the first longitudinal pattern and the horizontal pattern; the second connection structure is arranged in the active area, and in the top view of the pixel array, the second connection structure is arranged at the intersection of the second longitudinal pattern and the transverse pattern place. In addition, the first vertical pattern is connected to the horizontal pattern through the first transfer structure, and the horizontal pattern is connected to the second vertical pattern through the second transfer structure.

In an embodiment of the present invention, the length of the first longitudinal pattern in the longitudinal direction is greater than or equal to a pixel structure, and the length of the second longitudinal pattern in the longitudinal direction is greater than or equal to b pixel structures , where a and b are positive integers.

In an embodiment of the present invention, the above-mentioned b is 1.

In an embodiment of the present invention, the above-mentioned pixel array further includes a plurality of gate driving pads, wherein the plurality of gate driving pads are arranged in a lateral order in the peripheral region, and each gate driving pad is electrically connected to a corresponding The second vertical signal line.

In an embodiment of the present invention, the above-mentioned pixel array further includes constant voltage lines, wherein the constant voltage lines are arranged in the peripheral region and have main line segments and branch line segments. The main line segment is parallel to the horizontal signal line, and the branch line segment extends along one of the plurality of first vertical signal lines from the main line segment and spans c pixel structures, wherein c is a positive integer. In the top view of the pixel array, one end of the branch line segment relative to the main line segment is separated by a distance from the electrical connection between the second vertical signal line and the horizontal signal line, and the distance is smaller than the longitudinal direction of one of the plurality of pixel structures length.

In an embodiment of the present invention, the above distance is 3 μm˜5 μm.

In an embodiment of the present invention, the pixel array further includes an insulating layer, wherein the insulating layer covers the first vertical signal line and the second vertical signal line and has grooves. The groove extends along the first longitudinal signal line and the second longitudinal signal line, and the projection of the groove on the substrate is located between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate.

Based on the above, in the present invention, one of the second longitudinal signal lines includes a horizontal pattern, so that the second longitudinal signal lines can be appropriately segmented in the longitudinal direction, thereby reducing the transmission of signals from the second longitudinal signal lines to the adjacent first longitudinal signal lines. The coupling phenomenon generated during the process helps to reduce the coupling between the lines and improve the quality of the pixel array while meeting the requirements of the narrow frame design.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on," "connected to," "overlying" another element, it can be directly on the other element on or connected to another element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer," or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprising" and/or "comprising" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but do not exclude one or more The presence or addition of other features, entireties of regions, steps, operations, elements, components, and/or combinations thereof.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" may include an orientation of "lower" and "upper", depending on the particular orientation of the figures. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "above" can encompass both an orientation of above and below.

As used herein, "about", or "substantially" includes the stated value and the average value within an acceptable deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with the measurement a specific amount (i.e., the limits of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", or "substantially" may be used to select a more acceptable range of variation or standard deviation depending on optical properties, etching properties, or other properties, and not one standard deviation may apply to all properties.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances, are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions as shown herein, but rather include deviations in shapes resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and/or nonlinear features. Additionally, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

FIG. 1A is a schematic top view of a pixel array according to a first embodiment of the present invention; FIG. 1B is a schematic cross-sectional view of the pixel array of FIG. 1A along the line A-A'. For the convenience of description, the position of the insulating layer and part of the pixel structure PX are omitted in FIG. 1A .

1A and 1B, the pixel array 10 includes a substrate 100, a plurality of lateral signal lines GL, a plurality of first vertical signal lines DL, a plurality of second vertical signal lines 110 and a plurality of pixel structures PX. The substrate 100 may have an active area AA and a peripheral area BA located outside the active area AA. In this embodiment, the material of the substrate 100 may include glass or other suitable materials, but the invention is not limited thereto.

The lateral signal line GL is disposed on the active area AA of the substrate 100 and extends along the lateral direction X. In this embodiment, the plurality of horizontal signal lines GL may include a horizontal signal line GL1, a horizontal signal line GL2, . . . , and a horizontal signal line GLn, wherein n is a positive integer. The horizontal signal line GL1, the horizontal signal line GL2, ..., the horizontal signal line GLn are arranged in sequence along the longitudinal direction Y, for example, as shown in FIG. The upper side of the substrate 100 to the lower side of the substrate 100 are sequentially arranged on the substrate 100 . The lateral direction X is staggered with the longitudinal direction Y. For example, in this embodiment, the lateral direction X and the longitudinal direction Y may be perpendicular, but the invention is not limited to this. The transverse direction and the longitudinal direction described in the following embodiments can be regarded as the transverse direction X and the longitudinal direction Y in FIG. 1A , respectively. In this embodiment, the lateral signal line GL may be a gate line.

The first vertical signal line DL is disposed on the substrate 100, extends from the peripheral area BA into the active area AA, and intersects with a plurality of lateral signal lines GL. In this embodiment, the plurality of first vertical signal lines DL may include a first vertical signal line DL1, a first vertical signal line DL2, . . . , a first vertical signal line DLm+1, wherein m is a positive integer. The first vertical signal line DL1, the first vertical signal line DL2, ..., the first vertical signal line DLm+1 are arranged in sequence along the lateral direction X, for example, as shown in FIG. The lines DL2 , . . . , and the first vertical signal line DLm+1 are sequentially arranged on the substrate 100 from the left side of the substrate 100 to the right side of the substrate 100 , for example. In this embodiment, the first longitudinal signal line DL may be a data line.

The second vertical signal line 110 is disposed on the substrate 100 . In this embodiment, in the lateral direction X, the second longitudinal signal line 110 is adjacent to at least one of the first longitudinal signal lines DL. In this embodiment, the extending direction of the second longitudinal signal line 110 may be substantially parallel to the first longitudinal signal line DL. For example, the second longitudinal signal line 110 and the first longitudinal signal line DL may be linear patterns parallel to each other, or may have zigzag patterns parallel to each other, but the invention is not limited thereto. In this embodiment, the second vertical signal line 110 can be used as a gate transfer line, and is electrically connected to one of the horizontal signal lines GL. In addition, in order to avoid the short circuit between the horizontal signal line GL and the second vertical signal line 110, the horizontal signal line GL and the second vertical signal line 110 can be composed of different film layers, and the horizontal signal line GL and the second vertical signal line 110 are formed by different layers. One or more insulating layers may be sandwiched between them. In some embodiments, the first longitudinal signal line DL and the second longitudinal signal line 110 may be located in the same film layer, and the lateral signal line GL may be located in a different film from the first longitudinal signal line DL and the second longitudinal signal line 110 in the layer. In some embodiments, the second vertical signal line 110 may be connected to the corresponding horizontal signal line GL through the corresponding conductive structure CS. In some embodiments, one of the second vertical signal lines 110 includes a horizontal pattern 114, wherein the horizontal pattern 114 is adjacent to another horizontal signal line GL that is not electrically connected to the second vertical signal line 110, but the present invention Not limited to this. For example, as shown in FIG. 1A , the leftmost second vertical signal line 110 - 1 in FIG. 1A can be electrically connected to the uppermost row through the conduction structure CS1 located in the uppermost row but not in the first row from the left the horizontal signal line GL1. More specifically, the second vertical signal line 110-1 in the first row is a horizontal pattern 114-1 adjacent to the horizontal signal line GL2 with a length spanning at least the horizontal width Wx of the six pixel structures PX. And a second vertical pattern 116 adjacent to the first vertical signal line DL7 and having a length spanning at least the vertical length Wy of one pixel structure PX is connected to the horizontal signal line GL1.

A plurality of pixel structures PX are arranged in an array on the active area AA of the substrate 100 . In other words, the pixel structure PX exhibits an array arrangement along the lateral direction X and the longitudinal direction Y. In this embodiment, each pixel structure PX is electrically connected to one of the horizontal signal lines GL and one of the first vertical signal lines DL. In addition, the second vertical signal line 110 is not directly connected to the pixel structure PX. For example, each pixel structure PX may include a thin film transistor (not shown) and a pixel electrode (not shown), wherein the source electrode and the gate electrode of the thin film transistor may be respectively electrically connected to the corresponding A first vertical signal line DL and a corresponding horizontal signal line GL, and the pixel electrode is electrically connected to the drain electrode of the thin film transistor.

The plurality of pixel structures PX can be sequentially arranged in the horizontal direction X to form pixel rows R1 to Rn (hereinafter sometimes abbreviated as a plurality of pixel rows R), and can be sequentially arranged in the vertical direction Y to form a pixel row Rn. Pixel row C1 to pixel row Cm (hereinafter sometimes abbreviated as a plurality of pixel rows C), wherein n and m may be synonymous with n of the plurality of horizontal signal lines GL and m of the plurality of first vertical signal lines DL. For example, the plurality of pixel rows R are sequentially arranged in the longitudinal direction Y; the plurality of pixel structures PX of each pixel row R are sequentially arranged in the lateral direction X. The plurality of pixel rows C are sequentially arranged in the lateral direction X; the plurality of pixel structures PX of each pixel row C are sequentially arranged in the longitudinal direction Y, but the invention is not limited to this. In this embodiment, the coordinates of a pixel structure PX located in the pixel row Cx and the pixel row Ry are (x, y), and the following is represented as a pixel structure PXxy, where x and y are positive integers, and 1≦x ≦m, 1≦y≦n. For example, the coordinates of a pixel structure PX located in pixel row C1 and pixel row R1 are (1, 1), and the following is denoted as pixel structure PX11; a pixel structure located in pixel row C1 and pixel row Rn The coordinates of PX are (1, n), and the following is denoted as the pixel structure PX1n; the coordinates of a pixel structure PX located in the pixel row Cm and the pixel row Rn are (m, n), and the following is denoted as the pixel structure PXmn.

In this embodiment, a pixel structure PX is surrounded by two adjacent horizontal signal lines GL and two adjacent first vertical signal lines DL. For example, taking the pixel structure PX11 as an example, the pixel structure PX11 is surrounded by the horizontal signal line GL1 , the horizontal signal line GL2 , the first vertical signal line DL1 and the first vertical signal line DL2 . In this embodiment, a plurality of pixel structures PX in the same pixel row C can be selectively electrically connected to the same first vertical signal line DL, and a plurality of pixel structures PX in two adjacent pixel rows R They can be respectively electrically connected to a plurality of different lateral signal lines GL. In short, in this embodiment, the pixel array 10 may adopt a driving method of one gate line and one data line (1G1D), but the invention is not limited to this. In some embodiments, a plurality of pixel structures PX in the same pixel row C can be selectively and sequentially electrically connected to the first vertical signal lines DL on different sides. For example, in the pixel row C1, the pixel structures PX located in odd-numbered columns such as the pixel structure PX11 can be electrically connected to the first vertical signal line DL1 located on the first side (the left side of FIG. 1A ), on the other hand , the pixel structure PX located in the even number row, such as the pixel structure PX12 , can be electrically connected to the first vertical signal line DL2 located on the second side (the right side of FIG. 1A ), but the invention is not limited thereto.

In this embodiment, the pixel array 10 may further have a plurality of gate driving pads GD in the peripheral area BA. A plurality of gate driving pads GD can be arranged in sequence in the peripheral region BA of the substrate 100 , and each gate driving pad GD is electrically connected to one of the second vertical signal lines 110 . For example, the plurality of gate driving pads GD may include gate driving pads GD1, gate driving pads GD2, . . . , gate driving pads GDp, wherein p is a positive integer, gate driving pads GD1, gate driving pads GD2 , . . . The gate driving pad GDp can be electrically connected to the corresponding second vertical signal line 110-1, the second vertical signal line 110-2, . . , and the second vertical signal line 110-p respectively in sequence. In some embodiments, the second vertical signal line 110-1, the second vertical signal line 110-2, . . . , and the second vertical signal line 110-p are respectively electrically connected to different horizontal signal lines GL Corresponding conductive structures CS1 , CS2 , . . . , and conductive structures CSp are provided, but the present invention is not limited thereto. For example, as shown in FIG. 1A , one end of the second vertical signal line 110-1 is connected to the gate driving pad GD1, and the other end of the second vertical signal line 110-1 is electrically connected to the horizontal signal line GL1 through the conduction structure CS1 sexual connection.

Please refer to FIG. 1A , it is worth noting that at least one second vertical signal line 110 in the pixel array 10 of the present embodiment includes a horizontal pattern 114 , and the second vertical signal line 110 can be appropriately adjusted in the vertical direction by the horizontal pattern 114 The ground segment can reduce the coupling phenomenon when the second vertical signal line 110 transmits signals to the adjacent first vertical signal line DL, thereby improving the quality of the pixel array. In the pixel array 10 of this embodiment, at least one of the second vertical signal lines 110 does not include the horizontal pattern 114 . For example, as shown in FIG. 1A , the second vertical signal line 110-1 and the second vertical signal line 110-3 include the horizontal pattern 114, and the second vertical signal line 110-2 and the second vertical signal line 110-4 do not The lateral pattern 114 is included, but the invention is not limited thereto.

In some embodiments, the length L of the lateral pattern 114 extending along the lateral direction X is greater than or equal to the lateral width Wx of one pixel structure PX. For example, the horizontal pattern 114-3 of the second vertical signal line 110-3 extends substantially from the first vertical signal line DL7 to the first vertical signal line DL13. In other words, the horizontal pattern 114-3 generally spans six frames. Prime structure PX. That is to say, the length L of the lateral pattern 114-3 corresponds to, for example, the sum of the lateral widths Wx of the six pixel structures PX. In some embodiments, the length L of the horizontal pattern 114 may be equivalent to the horizontal width Wx of one pixel structure PX. Those skilled in the art can adjust the length of the horizontal pattern according to design requirements, and the present invention is not limited thereto. .

In this embodiment, the second vertical signal line 110 including the horizontal pattern 114 may further include the first vertical pattern 112 and the second vertical pattern 116 . For example, the first longitudinal pattern 112 and the second longitudinal pattern 116 are respectively adjacent to both ends of the lateral pattern 114 , and the first longitudinal pattern 112 and the second longitudinal pattern 116 are respectively adjacent to different first longitudinal signal lines DL. In some embodiments, the first vertical pattern 112 can be electrically connected to the corresponding gate driving pad GD; the second vertical pattern 116 can be electrically connected to the corresponding horizontal signal line GL. Thereby, the signal from the gate driving source (not shown) is transmitted to the corresponding second vertical signal line 110 through the corresponding gate driving pad GD, and then the signal is transmitted through the horizontal pattern 114 or directly through the second vertical signal line 110 . The signal is transmitted to the lateral signal line GL, and then the lateral signal line GL is input to the gate of the pixel structure PX in the same row, thereby turning on or off the thin film transistor of the pixel structure PX in the row. For example, the first vertical pattern 112-1 of the second vertical signal line 110-1 extends from the gate driving pad GD1 along the first vertical signal line DL1 to the horizontal pattern 114-1, and the horizontal pattern 114-1 is along the horizontal signal line GL2 extends to the second vertical pattern 116-1, the second vertical pattern 116-1 extends to the horizontal signal line GL1 along the first vertical signal line DL7, and the first vertical pattern 112, the horizontal pattern 114 and the second vertical pattern 116 Electrically connected in sequence.

Please refer to FIG. 1B . FIG. 1B is a schematic cross-sectional view of the pixel array of FIG. 1A along the line A-A'. The first longitudinal pattern 112 and the second longitudinal pattern 116 are located in the same film layer, and the film layer where the transverse pattern 114 is located is different from the film layer where the first longitudinal pattern 112 and the second longitudinal pattern 116 are located. For example, the horizontal pattern 114 and the horizontal signal line GL may be located on the first conductor layer M1, and the first vertical pattern 112 and the second vertical pattern 116 and the first vertical signal line DL may be located on the second conductor above the first conductor layer M1 layer M2, but the present invention is not limited to this. In some embodiments, a first insulating layer I1 is further interposed between the first conductor layer M1 and the second conductor layer M2, and a second insulating layer I2 is also covered on the second conductor layer M2. The insulating layer I1 has a first through hole V1 and a second through hole V2. In a plan view of the substrate 100, the first through hole V1 and the second through hole V2 overlap with the first longitudinal pattern 112 and the second longitudinal pattern 116, for example, respectively. , and the first through hole V1 and the second through hole V2, for example, expose a part of the lateral pattern 114 . In addition, the first transfer structure 120 may be disposed in the first through hole V1, and the second transfer structure 122 may be disposed in the second through hole V2. In other words, as shown in FIG. 1A, the first transfer structure 120 The second transfer structure 122 may be disposed at the intersection of the first longitudinal pattern 112 and the lateral pattern 114 , and the second transfer structure 122 may be disposed at the intersection of the second longitudinal pattern 116 and the lateral pattern 114 . In this way, the first vertical pattern 112 can be connected to the horizontal pattern 114 through the first transfer structure 120 , and the horizontal pattern 114 can be connected to the second vertical pattern 116 through the second transfer structure 122 . In this way, the signal required by the gate can be transmitted between different film layers through the lateral pattern 114 of the second vertical signal line 110 to span a plurality of first vertical signal lines DL, so that the wiring design of the second vertical signal line 110 is relatively It is not limited, and can be used to adjust the electrical connection between the second vertical signal line 110 and the corresponding horizontal signal line GL (eg, the position of the conduction structure CS).

In this embodiment, the second vertical signal lines 110 not including the horizontal pattern 114 can be scattered between the first vertical pattern 112 and the second vertical pattern 116 of the same second vertical signal line 110 . For example, as shown in FIG. 1A , in the top view direction of the substrate 100 , the second longitudinal signal line 110 - 2 is located, for example, in the first longitudinal pattern 112 - 1 and the second longitudinal pattern 116 of the second longitudinal signal line 110 - 1 . -1; the second longitudinal signal line 110-4 is, for example, located between the first longitudinal pattern 112-3 and the second longitudinal pattern 116-3 of the second longitudinal signal line 110-3. In this way, a plurality of conductive structures CS can be scattered on the pixel array 10 (for example, as shown in FIG. 1A ), so that the brightness caused by the coupling effect of the first vertical signal line DL and the second vertical signal line 110 Abnormal (eg, bright) multiple pixel structures PX are also scattered on the pixel array 10 . Since a plurality of pixel structures PX with abnormal brightness (eg, bright) are scattered on the pixel array 10 , the human eye is not easily aware of the coupling effect between the first longitudinal signal line DL and the second longitudinal signal line 110 The resulting display screen is abnormal (for example, there is a bright line corresponding to the diagonal of the substrate). In addition, the pixel array 10 of the present embodiment can reduce the need to additionally arrange peripheral circuit traces in the peripheral area BA to make the second vertical signal line 110 and the horizontal signal line The conduction structure CS of GL has a disordered space to realize the design of narrow border.

FIG. 2 is a schematic top view of a pixel array according to a second embodiment of the present invention. For the convenience of description, the position of the insulating layer and part of the pixel structure PX are omitted from illustration in FIG. 2 . It must be noted here that FIG. 2 uses the element numbers and part of the content of the embodiment in FIGS. 1A and 1B , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIG. 2 , the difference between the pixel array 20 of the second embodiment and the pixel array 10 of the first embodiment is that the pixel array 20 of this embodiment also has a constant voltage line 200 . The constant voltage line 200 can provide a constant voltage. In this embodiment, the constant voltage line 200 can provide, for example, a low-level voltage Vgl derived from the driving element (for example, compared with the high-level voltage Vgh transmitted by the second vertical signal line 110 ), but this is not the case in the present invention limited. In some embodiments, the constant voltage line 200 may have a main line segment 202 extending laterally and a branch line segment 204 extending longitudinally. The main line segment 202 is, for example, parallel to the lateral signal line GL. For example, the branch line segment 204 extends along one of the plurality of first longitudinal signal lines DL from the main line segment 202 and spans c pixel structures PX, where c is a positive integer. In some embodiments, in the active area AA of the substrate 100, taking the second longitudinal signal line marked as 110-p in FIG. 2 as an example, the length D1 of the active area AA of the substrate 100 along the longitudinal direction Y is equivalent to the second longitudinal signal line 110-p. The sum of the length D2 of the longitudinal signal line 110 along the longitudinal direction Y and the length D3 of the branch line segment 204 along the longitudinal direction Y, but the invention is not limited to this.

In this embodiment, in the longitudinal direction Y, for example, the second longitudinal signal line 110 only extends to the conductive structure CS, and the branch line segment 204 may overlap in the extending direction of the second longitudinal signal line 110 . In the top view direction of the substrate 100 , one end of the branch line segment 204 opposite to the main line segment 202 and the electrical connection between the second vertical signal line 110 and the horizontal signal line GL (eg, the conduction structure CS) may be separated by a distance D4 , so that the The main line segment 202 and the second longitudinal signal line 110 on the same extension line are electrically separated from each other, and transmit different signals respectively. The distance D4 between the main line segment 202 and the second longitudinal signal line 110 is, for example, smaller than the longitudinal length Wy of one pixel structure PX. For example, the distance D4 is about 3 μm˜5 μm, as long as the distance D4 can prevent the signals of the main line segment 202 and the second vertical signal line 110 from interfering with each other, the invention is not limited thereto.

Thereby, the same first vertical signal line DL experiences, for example, a low-level voltage Vgl at the branch line segment 204 adjacent to the constant-voltage line 200, and, for example, experiences a high-level voltage Vgh near the second vertical signal line 110, In this way, the range in which the first vertical signal line DL feels the high-level voltage Vgh can be reduced, the coupling effect between the first vertical signal line DL and the second vertical signal line 110 can be avoided, and the first vertical signal line 110 can be ensured. DL maintains a certain level of output voltage, thereby improving the quality of the pixel array.

3A is a schematic top view of a pixel array according to a third embodiment of the present invention; FIG. 3B is a schematic cross-sectional view of the pixel array in FIG. 3A along the line AA'; A schematic top view of another pixel array of the embodiment. For convenience of description, the position of the insulating layer and part of the pixel structure PX are omitted in FIGS. 3A and 4 . It must be noted here that FIGS. 3A , 3B and 4 follow the element numbers and part of the content of the embodiment in FIG. 2 , wherein the same or similar numbers are used to represent the same or similar elements, and the same technical content is omitted. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIGS. 3A and 4 , the difference between the pixel array 30A and the pixel array 30B of the third embodiment compared with the pixel array 20 of the second embodiment is that each second vertical signal line 310 includes a horizontal pattern 314 . That is to say, the conduction structures CS in the pixel array 10 and the pixel array 20 of the foregoing embodiment are scattered and distributed in an overall view. In contrast to this, the conduction structures CS in the pixel array 30A and the pixel array 30B of the third embodiment are The structures CS are not randomly arranged, but are generally arranged in a straight line. In this embodiment, the horizontal pattern 314 of each second vertical signal line 310 can span the same number of pixel structures PX. For example, as shown in FIGS. 3A and 4 , the horizontal pattern 314 of each second vertical signal line 310 spans a width equivalent to three pixel structures PX. In other words, as shown in FIG. 3B , the horizontal pattern 314 of the second vertical signal line 310 can span the three first vertical signal lines DL, but the invention is not limited thereto. In other embodiments, the horizontal pattern 314 of each second vertical signal line 310 can also span a different number of pixel structures PX, and the pixel structure spanned by the horizontal pattern 314 of the second vertical signal line 310 can be adjusted according to design requirements The number of PX.

In some embodiments, the first longitudinal pattern 312 of each second longitudinal signal line 310 may span a pixel structure PX in the longitudinal direction Y, and the second longitudinal pattern 316 may span b pixels in the longitudinal direction Y Structure PX, where a, b are positive integers. In other words, in the active area AA of the substrate 100, the length La of the first longitudinal pattern 312 in the longitudinal direction Y may be greater than or equal to the sum of the longitudinal lengths Wy of a pixel structures PX, and the length La of the second longitudinal pattern 316 in the longitudinal direction Y The length Lb above may be greater than or equal to the sum of the longitudinal lengths Wy of the b pixel structures PX.

In some embodiments, the lengths La of the first longitudinal patterns 312 of each of the second longitudinal signal lines 310 in the longitudinal direction Y may be different from each other, but the invention is not limited thereto. In other embodiments, the lengths La of the first longitudinal patterns 312 of each second longitudinal signal line 310 in the longitudinal direction Y can also be the same as each other, and the lengths of the first longitudinal patterns 312 in the longitudinal direction Y can be adjusted according to design requirements La.

In some embodiments, lengths Lb of the second longitudinal patterns 316 in the longitudinal direction Y may be the same as each other. In some embodiments, the length Lb of the second longitudinal pattern 316 in the longitudinal direction Y may be smaller than the length La of the first longitudinal pattern 312 in the longitudinal direction Y. Since the second vertical pattern 316 of the second vertical signal line 310 is connected to the conduction structure CS, when a signal is written to the pixel structure PX adjacent to the conduction structure CS, the second vertical signal line 310 and the first vertical signal line DL are prone to The coupling effect generated between them affects the gate/drain capacitance of the pixel structure. Therefore, the length Lb of the second vertical pattern 316 is smaller than the length La of the first vertical pattern 312, which can further avoid the second vertical signal line 310 and the first vertical signal line 310. A coupling effect occurs between the lines DL. For example, as shown in FIG. 4 , the second longitudinal pattern 316 of each second longitudinal signal line 310 may span one pixel structure PX in the longitudinal direction Y, that is, b may be 1, in other words, the second longitudinal The length Lb of the pattern 316 in the longitudinal direction Y may be equivalent to the longitudinal length Wy of one pixel structure PX, but the invention is not limited thereto. Taking the second vertical signal line 310-2 in the figure as an example, the second vertical signal line 310-2 turns on the pixel structure PX of the pixel row R1 in the figure through the conduction structure CS2 at a predetermined timing, and the turned on pixel row R1 The pixel structures PX are respectively input with corresponding signals through the corresponding first vertical signal lines DL7. At this time, the length Lb of the second vertical pattern 316 of the pixel structure PX is shorter because it is close to the pixel row R1 where the signal is being written. , so that the signal of the second vertical pattern 316 has a limited influence on the signal coupling of the adjacent first vertical signal line DL7, so it can effectively reduce the coupling effect between the second vertical signal line 310-2 and the first vertical signal line DL7. The display screen is abnormal.

In this way, because each second vertical signal line 310 includes the horizontal pattern 314, the length of the second vertical signal line 310 in the second vertical pattern 316 can be reduced, and the second vertical signal line 310 and the first vertical signal can be avoided. A coupling effect occurs between lines DL, which reduces gate/drain capacitance. In addition, even if the brightness of the plurality of pixel structures PX is abnormal due to the coupling effect of the first vertical signal line DL and the second vertical signal line 110 , the brightness change amount is not obvious, so the human eye is still not easily aware of the brightness caused by the first vertical signal line DL. Abnormal display images caused by the coupling effect of a vertical signal line DL and the second vertical signal line 110 .

FIG. 5 is a partial top plan view of a pixel array according to a fourth embodiment of the present invention. For the convenience of description, the position of the insulating layer is omitted in FIG. 5 . It must be noted here that FIG. 5 uses the element numbers and part of the content of the embodiment in FIG. 1A , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIG. 5 , the difference between the pixel array 40 of the fourth embodiment and the pixel array 10 of the first embodiment is that the pixel array 40 further has an insulating layer covering the first vertical signal line DL and the second vertical signal line 110 , and the insulating layer has a trench TR. In this embodiment, the common electrode COM may cover the surface of the trench TR. Therefore, it can be used for shielding the interference between the second vertical signal line 110 and the first vertical signal line DL, so as to reduce the adverse effect caused by the coupling between the lines. For example, the common electrode COM covers the surface of the trench TR and the trench TR is located between the second longitudinal signal line 110 and the first longitudinal signal line DL, so that the electric field generated by the second longitudinal signal line 110 is shielded, It will not be coupled to the first vertical signal line DL, so as to ensure that the first vertical signal line DL maintains an output voltage of a certain level, thereby improving the quality of the pixel array (eg, screen display, etc.).

In this embodiment, the trench TR extends along the second longitudinal pattern 116 of the first longitudinal signal line DL and the second longitudinal signal line 110 . Moreover, the projection of the trench TR on the substrate 100 is, for example, located between the projection of the second longitudinal pattern 116 of the second longitudinal signal line 110 on the substrate 100 and the projection of the first longitudinal signal line DL on the substrate 100 . For example, the sidewalls of the trench TR are separated from the sidewalls of the second longitudinal pattern 116 of the second longitudinal signal lines 110 and the side surfaces of the first longitudinal signal lines DL by a distance, for example, and the lower limit of the distance is preferably 2.0 μm , more preferably 3.0 μm. In addition, the upper limit of the distance is preferably 6.0 μm, more preferably 5.0 μm. In some embodiments, the trenches TR may be separated from the second longitudinal pattern 116 of the second longitudinal signal line 110 and the first longitudinal signal line DL by about 2.0 μm˜6.0 μm, respectively. It should be noted that, the implementation form of the trench can be adjusted according to design requirements, and the present invention is not limited thereto.

For example, taking the embodiment of FIG. 1B as an example, the trench TR may be located in the second insulating layer I2. In some embodiments, the depth of the trench TR may be equivalent to the film thickness of the second insulating layer I2. In some embodiments, the trench TR may extend from the second insulating layer I2 into the first insulating layer I1. For example, the depth of the trench TR may be larger than the film thickness of the second insulating layer I2 and smaller than the film thickness of the first insulating layer I1. In other embodiments, the depth of the trench TR may be smaller than the film thickness of the second insulating layer I2. In addition, in some embodiments, the second insulating layer I2 may include an upper insulating layer and a lower insulating layer (not shown), and the depth of the trench TR may be equivalent to the film thickness of the upper insulating layer. In some embodiments, the trench TR may extend from the upper insulating layer into the lower insulating layer. For example, the depth of the trench TR may be larger than the film thickness of the upper insulating layer and smaller than the film thickness of the lower insulating layer. In other embodiments, the depth of the trench TR may be smaller than the film thickness of the upper insulating layer.

To sum up, in the pixel array of the present invention, one of the second vertical signal lines includes a horizontal pattern, so that the second vertical signal lines can be appropriately segmented in the vertical direction, so as to reduce the number of the second vertical signal lines adjacent to the The length of the electrical connection of the horizontal signal line can reduce the coupling effect between the second vertical signal line and the adjacent first vertical signal line, which helps to improve the pixel while meeting the requirements of narrow frame design. the quality of the array.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 20, 30A, 30B, 40: pixel array 100: Substrate 110, 110-1～110-4, 110-p, 310, 310-1～310-3: Second vertical signal line 112, 112-1, 112-3, 312, 312-1: first longitudinal pattern 114, 114-1, 114-3, 314, 314-1: Horizontal pattern 116, 116-1, 116-3, 316, 316-1: Second longitudinal pattern 120, 120-1: The first transfer structure 122, 122-1: The second switching structure 200: constant voltage line 202: main line segment 204: Branch segment AA: Active area BA: Surrounding area C1, Cm: pixel row CS, CS1 to CS4, CSp: On structure D1～D4: Length DL, DL1, DL2, DL7, DL13, DLm+1: The first vertical signal line GD, GD1, GD2, GDp: Gate drive pads GL, GL1, GL2, GLn: Horizontal signal lines I1: first insulating layer I2: Second insulating layer L, La, Lb: length M1: first conductor layer M2: second conductor layer PX, PX11, PX12, PX1n, PXmn: pixel structure R1, Rn: pixel column TR: groove V1: first through hole V2: second via Vgl: low level voltage Vgh: high level voltage Wx: horizontal width Wy: Vertical length X: landscape orientation Y: portrait orientation

FIG. 1A is a schematic top view of a pixel array according to a first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view along the line A-A' of the pixel array of Fig. 1A. FIG. 2 is a schematic top view of a pixel array according to a second embodiment of the present invention. 3A is a schematic top view of a pixel array according to a third embodiment of the present invention. Fig. 3B is a schematic cross-sectional view along the line A-A' of the pixel array of Fig. 3A. FIG. 4 is a schematic top view of another pixel array according to the third embodiment of the present invention. FIG. 5 is a partial top plan view of a pixel array according to a fourth embodiment of the present invention.

10: Pixel array

100: Substrate

110, 110-1~110-4, 110-p: The second vertical signal line

112, 112-1, 112-3: first longitudinal pattern

114, 114-1, 114-3: Horizontal pattern

116, 116-1, 116-3: Second longitudinal pattern

120, 120-1: The first transfer structure

122, 122-1: The second switching structure

AA: Active area

BA: Surrounding area

C1, Cm: pixel row

CS, CS1~CS4, CSp: conduction structure

DL, DL1, DL2, DL7, DL13, DLm+1: The first vertical signal line

GD, GD1, GD2, GDp: Gate drive pads

GL, GL1, GL2, GLn: Horizontal signal lines

L: length

PX, PX11, PX12, PX1n, PXmn: pixel structure

R1, Rn: pixel column

Wx: horizontal width

Wy: Vertical length

X: landscape orientation

Y: portrait orientation

Claims (13)

A pixel array that includes: a substrate having an active area and a peripheral area outside the active area; a plurality of horizontal signal lines arranged in the active area; a plurality of first vertical signal lines extending from the peripheral region into the active region and intersecting with the horizontal signal lines; a plurality of second vertical signal lines electrically connected to one of the plurality of horizontal signal lines and adjacent to at least one of the first vertical signal lines, and one of the plurality of second vertical signal lines which includes a lateral pattern, wherein the lateral pattern is adjacent to the other of the plurality of lateral signal lines; and a plurality of pixel structures disposed in the active region and electrically connected to the horizontal signal line and the first vertical signal line, one of the plurality of pixel structures being adjacent to two of the The horizontal signal line is surrounded by two adjacent first vertical signal lines. The pixel array of claim 1, wherein a length of the lateral pattern is greater than or equal to a lateral width of one of the plurality of pixel structures. The pixel array of claim 1, wherein at least one of the plurality of second vertical signal lines includes the horizontal pattern, and at least one of the plurality of second vertical signal lines does not include the horizontal pattern pattern. The pixel array of claim 1, wherein each of the plurality of second vertical signal lines includes the horizontal pattern. The pixel array according to claim 3 or claim 4, wherein the second vertical signal line comprising the horizontal pattern further comprises a first vertical pattern and a second vertical pattern, the first vertical pattern and the The second longitudinal patterns are respectively adjacent to both ends of the transverse patterns, and are respectively adjacent to the two first longitudinal signal lines, The first longitudinal pattern, the transverse pattern and the second longitudinal pattern are electrically connected in sequence. The pixel array of claim 5, wherein the first longitudinal pattern and the second longitudinal pattern are located in the same film layer, and the film layer where the transverse pattern is located is different from the first longitudinal pattern and the second longitudinal pattern. the film layer where the second longitudinal pattern is located. The pixel array according to claim 6, further comprising: a first transfer structure disposed in the active area, and in a top view of the pixel array, the first transfer structure is disposed at the intersection of the first vertical pattern and the horizontal pattern; and The second transfer structure is disposed in the active area, and in the top view of the pixel array, the second transfer structure is disposed at the intersection of the second vertical pattern and the horizontal pattern, The first vertical pattern is connected to the horizontal pattern through the first transfer structure, and the horizontal pattern is connected to the second vertical pattern through the second transfer structure. The pixel array according to claim 5, wherein the length of the first longitudinal pattern in the longitudinal direction is greater than or equal to a of the pixel structures, and the length of the second longitudinal pattern in the longitudinal direction is greater than or equal to a or equal to b of the pixel structures, wherein a and b are positive integers. The pixel array of claim 8, wherein b is one. The pixel array as claimed in claim 1, further comprising: A plurality of gate driving pads are arranged in sequence in the peripheral region, and each of the gate driving pads is electrically connected to the corresponding second vertical signal line respectively. The pixel array as claimed in claim 1, further comprising: a constant voltage line, disposed in the peripheral area, and having a main line segment and a branch line segment, wherein the main line segment is parallel to the horizontal signal line, and the branch line segment extends from the main line segment along the plurality of first longitudinal signals one of the lines extends and spans c of the pixel structures, c being a positive integer, In the top view of the pixel array, one end of the branch line segment relative to the main line segment is separated from the electrical connection between the second vertical signal line and the horizontal signal line by a distance, and the distance is smaller than the the longitudinal length of one of the plurality of pixel structures. The pixel array of claim 11, wherein the distance is 3 μm to 5 μm. The pixel array of claim 1, further comprising, an insulating layer covering the first vertical signal line and the second vertical signal line, the insulating layer has a groove, wherein the groove is along the first vertical signal line and the second vertical signal line extending, and the projection of the groove on the substrate is located between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate.

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