TWI697709B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes signal lines, pixel structures, a driving element, a first fan-out trace and a second fan-out trace. The first fan-out includes a first segment connected to the driving element, a second segment connected to the first segment and a third segment connected to the second segment. Sheet resistance of the first segment of the first fan-out trace and sheet resistance of the third segment of the first fan-out trace are smaller than sheet resistance of the second segment of the first fan-out trace. The second fan-out includes a first segment connected to the driving element and a second segment connected to the first segment of the second fan-out trace. The first segment of the second fan-out trace is disposed correspondingly to the first segment of the first fan-out trace. The second segment of the second fan-out trace is disposed correspondingly to the second segment and the third segment of the first fan-out trace. Sheet resistance of the second segment of the second fan-out trace is less than sheet resistance of the first segment of the second fan-out trace.

Description

Pixel array substrate

The present invention relates to a pixel array substrate, and in particular to a pixel array substrate of a display panel.

With the development and popularization of display technology, consumers not only require display panels with specifications such as high resolution, high contrast, high color saturation, and wide viewing angles, but also the aesthetic appearance of the display panels. For example, consumers want to be able to display panels with narrow or no borders. Generally speaking, the multiple signal lines provided in the active area of the display panel need to be electrically connected to the driving elements of the display panel through multiple fan-out traces provided in the frame area (or peripheral area) of the display panel. When the resolution of the display panel is high, there are a large number of signal lines, and the large number of signal lines need to be electrically connected to the driving components of the display panel through a large number of fan-out traces. However, when the number of fan-out wires is large, it is not easy to reduce the width of the frame of the display panel.

The present invention provides a pixel array substrate whose peripheral area has a narrow width.

A pixel array substrate of the present invention includes a base, multiple signal lines, multiple pixel structures, driving elements, and multiple fan-out wiring lines. A plurality of signal lines are arranged on the substrate. The multiple pixel structures are electrically connected to multiple signal lines. The driving element is arranged on the substrate. Each of the plurality of fan-out wires is electrically connected to one of the plurality of signal wires and the driving element. The multiple fan-out wirings include a first fan-out wiring and a second fan-out wiring. The first fan-out wiring includes a first section connected to the driving element, a second section connected to the first section, and a third section connected to the second section. The sheet resistance of the first section of the first fan-out wiring and the sheet resistance of the third section of the first fan-out wiring are smaller than the sheet resistance of the second section of the first fan-out wiring. The second fan-out wiring includes a first section connected to the driving element and a second section connected to the first section of the second fan-out wiring. The first segment of the second fan-out wiring corresponds to the first segment of the first fan-out wiring. The second section of the second fan-out wiring is set corresponding to the second and third sections of the first fan-out wiring. The sheet resistance of the second section of the second fan-out wiring is smaller than the sheet resistance of the first section of the second fan-out wiring.

In an embodiment of the present invention, each of the aforementioned at least one first fan-out wiring further includes a switching structure. The transfer structure includes a first conductive pattern, a second conductive pattern, a first insulating layer, a second insulating layer, and a bridge pattern. The first conductive pattern is directly connected to the second section of the first fan-out wiring. The second conductive pattern is directly connected to the third section of the first fan-out wiring. The first insulating layer is disposed between the first conductive pattern and the second conductive pattern. The second insulating layer is disposed on the second conductive pattern and has at least one contact window. The bridge pattern is disposed on the second insulating layer, and is electrically connected to the first conductive pattern and the second conductive pattern through at least one contact window of the second insulating layer.

In an embodiment of the present invention, the above-mentioned first insulating layer has a contact window, the edge of the contact window of the first insulating layer and a part of the edge of the second conductive pattern and the edge of at least one contact window of the second insulating layer One part is substantially aligned.

In an embodiment of the present invention, the above-mentioned multiple signal lines are arranged in a first direction, at least one first fan-out wiring includes multiple first fan-out wirings, and a plurality of transitions for the multiple first fan-out wirings The structures are arranged in the second direction, and the first direction is perpendicular to the second direction.

In an embodiment of the present invention, the above-mentioned multiple signal lines are arranged in a first direction, at least one first fan-out wiring includes multiple first fan-out wirings, and a plurality of transitions for the multiple first fan-out wirings The structures are arranged in the third direction, where the first direction is staggered and not perpendicular to the third direction.

In an embodiment of the present invention, the above-mentioned at least one first fan-out wiring includes a plurality of first fan-out wirings, each of the plurality of first fan-out wirings includes a plurality of transition structures, and the plurality of pseudo-straight lines pass through a plurality of turns. In the connection structure, each of the plurality of pseudo straight lines passes through two adjacent transition structures of the plurality of transition structures, and the plurality of pseudo straight lines are connected to form a pseudo polyline.

In an embodiment of the present invention, the aforementioned at least one first fan-out wiring includes a plurality of first fan-out wirings, each of the plurality of first fan-out wirings includes a plurality of switching structures, and at least one second fan-out wiring includes Multiple second fan-out wirings, multiple second segments of multiple second fan-out wirings each have multiple bends, and multiple bends of multiple second fan-out wirings respectively correspond to multiple first fan-out wirings Of multiple transfer structure settings.

In an embodiment of the present invention, a vertical projection of the second section of each of the above-mentioned at least one first fan-out trace on the substrate and a second section of each of the at least one second fan-out trace on the substrate The vertical projection has a first pitch S1, a vertical projection of the third section of each of at least one first fan-out trace on the substrate and a vertical projection of the second section of each of at least one second fan-out trace on the substrate There is a second spacing S2, and S1<S2.

In an embodiment of the present invention, a part of the second segment of each of the at least one first fan-out trace has a line width W1, and a part of the second segment of each of the at least one second fan-out trace has a line Width W2, and W2>W1.

。 In an embodiment of the present invention, the first section of each of the at least one first fan-out wiring has a length L1, the second section of each of the at least one first fan-out wiring has a length L2, and at least one The third section of each fan-out trace has a length of L3, and

.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable range of deviation from the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meaning in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention. 2 is an enlarged schematic diagram of a part R1 of a pixel array substrate according to an embodiment of the invention. 3 is an enlarged schematic diagram of a part R2 of a pixel array substrate according to an embodiment of the invention. 4 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the invention. Figure 4 corresponds to the section line І-1' of Figure 2. 5 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the invention. Figure 5 corresponds to the section line П-П' of Figure 3. 6 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the invention. Figure 6 corresponds to the section line Ш-Ш' of Figure 2.

Please refer to FIG. 1, the pixel array substrate 100 includes a base 110. The base 110 is mainly used to carry the elements of the pixel array substrate 100. For example, in this embodiment, the material of the substrate 110 can be glass, quartz, organic polymer, or opaque/reflective material (for example, conductive material, wafer, ceramic, or other applicable materials) , Or other applicable materials.

The pixel array substrate 100 further includes a plurality of signal lines SL1 disposed on the base 110, a plurality of signal lines SL2 disposed on the base 110, and a plurality of pixel structures PX disposed on the base 110. The pixel structure PX may include an active device T and a pixel electrode 164 electrically connected to the active device T. For example, in this embodiment, the active device T includes a thin film transistor, the thin film transistor has a source S, a gate G, and a drain D, and the pixel electrode 164 is electrically connected to the drain D of the thin film transistor. . The multiple signal lines SL1 are arranged in the direction d1, and the multiple signal lines SL2 are arranged in the direction d2, where the direction d1 and the direction d2 are intersected. For example, in this embodiment, the direction d1 and the direction d2 can be selectively perpendicular, but the invention is not limited thereto. The pixel structures PX are electrically connected to the signal lines SL1 and the signal lines SL2. For example, in this embodiment, the source S of the active device T of the pixel structure PX is electrically connected to the signal line SL1, and the gate G of the active device T of the pixel structure PX is electrically connected to the signal line SL2 . That is, in this embodiment, the signal line SL1 can be a data line, and the signal line SL2 can be a scan line, but the invention is not limited to this.

The pixel array substrate 100 further includes a driving element 170 disposed on the base 110. For example, in this embodiment, the driving element 170 may include an integrated circuit (IC), but the invention is not limited thereto. In this embodiment, the driving element 170 has a central axis 170X, the base 110 has a central axis 110X, the extension direction of the central axis 170X (for example, but not limited to: direction d2) and the extension direction of the central axis 110X (for example, but not limited to : The direction d2) is staggered with the arrangement direction d1 of the multiple signal lines SL1. It is worth noting that in this embodiment, in the direction d1, the central axis 170X of the driving element 170 and the central axis 110X of the substrate 110 have a distance K. That is, in this embodiment, the central axis 170X of the driving element 170 is deviated from the central axis 110X of the substrate 110, but the invention is not limited to this.

The pixel array substrate 100 further includes a plurality of fan-out wiring lines FL1 and FL2, which are disposed on the base 110. Specifically, in this embodiment, the multiple vertical projections of the multiple fan-out traces FL1 and FL2 on the substrate 110 may be located on the multiple vertical projections of the multiple pixel structures PX on the substrate 110 and the multiple vertical projections of the driving element 170 on the substrate 110 110 between a vertical projection. Each of the plurality of fan-out wiring lines FL1 and FL2 is electrically connected to one of the plurality of signal lines SL1 and SL2 and the driving element 170. In the embodiment of FIG. 1, each of the plurality of fan-out traces FL1 and FL2 is electrically connected to a corresponding signal line SL1 as an example. However, the present invention is not limited to this. In another embodiment, a plurality of fan-out traces FL1 and FL2 can also be electrically connected to a plurality of signal lines SL1 and a plurality of signal lines SL2; in another embodiment, a plurality of fan-out wires Each of the outgoing traces FL1 and FL2 can also be electrically connected to a corresponding signal line SL2.

Referring to FIGS. 1, 2 and 3, the plurality of fan-out traces FL1 and FL2 of the pixel array substrate 100 include a first fan-out trace FL1. In this embodiment, a first fan-out wiring FL1 includes a first segment 141, a switching structure TS1, a second segment 122, a switching structure TS2, and a first segment 141 sequentially arranged from the driving element 170 to a corresponding signal line SL1. Three paragraphs 144. The driving element 170 is connected to the first section 141. The first section 141 is connected to the switching structure TS1. The switching structure TS1 is connected to the second section 122. The second section 122 is connected to the switching structure TS2. The switching structure TS2 is connected to the third section 144. The third segment 144 is connected to a corresponding signal line SL1.

In this embodiment, the sheet resistance of the first section 141 of the first fan-out wiring FL1 and the sheet resistance of the third section 144 of the first fan-out wiring FL1 may be substantially the same. In this embodiment, the first segment 141 of the first fan-out trace FL1 and the third segment 144 of the first fan-out trace FL1 can be selectively formed on the same conductive layer, such as but not limited to: the second metal layer. For example, in this embodiment, the material of the first segment 141 of the first fan-out trace FL1 and the material of the third segment 144 of the first fan-out trace FL1 may be molybdenum (Mo), and the sheet resistance of molybdenum is about 0.47 Ω/□. However, the present invention is not limited to this. The first section 141 of the first fan-out wiring FL1 and the third section 144 of the first fan-out wiring FL1 can also be made of other suitable conductive materials.

In this embodiment, the sheet resistance of the first section 141 of the first fan-out wiring FL1 and the sheet resistance of the third section 144 of the first fan-out wiring FL1 are smaller than the sheet resistance of the second section 122 of the first fan-out wiring FL1 . For example, in this embodiment, the material of the second section 122 of the first fan-out trace FL1 may be a stacked structure of titanium, aluminum, and titanium (Ti/Al/Ti), and the material of the stacked layer of titanium, aluminum and titanium The sheet resistance is about 0.1 Ω/□. However, the present invention is not limited to this, and the second section 122 of the first fan-out wiring FL1 can also be made of other suitable conductive materials. In addition, in this embodiment, the second section 122 of the first fan-out wiring FL1 is formed in the first metal layer, for example; that is, the second section 122 of the first fan-out wiring FL1 is connected to the first fan-out wiring FL1. A first insulating layer 130 (shown in Figure 4) is provided between the first section 141 of the first fan-out line, and a first section 122 is provided between the second section 122 of the first fan-out wiring FL1 and the third section 144 of the first fan-out wiring FL1. The insulating layer 130 (shown in FIG. 5); but the present invention is not limited to this.

。舉例而言，第一扇出走線FL1之第一段141的長度L1與第一扇出走線FL1之第二段122的長度L2實質上可相等，而第一扇出走線FL1之第三段144的長度L3遠大於第一扇出走線FL1之第一段141的長度L1及第一扇出走線FL1之第二段122的長度L2。 1, in this embodiment, the first section 141 of the first fan-out wiring FL1 has a length L1, the second section 122 of the first fan-out wiring FL1 has a length L2, and the third section of the first fan-out wiring FL1 has a length L2. Segment 144 has length L3, and

. For example, the length L1 of the first segment 141 of the first fan-out trace FL1 and the length L2 of the second segment 122 of the first fan-out trace FL1 may be substantially equal, and the third segment 144 of the first fan-out trace FL1 The length L3 is much larger than the length L1 of the first segment 141 of the first fan-out trace FL1 and the length L2 of the second segment 122 of the first fan-out trace FL1.

1, 2 and 4, in this embodiment, the transition structure TS1 of the first fan-out trace FL1 includes a conductive pattern 121, a first insulating layer 130, a conductive pattern 142, a second insulating layer 150, and bridges Pattern 161. The conductive pattern 142 is directly connected to the first segment 141 of the first fan-out wiring FL1. The conductive pattern 142 of the transit structure TS1 and the first segment 141 of the first fan-out trace FL1 may be formed on the same film layer. The conductive pattern 121 is directly connected to the second segment 122 of the first fan-out wiring FL1. The conductive pattern 121 of the transfer structure TS1 and the second segment 122 of the first fan-out trace FL1 may be formed on the same film layer. The first insulating layer 130 is disposed between the conductive pattern 121 and the conductive pattern 142. The second insulating layer 150 is disposed on the conductive pattern 142 and has at least one contact window 151a, 151b.

For example, in this embodiment, the second insulating layer 150 may selectively have a plurality of contact windows 151a and 151b separated from each other, which are respectively located on the conductive patterns 121 and 142. The bridging pattern 161 is disposed on the second insulating layer 150 and is electrically connected to the conductive pattern 121 and the conductive pattern 142 through at least one contact window 151 a, 151 b of the second insulating layer 150. In this embodiment, the bridging pattern 161 is electrically connected to the conductive pattern 121 through the contact window 151a of the second insulating layer 150 and the contact window 131 of the first insulating layer 130, and the contact window 151a of the second insulating layer 150 is electrically connected to the conductive pattern 121. The contact window 131 of an insulating layer 130 can be substantially aligned, but the invention is not limited to this. On the other hand, the bridge pattern 161 is electrically connected to the conductive pattern 142 through the contact window 151b of the second insulating layer 150. In this embodiment, the bridge pattern 161 and the pixel electrode 164 can be selectively formed on the same film layer, but the invention is not limited to this.

1, 3 and 5, in this embodiment, the transition structure TS2 of the first fan-out trace FL1 includes a conductive pattern 123, a first insulating layer 130, a conductive pattern 143, a second insulating layer 150, and bridges Pattern 162. The conductive pattern 123 is directly connected to the second segment 122 of the first fan-out wiring FL1. The conductive pattern 123 of the transit structure TS2 and the second segment 122 of the first fan-out trace FL1 may be formed on the same film layer. The conductive pattern 143 is directly connected to the third segment 144 of the first fan-out wiring FL1. The conductive pattern 143 of the transit structure TS2 and the third segment 144 of the first fan-out trace FL1 may be formed on the same film layer. The first insulating layer 130 is disposed between the conductive pattern 123 and the conductive pattern 143. The second insulating layer 150 is disposed on the conductive pattern 143 and has at least one contact window 152a, 152b.

For example, in this embodiment, the second insulating layer 150 may selectively have a plurality of contact windows 152a and 152b separated from each other, which are respectively located on the conductive patterns 123 and 143. The bridge pattern 162 is disposed on the second insulating layer 150 and is electrically connected to the conductive pattern 123 and the conductive pattern 143 through at least one contact window 152a, 152b of the second insulating layer 150. In this embodiment, the bridging pattern 162 is electrically connected to the conductive pattern 123 through the contact window 152a of the second insulating layer 150 and the contact window 132 of the first insulating layer 130, wherein the contact window 152a of the second insulating layer 150 is electrically connected to the conductive pattern 123. The contact window 132 of an insulating layer 130 can be substantially aligned, but the present invention is not limited to this. On the other hand, the bridge pattern 162 is electrically connected to the conductive pattern 143 through the contact window 152b of the second insulating layer 150. In this embodiment, the bridge pattern 162 and the pixel electrode 164 can be selectively formed on the same film layer, but the invention is not limited to this.

Please refer to FIG. 1, FIG. 2 and FIG. 6, the plurality of fan-out traces FL1 and FL2 of the pixel array substrate 100 include a second fan-out trace FL2. In this embodiment, a second fan-out wiring FL2 includes a first segment 124, a switching structure TS3, and a second segment 146 that are sequentially arranged from the driving element 170 to the corresponding signal line SL1. The driving element 170 is connected to the first section 124. The first section 124 is connected to the switching structure TS3. The switching structure TS3 is connected to the second section 146. The second segment 146 is connected to another corresponding signal line SL1. The sheet resistance of the second section 146 of the second fan-out wiring FL2 is smaller than the sheet resistance of the first section 124 of the second fan-out wiring FL2.

Please refer to FIG. 1, the first segment 124 of the second fan-out wiring FL2 is arranged corresponding to the first segment 141 of the first fan-out wiring FL1. The second section 146 of the second fan-out wiring FL2 is arranged corresponding to the second section 122 and the third section 144 of the first fan-out wiring FL1. For example, in this embodiment, the first segment 124 of the second fan-out trace FL2 and the first segment 141 of the first fan-out trace FL1 may be formed on two different film layers (for example, but not limited to: the first metal Layer and the second metal layer), and the second segment 146 of the second fan-out trace FL2 and the second segment 122 of the first fan-out trace FL1 can be formed on two different film layers (for example, but not limited to: the second metal layer And the first metal layer). Thereby, a part of the first fan-out wiring FL1 (for example: the first section 141/the second section 122) and a part of the second fan-out wiring FL2 (for example: the first section 124/the second section 146) are arranged corresponding to each other It can be densely arranged near the driving elements 170, thereby reducing the width W of the boarder of the pixel array substrate 100. Furthermore, in this embodiment, the longer part of the first fan-out wiring FL1 (that is, the third section 144) and the longer part of the second fan-out wiring FL2 (that is the second section 146) have a lower length. Therefore, the impedance of the first and second fan-out traces FL1 and FL2 can be greatly increased and the problem of insufficient charging of the pixel structure PX can be avoided.

In addition, in this embodiment, the first distance S1 between the first fan-out wiring FL1 and the second fan-out wiring FL2 near the driving element 170 may be smaller than the first fan-out wiring FL1 and the second fan-out wiring FL2 when they are far away from the driving element. The second spacing S2 at the element 170. For example, the first spacing S1 may refer to the spacing between the vertical projection of the second segment 122 of the first fan-out trace FL1 on the substrate 110 and the vertical projection of the second segment 146 of the second fan-out trace FL2 on the substrate 110. The second spacing S2 may refer to the spacing between the vertical projection of the third segment 144 of the first fan-out trace FL1 on the substrate 110 and the vertical projection of the second segment 146 of the second fan-out trace FL2 on the substrate 110.

1, 2 and 6, in this embodiment, the transition structure TS3 of the second fan-out trace FL2 includes a conductive pattern 125, a first insulating layer 130, a conductive pattern 145, a second insulating layer 150, and bridges Pattern 163. The conductive pattern 125 is directly connected to the first segment 124 of the second fan-out wiring FL2. The conductive pattern 125 of the transit structure TS3 and the first segment 124 of the second fan-out trace FL2 may be formed on the same film layer. The conductive pattern 145 is directly connected to the second segment 146 of the second fan-out wiring FL2. The conductive pattern 145 of the transit structure TS3 and the second segment 146 of the second fan-out wiring FL2 may be formed on the same film layer. The first insulating layer 130 is disposed between the conductive pattern 125 and the conductive pattern 145. The second insulating layer 150 is disposed on the conductive pattern 145 and has at least one contact window 153a, 153b.

For example, in this embodiment, the second insulating layer 150 may selectively have a plurality of contact windows 153a, 153b separated from each other, which are located on the conductive patterns 125, 145, respectively. The bridging pattern 163 is disposed on the second insulating layer 150 and is electrically connected to the conductive pattern 125 and the conductive pattern 145 through at least one contact window 153 a, 153 b of the second insulating layer 150. In this embodiment, the bridge pattern 163 is electrically connected to the conductive pattern 125 through the contact window 153a of the second insulating layer 150 and the contact window 133 of the first insulating layer 130, wherein the contact window 153a of the second insulating layer 150 and the The contact window 133 of an insulating layer 130 can be substantially aligned, but the invention is not limited to this. On the other hand, the bridge pattern 163 is electrically connected to the conductive pattern 145 through the contact window 153b of the second insulating layer 150. In this embodiment, the bridge pattern 163 and the pixel electrode 164 can be selectively formed on the same film layer, but the invention is not limited to this.

1 and 3, in this embodiment, the multiple signal lines SL1 are arranged in the direction d1, and the multiple switching structures TS2 of the multiple first fan-out wirings FL1 are arranged in the third direction d3, where the direction d1 is staggered and not perpendicular to direction d3. That is to say, in this embodiment, the arrangement of the multiple switching structures TS2 may be stepped. However, the present invention is not limited to this. According to other embodiments, the arrangement of the plurality of switching structures TS2 may also be in other suitable forms, as illustrated below with other illustrations.

FIG. 7 is an enlarged schematic diagram of a part R3 of a pixel array substrate according to another embodiment of the present invention. In the embodiment of FIG. 7, the plurality of switching structures TS2 of the plurality of first fan-out traces FL1 can be selectively arranged in the second direction d2, and the second direction d2 can be perpendicular to the first direction d1. In other words, in this embodiment, the arrangement of the multiple switching structures TS2 may be vertical.

FIG. 8 is an enlarged schematic diagram of a part R4 of a pixel array substrate according to another embodiment of the present invention. In the embodiment of FIG. 8, the plurality of first fan-out traces FL1 respectively include a plurality of switching structures TS2, a plurality of pseudo straight lines A pass through a plurality of switching structures TS2, and each pseudo straight line A passes through two adjacent transfer structures. Connect structure TS2, and multiple pseudo straight lines A can be connected to form pseudo broken lines Z. That is to say, in this embodiment, the arrangement of multiple switching structures TS2 may be staggered.

In addition, in the embodiment of FIG. 8, the plurality of second segments 146 of the plurality of second fan-out traces FL2 may respectively have a plurality of curved portions 146a, and the plurality of curved portions 146a may respectively correspond to the plurality of first fan-out traces The multiple switching structures TS2 of FL1 are set up. Thereby, the first fan-out wiring FL1 and the second fan-out wiring FL2 can be arranged more densely, thereby reducing the width of the frame of the pixel array substrate (not shown).

9 is a schematic cross-sectional view of a pixel array substrate according to another embodiment of the invention. Figure 9 corresponds to the section line IV-IV' of Figure 8. The switching structure TS2 in FIG. 9 is slightly different from the switching structure TS2 in FIG. 5. Specifically, in the embodiment of FIG. 9, the edge 132a of the contact window 132 of the first insulating layer 130 and a part 143a of the edge of the conductive pattern 143 and a part 152a of the edge of the contact window 152 of the second insulating layer 150 are substantially Chopped. That is, in the embodiment of FIG. 9, the bridge pattern 162 is electrically connected to the conductive pattern 123 and the conductive pattern 143 through the same contact window 152. Thereby, the area of the transfer structure TS2 can be reduced, which helps to reduce the width of the frame of the pixel array substrate (not shown).

The design of the switching structure TS2 with the same contact window 152 in FIG. 9 can be applied to the switching structures TS1, TS2, and/or TS3 of any of the foregoing embodiments. Those with ordinary knowledge in the art should be able to achieve this according to the foregoing description. , Here will not be illustrated and detailed one by one.

In addition, in this embodiment, a part of the second section 122 of the first fan-out wiring FL1 close to the driving element 170 (shown in FIG. 1) has a line width W1, and the second section 146 of the second fan-out wiring FL2 A part far away from the driving element 170 has a line width W2, and W2>W1. A part of the second segment 122 of the first fan-out trace FL1 with a line width W1 and a part of the second segment 146 of the second fan-out trace FL2 with a line width W2 are respectively located in the transition structure TS2 of the first fan-out trace FL1 On both sides.

Make the line width W1 of the part of the second segment 122 of the first fan-out trace FL1 close to the driving element 170 (shown in FIG. 1) small, which helps to provide more fan-out traces near the driving element 170 FL1, FL2; the line width W2 of the second segment 146 of the second fan-out wiring FL2 away from the driving element 170 is large, which helps to reduce its impedance and improve the electrical properties of the pixel array substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: Pixel array substrate 110: Base 110X, 170X: central axis 121, 123, 125, 142, 143, 146: conductive pattern 122, 146: second paragraph 124, 141: first paragraph 130: The first insulating layer 131, 132, 133, 151a, 151b, 152, 152a, 152b, 153a, 153b: contact window 132a: Edge 143a, 152a: partial 144: Third paragraph 146a: Curved part 150: second insulating layer 161, 162, 163: bridge pattern 164: Pixel electrode 170: drive components A: Quasi-straight line D: Dip pole d1, d2, d3: direction FL1, FL2: fan-out routing G: Gate K: distance L1, L2, L3: length PX: Pixel structure R1～R4: Partial S: Source S1, S2: Spacing SL1, SL2: signal line T: Active component TS1, TS2, TS3: transfer structure W: width W1, W2: line width Z: pseudo-broken line І-Ι’, П-П’, Ш-Ш’, Ⅳ-Ⅳ’: Sectional line

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention. 2 is an enlarged schematic diagram of a part R1 of a pixel array substrate according to an embodiment of the invention. 3 is an enlarged schematic diagram of a part R2 of a pixel array substrate according to an embodiment of the invention. 4 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the invention. 5 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the invention. 6 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the invention. FIG. 7 is an enlarged schematic diagram of a part R3 of a pixel array substrate according to another embodiment of the present invention. FIG. 8 is an enlarged schematic diagram of a part R4 of a pixel array substrate according to another embodiment of the present invention. 9 is a schematic cross-sectional view of a pixel array substrate according to another embodiment of the invention.

100: Pixel array substrate 110: Base 110X, 170X: central axis 122, 146: second paragraph 124, 141: first paragraph 144: Third paragraph 164: Pixel electrode 170: drive components D: Dip pole d1, d2, d3: direction FL1, FL2: fan-out routing G: Gate K: distance L1, L2, L3: length PX: Pixel structure R1, R2: partial S: Source S1, S2: Spacing SL1, SL2: signal line T: Active component TS1, TS2, TS3: transfer structure W: width

Claims (10)

A pixel array substrate includes: a substrate; a plurality of signal lines arranged on the substrate; a plurality of pixel structures electrically connected to the signal lines; a driving element arranged on the substrate; and a plurality of pixel structures Fan-out wiring, wherein each of the fan-out wiring is electrically connected to one of the signal lines and the driving element; wherein, the fan-out wiring includes at least one first fan-out wiring and at least one second fan-out wiring Line; each of the at least one first fan-out wiring includes: a first segment connected to the driving element; a first transition structure, wherein the first segment is connected to the first transition structure; a second Section, wherein the first transition structure is connected to the second section; a second transition structure, wherein the second section is connected to the second transition structure; and a third section, wherein the second transition structure Connected to the third segment, wherein the sheet resistance of the first segment of each of the at least one first fan-out trace and the sheet resistance of the third segment of each of the at least one first fan-out trace are less than The sheet resistance of the second segment of each of the at least one first fan-out trace; each of the at least one second fan-out trace includes: A first segment connected to the driving element and corresponding to the first segment of each of at least one first fan-out trace; and a second segment connected to the at least one second fan-out trace The first section of each one, and the second section and the third section of each of the at least one first fan-out wiring are arranged, wherein the first section of each of the at least one second fan-out wiring The sheet resistance of the two sections is smaller than the sheet resistance of the first section of each of the at least one second fan-out trace. The pixel array substrate according to claim 1, wherein the second transition structure includes: a first conductive pattern directly connected to the second section of each of the at least one first fan-out trace A second conductive pattern directly connected to the third section of each of the at least one first fan-out trace; a first insulating layer disposed between the first conductive pattern and the second conductive pattern; A second insulating layer is disposed on the second conductive pattern and has at least one contact window; and a bridge pattern is disposed on the second insulating layer and passes through the at least one contact window of the second insulating layer. And electrically connected to the first conductive pattern and the second conductive pattern. The pixel array substrate according to claim 2, wherein the first insulating layer has a contact window, and an edge of the contact window of the first insulating layer is connected to the A part of an edge of the second conductive pattern and a part of an edge of the at least one contact window of the second insulating layer are substantially aligned. According to the pixel array substrate described in claim 2, wherein the signal lines are arranged in a first direction, the at least one first fan-out wiring includes a plurality of first fan-out wirings, and the first fan-out wirings A plurality of second transition structures out of the wiring are arranged in a second direction, and the first direction is perpendicular to the second direction. The pixel array substrate according to claim 2, wherein the signal lines are arranged in a first direction, the at least one first fan-out wiring includes a plurality of first fan-out wirings, and the first fan-out wirings The plurality of second switching structures out of the wiring are arranged in a third direction, wherein the first direction and the third direction are staggered and not perpendicular to each other. According to the pixel array substrate described in claim 2, wherein the at least one first fan-out wiring includes a plurality of first fan-out wirings, and each of the first fan-out wirings includes a plurality of second transition structures, A plurality of pseudo straight lines pass through the second transition structures, each of the pseudo straight lines passes through two adjacent second transition structures of the second transition structures, and the pseudo straight lines are connected to form a pseudo broken line. According to the pixel array substrate described in claim 2, wherein the at least one first fan-out wiring includes a plurality of first fan-out wirings, and each of the first fan-out wirings includes a plurality of second transition structures, The at least one second fan-out trace includes a plurality of second fan-out traces, a plurality of second segments of the second fan-out traces respectively have a plurality of curved portions, and the curved portions of the second fan-out traces Don't set the second transition structure corresponding to the first fan-out wiring. The pixel array substrate according to claim 1, wherein a vertical projection of the second segment of each of the at least one first fan-out trace on the substrate is between a vertical projection of the at least one second fan-out trace A vertical projection of the second section of each line on the substrate has a first spacing S1, a vertical projection of the third section of each of the at least one first fan-out trace on the substrate and the at least one A vertical projection of the second segment of each of the second fan-out traces on the substrate has a second spacing S2, and S1<S2. A pixel array substrate includes: a substrate; a plurality of signal lines arranged on the substrate; a plurality of pixel structures electrically connected to the signal lines; a driving element arranged on the substrate; and a plurality of pixel structures Fan-out wiring, wherein each of the fan-out wiring is electrically connected to one of the signal lines and the driving element; wherein, the fan-out wiring includes at least one first fan-out wiring and at least one second fan-out wiring Line; each of the at least one first fan-out wiring includes: a first section connected to the driving element; a second section connected to the first section; and a third section connected to the second section , Wherein the sheet resistance of the first section of each of the at least one first fan-out trace and the sheet resistance of the third section of each of the at least one first fan-out trace are smaller than the sheet resistance of the at least one first fan Run away The sheet resistance of the second segment of each of the lines; each of the at least one second fan-out trace includes: a first segment connected to the driving element and corresponding to the at least one first fan-out trace The first section of each one is provided; and a second section is connected to the first section of each of the at least one second fan-out wiring, and corresponds to the each of the at least one first fan-out wiring The second segment and the third segment are arranged, wherein the sheet resistance of the second segment of each of the at least one second fan-out trace is smaller than the first segment of the each of the at least one second fan-out trace , Wherein a portion of the second section of each of the at least one first fan-out trace has a line width W1, and a portion of the second section of each of the at least one second fan-out trace has a line Width W2, and W2>W1. According to the pixel array substrate described in claim 1 or 9, wherein the first segment of each of the at least one first fan-out trace has a length L1, and the at least one first fan-out trace has a length L1 The second section of each one has a length L2, the third section of each of the at least one first fan-out trace has a length L3, and

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