TW202208956A - Electronic device - Google Patents

Abstract

An electronic device includes a substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel structures, a gate transfer line and a transfer structure. A plurality of pixel structures arranged in the same column are electrically connected to the data lines on different sides in sequence. The film layer of the gate transfer line is the same as that of the data line. The gate transfer line passes between the pixel structure and the data line to form a cross-line region on the substrate. The film layer of the transfer structure is located different from that of the gate transfer line and the data line. In the cross-line region, one of the gate transfer line and the data line crosses the other of the gate transfer line and the data line through the transfer structure or the active component of the pixel structure.

Description

electronic device

The present invention relates to an electronic device, and more particularly, to an electronic device with a switching structure.

With the advancement of science and technology, large-size panels are mostly developed towards the design of narrow bezels. At present, TGP (Tracking Gate-line in Pixel) narrow border technology is mostly used to further reduce the width of the panel border.

However, TGP needs to bypass the active components of the pixel, and is usually designed for traces with multiple turns. This increases the resistance-capacitance loading (RC loading) of the panel by 1.5 to 2 times, and is prone to coupling with adjacent data lines or generating gate-drain capacitance (Cgd), etc. problems, which further affects the quality of signal transmission in the electronic device. For example, the display effect of the display panel or the sensitivity of the touch panel may be affected. Therefore, how to plan the circuit layout, reduce the coupling effect between the circuits, and avoid the increase of the resistance and capacitance load has become a topic of concern to the current research and development personnel.

The present invention provides an electronic device, the design of which can help reduce the resistance-capacitance load, avoid the coupling between lines, and improve the quality of the electronic device.

At least one embodiment of the present invention provides an electronic device including a substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel structures, a gate switching wire, and a switching structure. The plurality of gate lines are disposed on the substrate and extend along the first direction. The plurality of data lines are disposed on the substrate and extend along the second direction, wherein the first direction and the second direction intersect. A plurality of pixel structure arrays are arranged on the substrate. Each pixel structure is surrounded by adjacent two of the plurality of gate lines and adjacent two of the plurality of data lines and includes an active element, wherein the plurality of pixel structures arranged in the same row along the second direction are in sequence with the Data lines on different sides are electrically connected. The gate transfer wire is disposed on the substrate and extends along the second direction. The gate transfer wire is electrically connected to one of the plurality of gate wires, the film layer where the gate transfer wire is located is the same as the film layer of the plurality of data wires, and in the top view of the electronic device, the gate transfer wire is A cross-line area is formed on the substrate through one of the plurality of pixel structures and a data line electrically connected to the pixel structure. The transfer structure is disposed on the substrate, and the film layer where the transfer structure is located is different from the film layer where the gate transfer line and the data line are located. In the cross-line region, one of the gate transition line and the data line crosses the other of the gate transition line and the data line through the active element of the transition structure or the pixel structure.

In an embodiment of the present invention, in the above-mentioned cross-line area, the data line crosses the gate jumper line through a transfer structure, the transfer structure extends along the first direction, and two ends of the transfer structure are respectively connected to the data line and the gate jumper line. The active element of the pixel structure, and in the top view of the electronic device, the switching structure intersects the gate switching line.

In an embodiment of the present invention, the active element of the pixel structure further includes a vertical wire, wherein the vertical wire is disposed on the substrate, and both ends of the vertical wire are connected to the switching structure and the active element, and in the top view of the electronic device, The gate transfer wire is located between the data wire and the longitudinal wire.

In an embodiment of the present invention, the electronic device further includes a first insulating layer, wherein the first insulating layer covers the gate line and has a first through hole and a second through hole. In the top view of the electronic device, the first insulating layer The through hole overlaps with the data line, the second through hole overlaps with the vertical wire, wherein the first through hole and the second through hole respectively expose a part of the transfer structure, the data line is connected to the transfer structure through the first through hole, and the transfer The structure is connected to the longitudinal conductor through the second through hole.

In an embodiment of the present invention, the above-mentioned pixel structure further has a pixel electrode, and the pixel electrode and the data line are respectively electrically connected to the drain electrode and the source electrode on the opposite sides of the active device, and the top view of the electronic device is , the pixel electrode and the gate switching wire are separated by a distance.

In an embodiment of the present invention, the electronic device further includes a second insulating layer, the second insulating layer covers the data lines and the gate transition lines, and has a third through hole, wherein the third through hole exposes the active element. In a part, the pixel electrode covers a part of the surface of the third through hole, so as to be connected to the active element.

In an embodiment of the present invention, the second insulating layer includes a lower insulating layer and an upper insulating layer, the lower insulating layer is conformally disposed on the first insulating layer, and the upper insulating layer is disposed on the lower insulating layer.

In an embodiment of the present invention, the second insulating layer has a single-layer structure.

In an embodiment of the present invention, in the above-mentioned over-the-line area, the gate transfer line crosses the data line through a transfer structure, the transfer structure extends along the second direction, and both ends of the transfer structure are respectively connected to the gate switch wiring, and in the top view of the electronic device, the switching structure intersects the data line.

In an embodiment of the present invention, the data line has a main line segment and a branch line segment, the main line segment extends along the second direction, and two ends of the branch line segment are respectively connected to the main line segment and the active element of the pixel structure, and the top view of the electronic device is , the transition structure intersects the branch line segment.

In an embodiment of the present invention, the electronic device further includes a first insulating layer, the first insulating layer covers the gate lines, and has a plurality of fourth through holes. In the top view of the electronic device, the plurality of fourth through holes overlapping with the gate transfer wire, wherein the plurality of fourth through holes expose a part of the transfer structure, and the gate transfer wire at one end of the transfer structure is connected to the transfer through one of the plurality of fourth through holes The transfer structure is connected to the gate transfer wire at the other end of the transfer structure through the other one of the plurality of fourth through holes.

In an embodiment of the present invention, the electronic device further includes a common electrode, which is disposed on the substrate and overlaps with at least the data line, the gate transfer line and the transfer structure in a plan view of the electronic device.

In an embodiment of the present invention, the active element of the pixel structure is a top-gate thin film transistor and includes a semiconductor channel layer, and in the cross-line region, the data line crosses the gate through the transition structure and the semiconductor channel layer Adapter cable.

In an embodiment of the present invention, the semiconductor channel layer includes a first line segment, a curved line segment and a second line segment, the first line segment and the second line segment extend along the second direction, and both ends of the curved line segment are adjacent to the first line The segment and the second line segment, in the top view of the electronic device, the first line segment overlaps the data line, and the curved line segment intersects the gate transition line.

In an embodiment of the present invention, the gate line further includes an extension structure, the extension structure extends from the gate line along the second direction, and the gate transfer wire is electrically connected to the gate line through the extension structure. The length of the extension structure is 1/10 to 1/2 of the length of the pixel structure.

In an embodiment of the present invention, the electronic device further includes an interlayer dielectric layer sandwiched between the gate switching wire and the gate wire, and having a through hole, wherein the gate switching wire covers the surface of the through hole to connect to the extension structure.

In an embodiment of the present invention, the electronic device further includes a third insulating layer, the third insulating layer covers the data line and the gate transition line and has a trench. The trenches extend along the second direction, and in a top view of the electronic device, the trenches are located between the data lines and the gate transfer lines.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on," "connected to," "overlying" another element, it can be directly on the other element on or connected to another element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer," or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a" and "an" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprising" and/or "comprising" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but do not exclude one or more The presence or addition of other features, entireties of regions, steps, operations, elements, components, and/or combinations thereof.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" may include an orientation of "lower" and "upper", depending on the particular orientation of the figures. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "above" can encompass both an orientation of above and below.

As used herein, "about" includes the stated value and the average within an acceptable deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (ie, measurement system limitations). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about" as used herein may be used to select a more acceptable range of variation or standard deviation depending on optical properties, etching properties, or other properties, and not one standard deviation may apply to all properties.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances, are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions as shown herein, but rather include deviations in shapes resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and/or nonlinear features. Additionally, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

FIG. 1 is a schematic top view of an electronic device according to a first embodiment of the present invention. For the convenience of description, the position of the insulating layer is omitted in FIG. 1 .

Referring to FIG. 1 , the electronic device 10 includes a substrate 100 , a plurality of gate lines GL, a plurality of data lines DL, a plurality of pixel structures SP, and a gate switching line 110 . The substrate 100 may have an active area AA and a peripheral area (not shown) located outside the active area AA. In this embodiment, the material of the substrate 100 may include glass or other suitable materials, but the invention is not limited thereto. The gate line GL is disposed on the substrate 100 and extends along the first direction D1. The data line DL is disposed on the substrate 100 and extends along a second direction D2 intersecting with the first direction D1.

A plurality of pixel structures SP arrays are arranged on the substrate 100 . In other words, the pixel structures SP can be arranged in an array along the first direction D1 and the second direction D2, wherein the first direction D1 can be understood as a lateral direction, and the second direction D2 can be understood as a vertical direction. Therefore, the lateral direction and the longitudinal direction described in the following embodiments can be regarded as the first direction D1 and the second direction D2 in FIG. 1 , respectively. In this embodiment, each pixel structure SP is surrounded by two adjacent gate lines GL and two adjacent data lines DL. For example, the pixel structures SP arranged in a row along the first direction D1 are sandwiched between two gate lines GL; the pixel structures SP arranged in a row along the second direction D2 are sandwiched between two data lines DL . Therefore, the pixel structure SP in the same column and the pixel structure SP in the same row described in the following embodiments can be regarded as the pixel structure SP arranged along the first direction D1 and the pixel structure SP arranged along the second direction D2 in FIG. 1 , respectively. .

Each pixel structure SP may include an active element T1 and a pixel electrode PE connected to the active element T1 , wherein the active element T1 is electrically connected to the corresponding gate line GL and the data line DL. In this embodiment, the pixel structures SP arranged in the same row along the second direction D2 can be electrically connected to the data lines DL on different sides in sequence. For example, the active elements T1 of the pixel structure SP in the same row can be electrically connected to the data line DL1 on the first side (the right side in FIG. 1 ) and the second side opposite (the left side in FIG. 1 ) in a staggered manner. The data line DL2. In some embodiments, in the pixel structures SP arranged in multiple columns along the first direction D1, the active elements T1 of the pixel structures SP of the odd-numbered columns can be electrically connected to the data line DL1 located on the first side thereof, and the active elements T1 of the pixel structures SP of the odd-numbered columns can be electrically connected to the data lines DL1 located on the first side thereof, The active element T1 of the pixel structure SP can be electrically connected to the data line DL2 on the second side thereof, but the invention is not limited thereto.

In some embodiments, the plurality of pixel structures SP may include a plurality of red sub-pixels R, a plurality of green sub-pixels G and a plurality of blue sub-pixels B respectively arranged along the second direction D2. For example, taking the data line DL1 marked in FIG. 1 as an example, when the data line DL1 is located between the blue sub-pixel B and the red sub-pixel R in the same row, the data line DL1 can be alternately electrically connected. are connected to the blue sub-pixel B and the red sub-pixel R; taking the data line DL2 marked in FIG. 1 as an example, the data line DL2 is located between the green sub-pixel G and the blue sub-pixel B in the same row. In this case, the data line DL2 can be alternately electrically connected to the green sub-pixel G and the blue sub-pixel B. Those skilled in the art can adjust the arrangement of the data line DL and the pixel structure SP according to the design requirements. and the connection relationship, the present invention is not limited to this.

In this embodiment, the pixel electrodes PE and the data lines DL can be electrically connected to the drain electrodes and the source electrodes on opposite sides of the active layer of the active device T1, respectively. For example, the active device T1 can be a transistor with a gate, a source and a drain, the gate can be connected to one of the gate lines GL, the source can be connected to one of the data lines DL, and the drain can be connected to to the pixel electrode PE. In addition, in order to avoid short circuit between the gate line GL and the data line DL, the gate line GL and the data line DL may be formed of different film layers, and one or more insulating layers may be sandwiched between the gate line GL and the data line DL.

The gate transfer line 110 is disposed on the substrate 100 and extends along the second direction D2. In this embodiment, the gate transfer line 110 may be parallel to the data line DL. For example, the gate transition line 110 and the data line DL may be linear patterns parallel to each other, or may have zigzag patterns parallel to each other, but the invention is not limited thereto. In FIG. 1 , the gate switching wire 110 is, for example, located between the data line DL1 and the pixel structure SP adjacent to the dotted frame, and the gate switching wire 110 is not directly connected to the pixel structure SP. In the plan view direction of the substrate 100 , the gate transition line 110 directly spans the connection path between the active element T1 of the pixel structure SP and the data line DL1 . In some embodiments, the pixel electrode PE may not overlap with the gate transition line 110 in the plan view direction of the substrate 100 . For example, the pixel electrode PE is separated from the gate transition wire 110 by a distance, but the invention is not limited to this. In other embodiments, the pixel electrode PE may also overlap with the gate transition line 110 .

The gate transfer line 110 and the data line DL may be located in the same film layer. In this embodiment, the gate transfer wire 110 can be electrically connected to one of the gate wires GL, and the film layer where the gate wire GL is located can be located in a different film layer from the gate transfer wire 110 and the data line DL middle. The active element T1 can be connected to the gate transfer line 110 through one of the gate lines GL. Accordingly, the signal of the gate electrode of the active element T1 can be transmitted to the gate electrode line GL through the gate electrode transfer line 110, and then input to the gate electrode through the gate electrode line GL. In some embodiments, in order to transmit the signal from the gate transfer line 110 to the gate line GL, a conduction structure (eg, the place marked as a dotted frame) may be provided between the corresponding gate transfer line 110 and the gate line GL. the turn-on structure CS). In this way, the signal of the gate of the active element T1 can be transmitted to the gate line GL through the gate transition line 110 through the conduction structure CS, and then transmitted to the gate through the gate line GL.

In some embodiments, the signal of the gate of the active element T1 is, for example, a signal output from a driving circuit (not shown) located in the peripheral region. In some embodiments, the driving circuit may be located at one end of the gate transfer line 110 and the data line DL. The gate transfer line 110 and the data line DL can directly receive the signal provided by the driving circuit, and the gate line GL can receive the signal corresponding to the gate transfer line 110 through the corresponding conduction structure CS. In this way, the electronic device 10 does not need to provide signal transmission lines or related circuits at both ends of the first direction D1 to meet the requirements of narrow frame design, and the outline of the electronic device 10 does not need to be limited. For example, the electronic device 10 may have a non-rectangular outline when viewed in a plan direction of the substrate 100 . In some embodiments, the electronic device 10 may further include other vertical signal lines (not shown), and the vertical signal lines may not be used to transmit the signals required by the gate line GL, but are input with a DC potential. For example, the vertical signal line may not be connected to any gate line GL, and is used for the realization of touch or other functions.

In FIG. 1 , the gate transition line 110 can pass between one of the pixel structures SP and the data line DL1 electrically connected to the pixel structure SP to form a cross-line region CR on the substrate 100 . More specifically, in the cross-line region CR, the electronic device 10 further includes a transition structure (which will be described in detail later) disposed on the substrate 100 , wherein the film layer where the transition structure is located is different from the gate transition line 110 and the film layer where the data line DL1 is located, so that in the cross-line region CR, one of the gate transfer line 110 and the data line DL1 can cross the gate through the active element T1 of the transfer structure or the pixel structure SP The other one of the transfer line 110 and the data line DL1, thereby, through the transfer structure in the cross-line region CR, the number of turning points of the signal traces can be reduced, and the increase of the resistance and capacitance load can be avoided, resulting in the occurrence of gaps between the lines. The problems such as adverse effects caused by the coupling of the electronic device can be improved, and the functions performed by the electronic device (such as screen display, touch sensing, etc.) are improved, but the present invention is not limited to this. In other embodiments, the type of the switching structure can also be adjusted according to different design or process requirements, which will be described in detail later.

Hereinafter, embodiments applicable to the transition structure in the above-mentioned embodiments will be exemplified, but the present invention is not limited to the following embodiments.

2A is an enlarged schematic view of the cross-line region CR of an embodiment in the electronic device of FIG. 1; FIG. 2B is a schematic view of an embodiment of the cross-section along the section line A'-A-B-C in the electronic device of FIG. 2A; 2A is a schematic diagram of another embodiment of the cross-section along the line A'-A-B-C in the electronic device. FIG. 2A corresponds to the cross-line region CR of FIG. 1 . It must be noted here that FIGS. 2A to 2C use the element numbers and part of the content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Please refer to FIG. 2A and FIG. 2B at the same time, the data line DL1 in the electronic device 10A can be connected to the active element T1 through the switching structure 120 across the gate switching wire 110 . In this embodiment, the transition structure 120 extends, for example, along the first direction D1, and two ends of the transition structure 120 are respectively connected to the data line DL1 and the active element T1 of the pixel structure SP. In this way, the transition structure 120 and the gate transition line 110 have intersections in the plan view direction of the substrate 100 to form the cross-line region CR described in FIG. 1 . For example, the film layer where the switching structure 120 is located in this embodiment is the same as the film layer where the gate line GL is located. The material of the switching structure 120 can be the same as that of the gate line GL, but the invention is not limited thereto.

In this embodiment, the active element T1 of the pixel structure SP may further have a vertical wire 130 . The vertical wires 130 are disposed on the substrate 100 , and two ends of the vertical wires 130 can be respectively connected to the switching structure 120 and the active element T1 of the pixel structure SP. In the plan view direction of the substrate 100 , the gate transition line 110 is, for example, located between the data line DL1 and the vertical wire 130 .

In order to clearly illustrate the film layer relationship of each component in the electronic device, the description is made with reference to FIG. 2A and FIG. 2B together. 2A and FIG. 2B at the same time, the active element T1 includes, for example, a gate electrode GE, a semiconductor pattern CH (as a channel layer), a source electrode SE and a drain electrode DE. In this embodiment, the active element T1 is illustrated as a bottom gate structure, but the present invention is not limited to this. The gate GE of the active element T1 can be electrically connected to a corresponding gate line GL, and the gate line GL can be electrically connected to a corresponding gate transfer wire 110 through the conduction structure CS. The gate electrode GE and the gate electrode line GL belong to the same film layer, for example. The semiconductor pattern CH is provided above the gate electrode GE, for example. The source electrode SE and the drain electrode DE are disposed above the semiconductor pattern CH, for example. In this embodiment, the vertical wire 130 can be regarded as an extension of the source electrode SE, but the invention is not limited to this. In this embodiment, the gate line GL and the transition structure 120 are located in the first conductor layer M1, for example, and the data line DL1 and the gate transition line 110 are located in the second conductor layer M2, for example, but the invention is not limited thereto. In addition, a first insulating layer 140 may also be included between the first conductor layer M1 and the second conductor layer M2. The first insulating layer 140 can cover the gate line GL and the transfer structure 120, and has a first through hole VIA1 and a second through hole VIA2. As shown in FIG. 2A , the first through hole VIA1 overlaps with the data line DL1 , the second through hole VIA2 overlaps with the vertical wire 130 serving as an extension of the source SE, wherein the first through hole VIA1 and the second through hole VIA2 are exposed respectively. A portion of the transit structure 120 . In this way, the data line DL1 located in the second conductor layer M2 can be connected to the via structure 120 of the first conductor layer M1 below through the conductor structure penetrating the first via VIA1, and the via structure 120 located in the first conductor layer M1 The conductor structure passing through the second through hole VIA2 can be connected to the vertical wires 130 of the second conductor layer M2 above. Thereby, the signal of the data line DL1 of the second conductor layer M2 can be transmitted to the vertical wire 130 of the second conductor layer M2 and the source electrode SE of the active element T1 of the pixel structure SP through the transition structure 120 of the first conductor layer M1 . Accordingly, even if the data line DL1 and the gate transition line 110 are located in the same film layer, the data line DL1 can cross the gate transition line 110 through the transition structure 120 in the cross-line region CR, which can reduce the The number of turning points in the routing design of the gate adapter line 110 can avoid problems such as increased resistance and capacitance loads and adverse effects caused by coupling between lines, thereby improving the functions performed by the electronic device.

As shown in FIG. 2B , the electronic device 10A1 of this embodiment may further include a second insulating layer 150 . The second insulating layer 150 covers, for example, the data line DL1 , the gate transition line 110 , the vertical wire 130 and the active element T1 of the pixel structure SP. In this embodiment, the second insulating layer 150 may have a third through hole VIA3, the third through hole VIA3 may expose a part of the active element T1, and the pixel electrode PE may cover a part of the surface of the third through hole VIA3 for connection to the active element T1.

The second insulating layer 150 may have a single-layer or multi-layer structure. For example, as shown in FIG. 2B , the second insulating layer 150 includes, for example, a lower insulating layer 152 and an upper insulating layer 154 , wherein the lower insulating layer 152 may be conformally disposed on the first insulating layer 140 , and the upper insulating layer 154 may be is disposed on the lower insulating layer 152 . In some embodiments, the lower insulating layer 152 can be used as a passivation layer, and the upper insulating layer 154 can be used as a flat layer, but the invention is not limited thereto.

On the other hand, compared to the double-layer structure of the second insulating layer 150 of the electronic device 10A1 of FIG. 2B , the second insulating layer 150' of the electronic device 10A2 of FIG. 2C is exemplified as a single-layer structure. The second insulating layer 150' may be an oxide layer, and the material of the second insulating layer 150' may use the same material as the lower insulating layer 152 in FIG. 2B , but the present invention is not limited thereto.

Referring to FIGS. 2A and 2B , the electronic device 10 may further include a common electrode COM. For example, the common electrode COM is disposed on the active area AA of the substrate 100 , and in the top view direction of the substrate 100 , the common electrode COM is at least connected to the active area of the data line DL1 , the gate transfer line 110 , the transfer structure 120 and the pixel structure SP. Element T1 overlaps. In some embodiments, the common electrode COM may be a common electrode used for connecting to a panel or implementing a touch function. In some embodiments, when the electronic device further has a touch signal line (TP trace; not shown), the common electrode COM may also have a plurality of them, and a gap exists between the plurality of common electrodes COM to expose the touch signal line. The control signal line can be applied to the realization of touch or other functions. For example, the touch signal line can be used as the center between the plurality of common electrodes COM to be spaced by about 2.0 μm˜8.0 μm.

The electronic device 10 may further include a third insulating layer 160 . The third insulating layer 160 covers the common electrode COM and the second insulating layer 150 . In some embodiments, the third insulating layer 160 is sandwiched between the common electrode COM and the pixel electrode PE to separate the common electrode COM and the pixel electrode PE. In some embodiments, the third insulating layer 160 may be a passivation layer, but the invention is not limited thereto.

3A is an enlarged schematic view of the cross-line region CR in another embodiment of the electronic device of FIG. 1 ; FIG. 3B is a schematic cross-sectional view of the electronic device of FIG. 3A along the section line A-A'. FIG. 3A corresponds to the cross-line region CR of FIG. 1 . It must be noted here that FIGS. 3A and 3B use the element numbers and part of the content of the embodiment of FIG. 2A , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Different from the above-mentioned cross-line area CR of the electronic device 10A in FIG. 2A, the switching structure 120 extending along the first direction D1 is used as a relay station for the signal transmission of the data line DL1. The cross-line area CR of the electronic device 10B of this embodiment is The switching structure 200 extending along the second direction D2 is used as a relay station for the signal transmission of the gate switching wire 110 . Referring to FIG. 3A , in the electronic device 10B of the present embodiment, the gate switching line 110 can cross the data line DL1 through the switching structure 200 . In this embodiment, the transition structure 200 extends along the second direction D2, and two ends of the transition structure 200 are respectively connected to the gate transition wires 110 . In this way, in the plan view direction of the substrate 100 , the transition structure 200 and the data line DL1 have an intersection, which constitutes the aforementioned cross-line region CR.

In this embodiment, the data line DL1 may include a main line segment DLa and a branch line segment DLb. The main line segment DLa extends along the second direction D2 and is located between two adjacent rows of pixel structures SP; the branch line segment DLb extends from the main line segment DLa along the first direction D1 and the second direction D2, and the two ends of the branch line segment DLb are respectively connected To the main line segment DLa and the active element T1 of the pixel structure SP. For example, in the plan view direction of the substrate 100 , the branch line segment DLb spans the transition structure 200 . That is, the branch line segment DLb and the transition structure 200 have an intersection, and the gate transition line 110 crosses the branch line segment DLb of the data line DL1 through the transition structure 200 .

3A and 3B at the same time, in this embodiment, the transition structure 200 is located in the first conductor layer M1, for example, the main line segment DLa, the branch line segment DLb and the gate transition line 110 are located in the second conductor layer M2, for example. In this way, the signal of the data line DL1 can be transmitted in the second conductor layer M2, and the gate transfer line 110 can transmit the signal to the first conductor layer M1 through the transfer structure 200 at the intersection with the data line DL1, and then to the second conductor layer M1. The second conductor layer M2 crosses the data line DL1.

Referring to FIG. 3B for a cross-sectional view of the transfer structure 200 , the first insulating layer 140 covers the gate line GL and has a plurality of fourth through holes VIA4 . As shown in FIG. 3A , the plurality of fourth through holes VIA4 overlap with the gate transfer wires 110 and expose a part of the transfer structure 200 . In this way, the gate transfer wire 110 at one end of the transfer structure 200 can be connected to the transfer structure 200 through one of the conductor structures penetrating the fourth through hole VIA4, so that the signal of the gate transfer wire 110 can be transmitted from the second through hole VIA4 to the transfer structure 200. The conductor layer M2 is jumped to the first conductor layer M1. In addition, the switching structure 200 can be connected to the gate switching wire 110 located at the other end of the switching structure 200 through another conductor structure penetrating the fourth through hole VIA4, so that the signal of the gate switching wire 110 can be transmitted from the first A conductor layer M1 jumps to the second conductor layer M2. That is, both ends of the switching structure 200 can be connected to the gate switching wire 110 through the conductor structure passing through the fourth through hole VIA4. Therefore, the data line DL1 and the gate transfer line 110 can be located in the same film layer, and the signal of the gate transfer line 110 can be transmitted to the gate transfer line 110 at the other end through one end of the transfer structure 200 . In addition, the routing design of the gate adapter wire 110 can reduce the number of turning points, and can avoid problems such as increased resistance and capacitance loads and adverse effects caused by coupling between lines, thereby improving the functions performed by the electronic device.

FIG. 4A is a schematic top view of an electronic device according to a second embodiment of the present invention; FIG. 4B is an enlarged schematic view of the cross-line region CR in the electronic device of FIG. 4A . FIG. 4B corresponds to the cross-line region CR of FIG. 4A . It must be noted here that FIGS. 4A and 4B use the element numbers and part of the content of the embodiment of FIG. 2A , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here. For the convenience of description, the positions of the pixel electrodes are omitted in FIGS. 4A and 4B .

4A and 4B at the same time, the difference between the electronic device 20 of the second embodiment and the electronic device 10 of the first embodiment is that the active element T1 of the electronic device 10 is illustrated as a bottom gate structure, and the active element of the electronic device 20 is illustrated as a bottom gate structure. T2 is illustrated as a top gate structure, and the data line DL1 is connected to the semiconductor channel layer 310 of the active element T2 via the via structure 300 . For example, the active element T2 of the pixel structure SP may include the semiconductor channel layer 310 , and in the cross-line region CR, the data line DL1 may cross the gate transition line 110 through the transition structure 300 and the semiconductor channel layer 310 .

In this embodiment, the active element T2 of the pixel structure SP includes, for example, a semiconductor channel layer 310 , a data electrode (as a source electrode or a drain electrode) and a gate electrode. The semiconductor channel layer 310 is disposed on the substrate 100 . The gate insulating layer covers the semiconductor channel layer 310 , the gate is disposed on the gate insulating layer (eg, the gate insulating layer GI shown in FIG. 5B ), and in the top view direction of the substrate 100 , the gate overlaps with the semiconductor channel layer 310 . The interlayer dielectric layer covers the gate electrode and insulates the gate electrode and the data electrode from each other (eg, the interlayer dielectric layer ILD shown in FIG. 5B ). The data electrodes (source/drain) are electrically connected to the semiconductor channel layer 310 . For example, the gate of the active element T2 is electrically connected to a corresponding gate line GL, and the gate line GL can be connected to the gate transfer line 110 through the conduction structure CS.

In this embodiment, in order to transmit the signal from the data line DL1 to the semiconductor channel layer 310 , the transition structure 300 can be disposed between the corresponding data line DL1 and the semiconductor channel layer 310 . For example, the transfer structure 300 may penetrate through the interlayer dielectric layer and the gate insulating layer. That is to say, the layer where the transition structure 300 is located is between the layer where the data line DL1 is located and the layer where the semiconductor channel layer 310 is located.

More specifically, the semiconductor channel layer 310 may include a first line segment 312 , a curved line segment 314 and a second line segment 316 . The first line segment 312 and the second line segment 316 extend, for example, along the second direction D2 , and both ends of the curved line segment 314 It is adjacent to the first line segment 312 and the second line segment 316 . In this embodiment, the shape of the curved line segment 314 is, for example, a U shape, but the present invention is not limited to this. In other embodiments, the shape of the curved line segment 314 can also be adjusted according to design requirements. In the plan view direction of the substrate 100 , the first line segment 312 overlaps with the data line DL1 , for example, and the curved line segment 314 has an intersection with the gate transition line 110 . In addition, one end of the first line segment 312 opposite to the adjacent curved line segment 314 is connected to the transition structure 300 , and one end of the second line segment 316 opposite to the adjacent curved line segment 314 is connected to the active element T2 . In this way, the signal of the data line DL1 can be transmitted to the first line segment 312 through the transition structure 300 , and then transmitted to the active element T2 through the curved line segment 314 and the second line segment 316 in sequence. In this way, the data line DL1 and the gate transfer line 110 can be located in the same film layer, and the signal of the data line DL1 can cross the gate transfer line 110 through the transfer structure 300 to be transmitted to the active element T2 of the pixel structure SP . In addition, the routing design of the gate adapter wire 110 can reduce the number of turning points, and can avoid problems such as increased resistance and capacitance loads and adverse effects caused by coupling between lines, thereby improving the functions performed by the electronic device ( such as screen display, touch sensing, etc.).

Fig. 5A is a schematic top view of an electronic device according to a third embodiment of the present invention; Fig. 5B is a schematic cross-sectional view of the electronic device of Fig. 5A along the line A-A'. It must be noted here that FIGS. 5A and 5B follow the element numbers and part of the content of the embodiment in FIGS. 4A and 4B , wherein the same or similar numbers are used to represent the same or similar elements, and the same technical content is omitted. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here. For the convenience of description, the positions of the pixel electrodes are omitted in FIGS. 5A and 5B .

Referring to FIGS. 5A and 5B , compared with the electronic device 20 of FIG. 4A , the gate line GL of the electronic device 30 of the present embodiment further has an extension structure 320 extending along the second direction D2 , and the aforementioned conduction structure CS is arranged At one end of the extension structure 320 away from the gate line GL, that is, the gate transition line 110 can be connected to one end of the extension structure 320 through the conducting structure CS at the end away from the cross-line region CR, and the other end of the extension structure 320 is connected. One end is connected to the gate line GL. In this embodiment, the film layer where the extension structure 320 is located is the same as the film layer where the gate line GL is located. For example, as shown in FIG. 5B , the buffer layer 102 , the gate insulating layer GI, the interlayer dielectric layer ILD and the gate switching line 110 may be sequentially disposed on the substrate 100 , wherein the extension structure 320 and the gate line GL are, for example, They are both located on the side of the interlayer dielectric layer ILD close to the gate insulating layer GI, but the present invention is not limited thereto. As shown in FIG. 5A , the extension structure 320 extends from the gate line GL to the middle region of the pixel structure SP along the second direction D2 . For example, the length of the extension structure 320 may be about 1/10˜1/2 of the length of the pixel structure SP. In some embodiments, the length of the extension structure 320 may be equivalent to 1/2 of the length of the pixel structure SP, but the invention is not limited thereto.

In this embodiment, the gate transition line 110 can be electrically connected to the gate line GL through the extension structure 320 . For example, as shown in FIG. 5B , an interlayer dielectric layer ILD may be sandwiched between the gate transfer line 110 and the gate line GL, the interlayer dielectric layer ILD may have through holes TH, and the gate transfer line A part of 110 may cover the surface of the through hole TH to serve as the conduction structure CS, but the present invention is not limited thereto. Thereby, the gate transition line 110 can be connected to the extension structure 320 . In other words, the gate signal of the active element T2 can be sequentially transmitted to the extension structure 320 and the gate line GL through the gate transition line 110, and then input to the gate through the gate line GL. In this way, the position of the conduction structure CS can be set flexibly, and it is not necessary to set the conduction structure CS at the intersection of the gate transition line 110 and the gate line GL. In addition, the pattern of the extension structure 320 and the position where the gate adapter line 110 is connected to the extension structure 320 can be adjusted according to the consideration of the manufacturing process, thereby avoiding the loading effect caused by the short distance between the conducting structures of different lines or the conductor structures. effect) or the line width of the line is not uniform.

6 is a schematic top view of an electronic device according to a fourth embodiment of the present invention. It must be noted here that FIG. 6 uses the element numbers and part of the content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIG. 6 , the difference between the electronic device 40 of the fourth embodiment and the electronic device 10 of the first embodiment is that the electronic device 40 further has an insulating layer covering the data line DL and the gate switching line 110 , and the insulating layer Has groove TR.

In this embodiment, the trench TR extends along the gate transition line 110 and the data line DL. Moreover, the projection of the trench TR on the substrate 100 is located between the projection of the gate transition line 110 on the substrate 100 and the projection of the data line DL on the substrate 100 . For example, the sidewalls of the trenches TR are respectively separated from the sidewalls of the gate transition lines 110 and the data lines DL by a distance, and the lower limit of the distance is preferably 2.0 μm, more preferably 3.0 μm. In addition, the upper limit of the distance is preferably 6.0 μm, more preferably 5.0 μm. In some embodiments, the trenches TR may be separated from the gate transition lines 110 and the data lines DL by about 2 μm˜6 μm, respectively. It should be noted that, the implementation form of the trench can be adjusted according to design requirements, and the present invention is not limited thereto.

For example, taking the embodiment of FIG. 2B as an example, the trench TR may be located in the second insulating layer 150 . In some embodiments, the depth of the trench TR may be equivalent to the film thickness of the upper insulating layer 154 . In some embodiments, the trench TR may extend from the upper insulating layer 154 into the lower insulating layer 152 . For example, the depth of the trench TR may be larger than the film thickness of the upper insulating layer 154 and smaller than the film thickness of the lower insulating layer 152 . In other embodiments, the depth of the trench TR may be smaller than the film thickness of the upper insulating layer 154 . In addition, taking the embodiment of FIG. 2C as an example, the trench TR may be located in the second insulating layer 150'. In some embodiments, the depth of the trench TR may be equivalent to the film thickness of the second insulating layer 150'. In some embodiments, the trench TR may extend from the second insulating layer 150' into the first insulating layer 140. For example, the depth of the trench TR may be larger than the film thickness of the second insulating layer 150' and smaller than the film thickness of the first insulating layer 140. In other embodiments, the depth of the trench TR may be smaller than the film thickness of the second insulating layer 150'.

In some embodiments, the common electrode COM covers the surface of the trench TR. In this way, it can be used to shield the interference between the gate transfer line 110 and the data line DL, so as to reduce the adverse effect caused by the coupling between the lines. For example, the common electrode COM covers the surface of the trench TR and the trench TR is located between the gate transfer line 110 and the data line DL, so that the electric field generated by the gate transfer line 110 is shielded, and the electric field generated by the gate transfer line 110 is shielded without Coupling to the data line DL can ensure that the data line DL maintains a certain level of output voltage, thereby improving the functions performed by the electronic device (eg, screen display, touch sensing, etc.).

To sum up, the electronic device of the present invention can make one of the gate switching line and the data line cross the active element of the switching structure or the pixel structure in the cross-line area by disposing the switching structure. The other of the gate transfer line and the data line. In this way, problems such as increased resistance and capacitance loads and adverse effects caused by coupling between lines can be avoided, thereby improving the functions performed by the electronic device (eg, screen display, touch sensing, etc.).

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 10A, 10A1, 10A2, 10B, 20, 30, 40: Electronic devices 100: Substrate 102: Buffer layer 110: Gate transfer wiring 120, 200, 300: transfer structure 130: Longitudinal wire 140: first insulating layer 150, 150': the second insulating layer 152: Lower insulating layer 154: Upper insulating layer 160: The third insulating layer 310: Semiconductor channel layer 312: first line segment 314: Bend Line Segment 316: Second line segment 320: Extended Structure AA: Active area B: blue sub-pixel CH: semiconductor pattern COM: Common electrode CR: Cross-Line Area CS: Conduction structure D1: first direction D2: Second direction DE: drain DL, DL1, DL2: data lines DLa: main line segment DLb: branch line segment G: Green subpixel GE: gate GI: gate insulating layer GL: gate line ILD: Interlayer Dielectric Layer M1: first conductor layer M2: second conductor layer PE: pixel electrode R: red subpixel SE: source SP: pixel structure T1, T2: Active components TH: through hole TR: groove VIA1: first through hole VIA2: second via VIA3: third via VIA4: Fourth Via

FIG. 1 is a schematic top view of an electronic device according to a first embodiment of the present invention. FIG. 2A is an enlarged schematic diagram of a cross-line region CR in an embodiment of the electronic device of FIG. 1 . Figure 2B is a schematic diagram of one embodiment of a cross-section along the line A'-A-B-C in the electronic device of Figure 2A. FIG. 2C is a schematic diagram of another embodiment of a cross-section along the line A'-A-B-C in the electronic device of FIG. 2A. FIG. 3A is an enlarged schematic view of the cross-line region CR in another embodiment of the electronic device of FIG. 1 . FIG. 3B is a schematic cross-sectional view of the electronic device of FIG. 3A along the line A-A'. 4A is a schematic top view of an electronic device according to a second embodiment of the present invention. FIG. 4B is an enlarged schematic view of the cross-line region CR in the electronic device of FIG. 4A . 5A is a schematic top view of an electronic device according to a third embodiment of the present invention. Fig. 5B is a schematic cross-sectional view of the electronic device of Fig. 5A along the line A-A'. 6 is a schematic top view of an electronic device according to a fourth embodiment of the present invention.

10A: Electronic device

100: Substrate

110: Gate transfer wiring

120: transfer structure

130: Longitudinal wire

AA: Active area

COM: Common electrode

CS: Conduction structure

D1: first direction

D2: Second direction

DL1: data line

GL: gate line

PE: pixel electrode

SP: pixel structure

T1: Active element

VIA1: first through hole

VIA2: second via

Claims (17)

An electronic device, comprising: substrate; a plurality of gate lines, disposed on the substrate and extending along the first direction; a plurality of data lines disposed on the substrate and extending along a second direction, wherein the first direction intersects the second direction; a plurality of pixel structures arranged in an array on the substrate, each of the pixel structures is surrounded by two adjacent two of the plurality of gate lines and adjacent two of the plurality of data lines and includes an active a device, wherein the plurality of pixel structures arranged in the same row along the second direction are sequentially electrically connected to the data lines on different sides; a gate transfer line, disposed on the substrate and extending along the second direction, the gate transfer line is electrically connected to one of the plurality of gate lines, and the gate transfer line The film layer where the lines are located is the same as the film layer where the plurality of data lines are located, and in the top view of the electronic device, the gate switching line passes through one of the plurality of pixel structures and is related to all the pixel structures. The pixel structure is electrically connected between the data lines to form a jumper region on the substrate; and The transfer structure is disposed on the substrate, and the film layer where the transfer structure is located is different from the film layer where the gate transfer line and the data line are located. One of the gate switching line and the data line crosses the other of the gate switching line and the data line through the switching structure or the active element of the pixel structure. The electronic device of claim 1, wherein in the cross-line region, the data line crosses the gate jumper line through the transfer structure, The transfer structure extends along the first direction, two ends of the transfer structure are respectively connected to the data line and the active element of the pixel structure, and in the top view of the electronic device, all The transfer structure intersects with the gate transfer line. The electronic device according to claim 2, wherein the active element of the pixel structure further comprises: A vertical wire is arranged on the substrate, two ends of the vertical wire are connected to the switching structure and the active element, and in the top view of the electronic device, the gate switching wire is located on the data between the wire and the longitudinal wire. The electronic device according to claim 3, further comprising: A first insulating layer covers the gate line and has a first through hole and a second through hole. In a top view of the electronic device, the first through hole overlaps with the data line, and the second through hole overlaps with the data line. The through hole overlaps with the vertical wire, wherein the first through hole and the second through hole respectively expose a part of the transfer structure, and the data line is connected to the transfer structure through the first through hole The connecting structure is connected to the longitudinal wire through the second through hole. The electronic device according to claim 2, wherein the pixel structure further has a pixel electrode, and the pixel electrode and the data line are respectively electrically connected to the drain electrodes and the drain electrodes on opposite sides of the active element. source, and In a top view of the electronic device, the pixel electrodes are spaced apart from the gate transition wires by a distance. The electronic device according to claim 5, further comprising: A second insulating layer covers the data line and the gate transition line, and has a third through hole, wherein the third through hole exposes a part of the active element, and the pixel electrode covers the A part of the surface of the third through hole is connected to the active element. The electronic device of claim 6, wherein the second insulating layer includes a lower insulating layer and an upper insulating layer, the lower insulating layer is conformally disposed on the first insulating layer, and the upper insulating layer is configured on the lower insulating layer. The electronic device of claim 6, wherein the second insulating layer has a single-layer structure. The electronic device according to claim 1, wherein in the cross-line region, the gate switching line crosses the data line through the switching structure, The transfer structure extends along the second direction, two ends of the transfer structure are respectively connected to the gate transfer wire, and in the top view of the electronic device, the transfer structure and the data Lines intersect. The electronic device of claim 9, wherein the data line has a main line segment and a branch line segment, the main line segment extends along the second direction, and two ends of the branch line segment are respectively connected to the main line segment and the pixel The active element of the structure, and in the top view of the electronic device, the transfer structure intersects the branch line segment. The electronic device as claimed in claim 10, further comprising: The first insulating layer covers the gate line and has a plurality of fourth through holes. In the top view of the electronic device, the plurality of fourth through holes overlap with the gate transfer line, wherein the The plurality of fourth through holes expose a part of the transfer structure, and the gate transfer wire located at one end of the transfer structure is connected to the through one of the plurality of fourth through holes The transfer structure is connected to the gate transfer wire at the other end of the transfer structure through the other one of the plurality of fourth through holes. The electronic device according to claim 2 or claim 9, further comprising: The common electrode is disposed on the substrate and overlaps with at least the data line, the gate transfer line and the transfer structure in the top view of the electronic device. The electronic device of claim 1, wherein the active element of the pixel structure is a top-gate thin film transistor and includes a semiconductor channel layer, and in the cross-line region, the data line passes through the A transfer structure and the semiconductor channel layer span the gate transfer line. The electronic device of claim 13, wherein the semiconductor channel layer comprises a first line segment, a curved line segment and a second line segment, the first line segment and the second line segment extending along the second direction, the Both ends of the curved line segment are adjacent to the first line segment and the second line segment, In a top view of the electronic device, the first line segment overlaps the data line, and the curved line segment intersects the gate transition line. The electronic device of claim 13, wherein the gate line further comprises an extension structure, the extension structure extends from the gate line along the second direction, and the gate transition line is extended by the extension the structure is electrically connected to the gate line, The length of the extension structure is 1/10˜1/2 of the length of the pixel structure. The electronic device as claimed in claim 15, further comprising: an interlayer dielectric layer sandwiched between the gate transfer line and the gate line, and having a through hole, wherein the gate transfer line covers the surface of the through hole to connect to the extension structure. The electronic device according to claim 1, further comprising: A third insulating layer covering the data line and the gate transition line, the third insulating layer has a groove, the groove extending along the second direction, and in the top view of the electronic device , the trench is located between the data line and the gate transfer line.

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