CN113035066B - Electronic device with a detachable cover - Google Patents

Abstract

An electronic device comprises a substrate, a transverse signal line, a first longitudinal signal line, a second longitudinal signal line, a first insulating layer and a common electrode. The first longitudinal signal line intersects with the transverse signal lines and is connected with one of the transverse signal lines. The second longitudinal signal line is adjacent to and parallel to the first longitudinal signal line. The first insulating layer covers the first vertical signal line and the second vertical signal line. The first insulating layer is provided with a groove, wherein the groove extends along the first longitudinal signal line and the second longitudinal signal line, and the projection of the groove on the substrate is positioned between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate. The common electrode covers the first insulating layer and the surface of the groove.

Description

electronic device

technical field

The invention relates to an electronic device, and in particular to an electronic device with a groove.

Background technique

With the advancement of technology, large-size panels tend to develop in the form of narrow bezel design, and the layout of circuits in various electronic devices is becoming more and more complicated. The coupling between many adjacent lines used to transmit different types of signals often affects the quality of signal transmission, resulting in unexpected functions. Therefore, how to plan the circuit layout, reduce the width of the border, reduce the demand for low-resistance metals, and avoid insufficient charging due to increased resistance-capacitance loading (RC loading) has become the focus of current R&D personnel. issue.

Contents of the invention

The invention provides an electronic device, the design of which can help to realize the requirement of narrow frame design, and can reduce the coupling between lines to improve the quality of the electronic device.

At least one embodiment of the present invention provides an electronic device, including a substrate, a plurality of horizontal signal lines, a first vertical signal line, a second vertical signal line, a first insulating layer, and a common electrode. A plurality of horizontal signal lines are arranged on the substrate. The first vertical signal line is arranged on the substrate, intersects with the multiple horizontal signal lines, and the first vertical signal line is connected to one of the multiple horizontal signal lines. The second vertical signal line is arranged on the substrate, parallel to and adjacent to the first vertical signal line. The first insulating layer covers the first vertical signal line and the second vertical signal line, and the first insulating layer has a trench, wherein the trench extends along the first vertical signal line and the second vertical signal line. The projection of the groove on the substrate is located between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate. The common electrode covers the first insulating layer, and the common electrode covers the surface of the trench.

In an embodiment of the present invention, the distance between the sidewall of the trench and the first vertical signal line is 2.0 μm˜6.0 μm, and the distance between the other sidewall of the trench and the second vertical signal line is 2.0 μm˜6.0 μm.

In an embodiment of the present invention, the first insulating layer includes a lower insulating layer and an upper insulating layer, the lower insulating layer covers the first longitudinal signal line and the second longitudinal signal line, and the upper insulating layer is sandwiched between the lower insulating layer and the upper insulating layer. Between the film layers where the common electrode is located.

In an embodiment of the present invention, the depth of the trench is equivalent to the film thickness of the upper insulating layer.

In an embodiment of the present invention, the trench extends from the upper insulating layer to the lower insulating layer, and the depth of the trench is smaller than the film thickness of the lower insulating layer.

In an embodiment of the present invention, the depth of the trench is smaller than the film thickness of the upper insulating layer.

In an embodiment of the present invention, the above-mentioned electronic device further includes a second insulating layer. The second insulating layer is interposed between the film layer where the horizontal signal line is located and the film layer where the first vertical signal line is located, and has a groove corresponding to the groove. The common electrode is further formed in the groove of the second insulating layer.

In an embodiment of the present invention, the depth of the groove is smaller than the film thickness of the second insulating layer.

In an embodiment of the present invention, the groove of the second insulating layer exposes the substrate.

In an embodiment of the present invention, the above-mentioned second insulating layer has a through hole and a conduction structure passing through the through hole, and the first vertical signal line is connected to one of the plurality of horizontal signal lines through the conduction structure.

In an embodiment of the present invention, the above-mentioned electronic device further includes a plurality of pixel structures disposed on the substrate. One of the plurality of pixel structures is surrounded by adjacent two of the plurality of horizontal signal lines and the first vertical signal line and includes a pixel electrode and an active element, and the active element communicates with the first vertical signal line through one of the plurality of horizontal signal lines. The active element is connected to the second vertical signal line, and the first vertical signal line is located between the pixel structure and the trench.

In an embodiment of the present invention, in a top view of the substrate, the overlapping portion of the first vertical signal line and the horizontal signal line has a pattern bypassing the active device.

In an embodiment of the present invention, the above-mentioned first vertical signal line and the second vertical signal line have meandering patterns parallel to each other.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic partial top view of an electronic device according to an embodiment of the present invention.

FIG. 2A is a schematic diagram of a first embodiment of a section along the section line A-A' of the electronic device in FIG. 1 .

FIG. 2B is a schematic diagram of a modified example of the electronic device shown in FIG. 2A .

Fig. 3 is a schematic diagram of a second embodiment of the section along the section line A-A' in the electronic device of Fig. 1 .

Fig. 4 is a schematic diagram of a third embodiment of the section along the section line A-A' in the electronic device of Fig. 1 .

Fig. 5 is a schematic diagram of a fourth embodiment of the cross section along the section line A-A' in the electronic device of Fig. 1 .

Explanation of reference signs:

10, 10A1, 10A2, 10B, 10C, 10D: Electronics

100: Substrate

110: horizontal signal line

120: the first longitudinal signal line

130, 130a, 130b: second longitudinal signal lines

200: first insulating layer

200a, 200b: surface

210, 210': second insulating layer

212: lower insulating layer

214: upper insulating layer

300: third insulating layer

400, 402: Groove

AA: active area

COM, COM’: common electrode

CS: conduction structure

L1, L2, L3, L4: Distance

P: winding pattern

Pa1, Pa2: horizontal pattern

Pb: Vertical pattern

PE, PE': pixel electrode

PX, PX1, PX2: pixel structure

S1: First side

S2: second side

t1, t2, t3, t4: film thickness

TFT: active element

TR, TR1, TR1’, TR2, TR3: Trench

X: landscape direction

Y: Vertical direction

Detailed ways

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on," "connected to," or "overlapping" another element, it can be directly on the other element. on or connected to another element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.

It should be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer," or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or parts, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "above" can encompass both an orientation of above and below.

As used herein, "about," or "substantially" includes stated values and averages within acceptable deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurements A certain amount of (that is, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about" or "substantially" used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and one standard deviation may not be applicable to all properties.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a schematic partial top view of an electronic device according to an embodiment of the present invention; Fig. 2A is a schematic diagram of a first embodiment of a section along the section line A-A' in the electronic device of Fig. 1 . For convenience of description, the position of the insulating layer is omitted in FIG. 1 .

Referring to FIG. 1 , the electronic device 10 includes a substrate 100 , a plurality of horizontal signal lines 110 , a first vertical signal line 120 , a plurality of second vertical signal lines 130 , a common electrode COM and a plurality of pixel structures PX. The substrate 100 may have an active area AA and a peripheral area (not shown) outside the active area AA. In this embodiment, the material of the substrate 100 may include glass or other suitable materials, but the present invention is not limited thereto.

The horizontal signal line 110 is disposed on the substrate 100 and extends along the horizontal direction X. A plurality of lateral signal lines 110 may be arranged along a longitudinal direction Y intersecting the lateral direction X. Referring to FIG. Therefore, the horizontal and vertical directions described in the following embodiments can be regarded as the horizontal direction X and the longitudinal direction Y in FIG. 1 , respectively. In this embodiment, the horizontal signal lines 110 may be gate lines.

The first vertical signal lines 120 are disposed on the substrate 100 and intersect with the plurality of horizontal signal lines 110 . In this embodiment, the first vertical signal line 120 can be used as a gate transmission line and connected to one of the horizontal signal lines 110 . In some embodiments, the first vertical signal line 120 may be connected to the horizontal signal line 110 through a corresponding conducting structure CS, but the invention is not limited thereto.

The second vertical signal line 130 is disposed on the substrate 100 and parallel to the first vertical signal line 120 . In this embodiment, in the horizontal direction X, the second vertical signal line 130 is adjacent to the first vertical signal line 120; in the vertical direction Y, the first vertical signal line 120 and the second vertical signal line 130 have mutual Parallel zigzag patterns, but the present invention is not limited thereto. The second vertical signal line 130 may be a data line.

A plurality of pixel structures PX are arranged in an array on the substrate 100 . In other words, the pixel structures PX are arranged in an array along the lateral direction X and the longitudinal direction Y. In this embodiment, the pixel structure PX is connected to one of the horizontal signal lines 110 and one of the second vertical signal lines 130 . In addition, the first vertical signal line 120 is not directly connected to the pixel structure PX.

In this embodiment, one of the pixel structures PX1 is surrounded by two adjacent horizontal signal lines 110 and the first vertical signal line 120 . For example, the pixel structures PX arranged in a row along the horizontal direction X are sandwiched between two horizontal signal lines 110 ; the pixel structures PX arranged in a row along the longitudinal direction Y are sandwiched between two second vertical signal lines 130 Between; the first vertical signal line 120 is sandwiched between the pixel structure PX and the second vertical signal line 130 . In some embodiments, the pixel structures PX1 and PX2 arranged in the same row along the longitudinal direction Y may be respectively connected to the second vertical signal line 130a on the first side S1 and the second signal line 130a on the opposite second side S2. The longitudinal signal line 130b.

In this embodiment, each pixel structure PX may include an active element TFT and a pixel electrode PE connected to the active element TFT. Viewed from the top view direction of the substrate 100, although the pixel electrode PE illustrated in FIG. 1 does not overlap the first vertical signal line 120, in other embodiments, the pixel electrode PE may also overlap the first vertical signal line 120, The present invention is not limited thereto. In addition, as shown in FIG. 1 , the overlapping portion of the first vertical signal line 120 and the horizontal signal line 110 may have a winding pattern P bypassing the TFT of the active element. For example, the winding pattern P may include a horizontal pattern Pa1, a horizontal pattern Pa2, and a vertical pattern Pb. As shown in FIG. Between the TFTs and adjacent to the vertical pattern Pb, the vertical pattern Pb extends to the horizontal pattern Pa2 along the longitudinal direction Y, and the horizontal pattern Pa2 extends to the first side of the pixel structure PX2 along the pixel structure PX2. In this way, the winding pattern P can bypass the active element TFT along the side of the active element TFT. In addition, as shown in FIG. 1 , the conductive structure CS may be located at the intersection of the vertical pattern Pb and the horizontal pattern Pa2, but the present invention is not limited thereto.

The active element TFT is connected to the first vertical signal line 120 through, for example, one of the horizontal signal lines 110 , and the active element TFT is connected to the second vertical signal line 130 . For example, the active element TFT can be a transistor having a gate, a source and a drain, the gate can be connected to one of the horizontal signal lines 110, the source is connected to one of the second vertical signal lines 130, and the drain is connected to to the pixel electrode PE. Accordingly, in some embodiments, the electronic device 100 may further include a driving circuit, and the driving circuit is located at one end of the first vertical signal line 120 . The horizontal signal line 110 can receive a corresponding signal through the first vertical signal line 120 . In this way, the two ends of the horizontal signal line 110 in the horizontal direction X do not need to arrange signal transmission lines or related circuits, so that a narrow border design can be achieved. The first vertical signal line 120 can transmit the signal from the driving circuit to the horizontal signal line 110, and then input the signal from the horizontal signal line 110 to the gate of the pixel structure PX in the same column, thereby turning on or off the active gate of the pixel structure PX in the column. Element TFT. In addition, in order to avoid short circuit between the horizontal signal line 110 and the second vertical signal line 130, the horizontal signal line 110 and the second vertical signal line 130 can be made of different film layers, and the connection between the horizontal signal line 110 and the second vertical signal line 130 There can be one or more layers of insulation between them. In some embodiments, the first vertical signal line 120 and the second vertical signal line 130 can be located in the same film layer, and the horizontal signal line 110 can be located in a different film from the first vertical signal line 120 and the second vertical signal line 130 layer. In some embodiments, in order to transfer signals from the first vertical signal line 120 to the horizontal signal line 110 , a conductive structure CS may be provided between the corresponding first vertical signal line 120 and the horizontal signal line 110 . In this way, the signal required by the gate can be transmitted from the first vertical signal line 120 to the horizontal signal line 110 through the conductive structure CS, and then transmitted to the gate by the horizontal signal line 110 . In some embodiments, the electronic device 10 may further include other vertical signal lines (not shown), and the vertical signal lines may not be used to transmit signals required by the horizontal signal lines 110 , but may be input with DC potential. For example, the vertical signal lines may not be connected to any horizontal signal lines 110 , but may be used to realize touch control or other functions.

The common electrode COM covers, for example, the entire active area AA of the substrate 100 . The common electrode COM may be a common electrode for connecting panels or realizing a touch function. In some embodiments, when the electronic device 10 also has a touch signal line (TPtrace), there may also be multiple common electrodes COM, and there is a gap between the multiple common electrodes COM to expose the touch signal line, It can be applied to the realization of touch or other functions. For example, the plurality of common electrodes COM can be separated by about 2.0 μm˜8.0 μm with the touch signal line as the center.

Please refer to FIG. 1 and FIG. 2A at the same time. The electronic device 10A1 is an example of an implementation of the electronic device 10 in FIG. 1 , wherein the trench TR1 shown in FIG. 2A corresponds to the trench TR in FIG. 1 . It should be noted that the implementation form of the trench can be adjusted according to design requirements, which will be described in detail later.

In this embodiment, as shown in FIG. 2A , the electronic device 10A1 may include a first insulating layer 200 and a second insulating layer 210 . The first insulating layer 200 covers the substrate 100 , and the second insulating layer 210 covers the first vertical signal line 120 and the second vertical signal line 130 . In some embodiments, the horizontal signal line 110 is located on the first conductor layer, for example, and the first vertical signal line 120 and the second vertical signal line 130 are located on the second conductor layer above the first conductor layer. The first insulating layer 200 is, for example, sandwiched between the first conductor layer and the second conductor layer, and the second insulating layer 210 is, for example, sandwiched between the second conductor layer and the film layer where the common electrode COM is located.

The first insulating layer 200 may have a through hole and a conductive structure CS (as shown in FIG. 1 ) passing through the through hole. Therefore, the first vertical signal line 120 can be connected to one of the horizontal signal lines 110 through the conductive structure CS.

The second insulating layer 210 can be a single layer or a multilayer structure. In this embodiment, the second insulating layer 210 includes, for example, a lower insulating layer 212 and an upper insulating layer 214, wherein the lower insulating layer 212 covers the first longitudinal signal line 120 and the second longitudinal signal line 130, and the upper insulating layer 214 sandwiches Between the lower insulating layer 212 and the film layer where the common electrode COM is located. In some embodiments, the above-mentioned first insulating layer 200 and second insulating layer 210 may include inorganic insulating materials or organic insulating materials, wherein the inorganic insulating materials include silicon oxide, silicon nitride or silicon oxynitride, etc., while the organic insulating materials Materials include polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP) or polyimide (PI), etc., for example, the lower insulating layer 212 can be a passivation layer of inorganic insulating materials. layer), the upper insulating layer 214 may be a flat layer of organic insulating material, but the present invention is not limited thereto.

In this embodiment, the second insulating layer 210 has a trench TR1 . As shown in FIG. 1 , the trench TR1 extends along the first vertical signal line 120 and the second vertical signal line 130 . Moreover, the projection of the trench TR1 on the substrate 100 is located between the projection of the first vertical signal line 120 on the substrate 100 and the projection of the second vertical signal line 130 on the substrate 100 . In other words, the first vertical signal line 120 is located between the pixel structure PX and the trench TR1. As shown in FIG. 2A , the sidewall of the trench TR1 is separated from the side of the first vertical signal line 120 by a distance L1 , and the lower limit of the distance L1 is preferably 2.0 μm, preferably 3.0 μm. In addition, the upper limit of the distance L1 is preferably 6.0 μm, more preferably 5.0 μm. In one embodiment, the distance between the trench TR1 and the first vertical signal line 120 is, for example, about 2.0 μm˜6.0 μm. The other sidewall of the trench TR1 is separated by a distance L2 from the side of the second vertical signal line 130 , and the lower limit of the distance L2 is preferably 2.0 μm, preferably 3.0 μm. In addition, the upper limit of the distance L2 is preferably 6.0 μm, more preferably 5.0 μm. In one embodiment, the distance between the trench TR1 and the second vertical signal line 130 is, for example, about 2.0 μm˜6.0 μm.

In this embodiment, the depth of the trench TR1 corresponds to, for example, the film thickness t1 of the upper insulating layer 214 . In some embodiments, the trench TR1 may extend from the upper insulating layer 214 into the lower insulating layer 212 . For example, the depth of the trench TR1 may be larger than the film thickness t1 of the upper insulating layer 214 and smaller than the film thickness t2 of the lower insulating layer 212 .

The common electrode COM covers, for example, the surface of the trench TR1. Therefore, it can be used for shielding the interference between the first vertical signal line 120 and the second vertical signal line 130 to reduce the adverse effect caused by the coupling between the lines. For example, the surface of the trench TR1 is covered by the common electrode COM and the trench TR1 is located between the first vertical signal line 120 and the second vertical signal line 130, so that the electric field generated by the first vertical signal line 120 is shielded, and It will not be coupled to the second vertical signal line 130 , which can ensure that the second vertical signal line 130 maintains a certain level of output voltage, thereby improving the functions performed by the electronic device (such as screen display, touch sensing, etc.).

It should be noted that, in the first embodiment shown in FIG. 2A , the film layer where the pixel electrode (such as the pixel electrode PE in FIG. 1 ) is located is located on the film layer where the common electrode COM is located. In other words, in the manufacturing process of the electronic device, the electronic device 10A1 of this embodiment first forms the common electrode COM and then forms the pixel electrode, but the present invention is not limited thereto.

FIG. 2B is a schematic diagram of a modified example of the electronic device shown in FIG. 2A . It must be noted here that the embodiment in FIG. 2B follows the component numbers and partial contents of the embodiment in FIG. 2A , wherein the same or similar symbols are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The electronic device 10A2 of this embodiment is different from the electronic device 10A1 in FIG. 2A in that the film layers where the pixel electrodes are located and the film layers where the common electrodes are located are different. More specifically, please refer to FIG. 2B. In the electronic device 10A2 shown in FIG. 2B, the film layer where the pixel electrode PE' is located is located between the film layer where the first vertical signal line 120 or the second vertical signal line 130 is located and where the common electrode COM' is located. between the film layers. In other words, in the manufacturing process of the electronic device, in the electronic device 10A2 of this embodiment, the pixel electrode PE' is formed first and then the common electrode COM' is formed. On the other hand, viewed from the plan view direction of the substrate 100, the pixel electrode PE' overlaps the first vertical signal line 120 in the electronic device 10A2 shown in FIG. A vertical signal line 120 overlaps, and the present invention is not limited thereto.

In this embodiment, there is a third insulating layer 300 between the pixel electrode PE' and the common electrode COM'. The third insulating layer 300 and the common electrode COM' sequentially cover the surface of the trench TR1'. In other words, the third insulating layer 300 is interposed between the common electrode COM' and the surface of the trench TR1'. In this way, the shielding effect can be improved to reduce the interference between the first vertical signal line 120 and the second vertical signal line 130 .

Fig. 3 is a schematic diagram of a second embodiment of the section along the section line A-A' in the electronic device of Fig. 1 . It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1 and FIG. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here. The electronic device 10B in FIG. 3 is an example of an implementation of the electronic device 10 in FIG. 1 , wherein the trench TR2 shown in FIG. 3 corresponds to the trench TR in FIG. 1 .

Referring to FIG. 3 , the difference between the electronic device 10B of this embodiment and the electronic device 10A1 of FIG. 2A is that the depth of the trench TR2 of the electronic device 10B is smaller than the depth of the trench TR1 of the electronic device 10A1 . In this embodiment, the depth of the trench TR2 is, for example, smaller than the film thickness t1 of the upper insulating layer 214 . In addition to having a shielding effect, process steps can also be omitted to reduce manufacturing costs.

Fig. 4 is a schematic diagram of a third embodiment of the section along the section line A-A' in the electronic device of Fig. 1 . It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIG. 1 and FIG. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here. The electronic device 10C in FIG. 4 is an example of an implementation of the electronic device 10 in FIG. 1 , wherein the trench TR3 shown in FIG. 4 corresponds to the trench TR in FIG. 1 .

Please refer to FIG. 4, the difference between the electronic device 10C of this embodiment and the electronic device 10A1 of FIG. There is also a groove 400 corresponding to the groove TR3. Specifically, in this embodiment, the trench TR3 of the second insulating layer 210' runs through the thickness direction of the second insulating layer 210', while the groove 400 of the first insulating layer 200 is in the top view direction of the electronic device 10C, It completely overlaps with the trench TR3 of the second insulating layer 210 ′, so that the groove 400 of the first insulating layer 200 and the trench TR3 of the second insulating layer 210 ′ together form a bridge spanning the second insulating layer 210 ′ and the first insulating layer. 200 , and the common electrode COM is formed in the accommodating space jointly formed by the trench TR3 and the groove 400 . In this embodiment, the second insulating layer 210' may be an oxide layer. The material of the second insulating layer 210' may be the same as that of the lower insulating layer 212 in FIG. 2A , but the present invention is not limited thereto.

In this embodiment, viewed from the top view direction of the substrate 100 , the groove 400 may have the same shape as the trench TR3 . For example, the groove 400 may extend along the first vertical signal line 120 and the second vertical signal line 130, and the width of the groove 400 in the lateral direction X may be equivalent to the width of the trench TR3 in the lateral direction X, But the present invention is not limited thereto. The sidewall of the groove 400 is separated by a distance L3 from the side of the first longitudinal signal line 120 , for example, and the lower limit of the distance L3 is preferably 2.0 μm, preferably 3.0 μm. In addition, the upper limit of the distance L3 is preferably 6.0 μm, more preferably 5.0 μm. In one embodiment, the distance between the groove 400 and the first longitudinal signal line 120 is, for example, about 2.0 μm˜6.0 μm. The other sidewall of the groove 400 is separated from the side of the second longitudinal signal line 130 by a distance L4, and the lower limit of the distance L4 is preferably 2.0 μm, preferably 3.0 μm. In addition, the upper limit of the distance L4 is preferably 6.0 μm, more preferably 5.0 μm. In one embodiment, the distance between the groove 400 and the second longitudinal signal line 130 is, for example, about 2.0 μm˜6.0 μm.

In this embodiment, the depth of the trench TR3 is, for example, equivalent to the film thickness t3 of the second insulating layer 210', and the depth of the groove 400 is, for example, smaller than the film thickness t4 of the first insulating layer 200. In other words, the bottom surface of the groove 400 is between the surface 200 a and the surface 200 b of the first insulating layer 200 . Since the first vertical signal line 120 and the second vertical signal line 130 cover the surface 200a of the first insulating layer 200, the common electrode COM can be substantially located on the first surface by covering the surface of the trench TR3 and the surface of the groove 400. Between the vertical signal line 120 and the second vertical signal line 130 . In this way, the interference shielding effect between the first vertical signal line 120 and the second vertical signal line 130 can be ensured, thereby improving the functions performed by the electronic device.

Fig. 5 is a schematic diagram of a fourth embodiment of the cross section along the section line A-A' in the electronic device of Fig. 1 . It must be noted here that the embodiment in FIG. 5 follows the component numbers and part of the content of the embodiment in FIG. 1 and FIG. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here. The electronic device 10D in FIG. 5 is an example of an implementation of the electronic device 10 in FIG. 1 , wherein the trench TR3 shown in FIG. 5 corresponds to the trench TR in FIG. 1 .

Referring to FIG. 5 , the difference between the electronic device 10D of this embodiment and the electronic device 10C of FIG. 4 is that the depth of the groove 402 of the electronic device 10D is greater than the depth of the groove 400 of the electronic device 10C. In this embodiment, the groove 402 of the first insulating layer 200 exposes the substrate 100 , for example. For example, the depth of the groove 402 is equivalent to the film thickness t4 of the first insulating layer 200 . In this way, the common electrode COM can completely block the interference between the first vertical signal line 120 and the second vertical signal line 130 by covering the surface of the trench TR3 and the surface of the groove 402 , thereby further improving the shielding effect.

To sum up, the electronic device of the present invention can realize the requirement of narrow frame design by arranging the first vertical signal line. Moreover, by having a groove between the first vertical signal line and the second vertical signal line, and the common electrode covers the surface of the groove, it can be used to shield a plurality of signal lines from interfering with each other to avoid interference between lines. Problems such as adverse effects caused by coupling. In addition, it can also ensure that the signal line maintains a certain level of output voltage, thereby improving the functions performed by the electronic device.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (12)

1. An electronic device, comprising: Substrate; a plurality of horizontal signal lines arranged on the substrate; The first vertical signal line is arranged on the substrate and intersects with the plurality of horizontal signal lines, and the first vertical signal line is connected to one of the plurality of horizontal signal lines; a second vertical signal line, configured on the substrate, parallel to and adjacent to the first vertical signal line; A first insulating layer, covering the first vertical signal line and the second vertical signal line, the first insulating layer has a groove, wherein the groove is along the first vertical signal line and the second vertical signal line. Two longitudinal signal lines extend, and the projection of the groove on the substrate is located between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate; a common electrode covering the first insulating layer, and the common electrode covering the surface of the trench; and The second insulating layer is sandwiched between the film layer where the horizontal signal line is located and the film layer where the first vertical signal line is located, the second insulating layer has a groove corresponding to the groove, and the A common electrode is further formed in the groove of the second insulating layer. 2. The electronic device according to claim 1, wherein the distance between the sidewall of the trench and the first longitudinal signal line is 2.0 μm˜6.0 μm, and the distance between the other sidewall of the trench and the second longitudinal signal line The distance between the signal lines is 2.0 μm to 6.0 μm. 3. The electronic device according to claim 1 or claim 2, wherein the first insulating layer comprises a lower insulating layer and an upper insulating layer, and the lower insulating layer covers the first longitudinal signal line and the first longitudinal signal line. Two vertical signal lines, the upper insulating layer is sandwiched between the lower insulating layer and the film layer where the common electrode is located. 4. The electronic device according to claim 3, wherein the depth of the groove corresponds to the film thickness of the upper insulating layer. 5. The electronic device according to claim 4, wherein the trench extends from the upper insulating layer into the lower insulating layer, and a depth of the trench is smaller than a film thickness of the lower insulating layer. 6. The electronic device according to claim 3, wherein a depth of the groove is smaller than a film thickness of the upper insulating layer. 7. The electronic device according to claim 1, wherein a depth of the groove is smaller than a film thickness of the second insulating layer. 8. The electronic device of claim 1, wherein the groove of the second insulating layer exposes the substrate. 9. The electronic device as claimed in claim 1, wherein the second insulating layer has a through hole and a conduction structure passing through the through hole, and the first longitudinal signal line is connected to a plurality of said conduction structures through the conduction structure. One of the horizontal signal lines described above. 10. The electronic device of claim 1 or claim 2, further comprising: A plurality of pixel structures arranged on the substrate, one of the plurality of pixel structures is surrounded by adjacent two of the plurality of horizontal signal lines and the first vertical signal line and includes a pixel electrode and an active component, the active component is connected to the first vertical signal line through one of the plurality of horizontal signal lines, and the active component is connected to the second vertical signal line, and the first vertical signal line is located at Between the pixel structure and the trench. 11 . The electronic device according to claim 10 , wherein in a plan view of the substrate, the overlap between the first vertical signal line and the horizontal signal line has a pattern bypassing the active element. 12. The electronic device according to claim 1 or claim 2, wherein the first longitudinal signal line and the second longitudinal signal line have meandering patterns parallel to each other.

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