CN104181733A - Display device and transistor array substrate thereof - Google Patents

Abstract

A display device and a transistor array substrate thereof are provided, wherein the transistor array substrate comprises a substrate, a plurality of signal lines, a plurality of transistors, an insulating layer, a plurality of pixel electrodes and a common electrode. The signal lines are disposed on the substrate, wherein the signal lines are interlaced with each other. The transistors are arranged on the substrate and electrically connected with the signal lines. The insulating layer covers the signal lines and the transistors. The pixel electrodes are formed on the insulating layer and electrically connected to the transistors. Each of the pixel electrodes has a plurality of pixel edges facing each other. The common electrode is disposed under the insulating layer and has a plurality of trenches. The trench is located right below one of the pixel edges and has a first edge. The first edges extend along the pixel edges adjacent to the first edges, and the first edges are not covered by the pixel electrodes.

Description

Display device and its transistor array substrate

technical field

The invention relates to a display device, in particular to a liquid crystal display device and a transistor array substrate thereof.

Background technique

The current wide viewing angle (wider viewing angle) display technology has developed a display that uses a horizontal electric field (horizontal electric field) to drive liquid crystal molecules, such as a fringe field switching (Fringe Field Switching, FFS) display and a lateral electric field effect (In- Plane-Switching, IPS) display.

In detail, this type of display has a plurality of pixel electrodes capable of generating the above-mentioned horizontal electric field. The deflection amplitude of the liquid crystal molecules on the plane parallel to the substrate can be controlled by changing the strength of the horizontal electric field, so that the pixels of the display can display different gray scales. In this regard, many liquid crystal display manufacturers are researching how to increase the intensity of the above-mentioned horizontal electric field, so as to increase the deflection range of liquid crystal molecules, thereby improving the liquid crystal efficiency of the display.

Contents of the invention

The invention provides a transistor array substrate, the common electrode of which has a plurality of grooves, and the grooves can increase the strength of the horizontal electric field.

The present invention provides a display device, which includes the above-mentioned transistor array substrate.

An embodiment of the present invention provides a transistor array substrate, including a substrate, a plurality of signal lines, a plurality of transistors, an insulating layer, a plurality of pixel electrodes and a common electrode. The substrate has a surface. A plurality of signal lines are arranged on the surface. Each signal line has a signal line projection area on the surface. A plurality of transistors are arranged on the surface and electrically connected to these signal lines. An insulating layer is disposed on the signal lines and the transistors. A plurality of pixel electrodes are formed on the insulating layer and electrically connected with these transistors. The periphery of each pixel electrode has a plurality of pixel edges facing each other. Each pixel electrode has a pixel projection area on the surface. The common electrode is arranged under the insulating layer and has a plurality of grooves. One of the trenches is directly below one of the pixel edges, and the trench has a first edge. The first edge extends along adjacent pixel edges and has a projected section on the surface. The projection section is located between the adjacent pixel projection area and the signal line projection area.

Another embodiment of the present invention provides a display device, which includes a liquid crystal display panel, a backlight module, and a circuit board assembly. The liquid crystal display panel includes the above-mentioned transistor array substrate, an opposite substrate and a liquid crystal layer, wherein the liquid crystal layer is arranged between the transistor array substrate and the opposite substrate. The backlight module is electrically connected to the liquid crystal display panel, and the circuit board component drives the liquid crystal display panel to display images.

Based on the above, since the groove is located directly below one of the pixel edges of the pixel electrode, and the first edge extends along the adjacent pixel edge, and the projection section of the first edge on the substrate surface is located at the same Between the adjacent pixel projection area and the signal line projection area, the groove can increase the intensity of the horizontal electric field generated by the pixel electrode, so as to increase the deflection range of the liquid crystal molecules.

In order to further understand the technology, method and effect adopted by the present invention to achieve the intended purpose, please refer to the following detailed description and drawings of the present invention, and believe that the purpose, characteristics and characteristics of the present invention can be deepened and concretely obtained from this However, the accompanying drawings and appendices are provided for reference and illustration only, and are not intended to limit the present invention.

Description of drawings

FIG. 1A is a schematic wiring diagram of a transistor array substrate according to an embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view along the line I-I in FIG. 1A .

FIG. 1C is a schematic cross-sectional view along line II-II in FIG. 1A .

FIG. 2A is a schematic wiring diagram of a transistor array substrate according to another embodiment of the present invention.

FIG. 2B is a schematic cross-sectional view along line III-III in FIG. 2A .

FIG. 3 is a schematic diagram of wiring of a transistor array substrate according to another embodiment of the present invention.

FIG. 4A is a schematic perspective view of a display device according to an embodiment of the present invention.

FIG. 4B is an exploded schematic view of the display device in FIG. 4A .

FIG. 4C is a schematic cross-sectional view of the liquid crystal display panel in FIG. 4B .

【Symbol Description】

100, 200, 300, 422: transistor array substrate

110: Substrate

120d, 120s: signal line

130: Transistor

130c: Channel layer

130d: drain

130g: grid

130s: source

140, 240, 340: common electrode

151, 152: insulating layer

160, 360: pixel electrode

160e, 360e: Pixel edge

160s, 360s: slot

170: Gate insulating layer

242: electrode strip

400: display device

410: Assembling the shell

412, 414: Housing components

420: Liquid crystal display panel

426: liquid crystal layer

430: Circuit Board Assembly

432: hard circuit board

434: Flexible circuit board

440: Backlight module

424: opposite substrate

E11, E21, E31: first edge

E22, E22, E32: Second edge

H: contact window

H1: open

L1, L2: Distance

P1: pixel area

S1, S2, S3: grooves

Detailed ways

FIG. 1A is a schematic diagram of wiring of a transistor array substrate according to an embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along line I-I in FIG. 1A . Referring to FIG. 1A and FIG. 1B , the transistor array substrate 100 of this embodiment includes a substrate 110 , a plurality of signal lines 120 d and 120 s, a plurality of transistors 130 , a common electrode 140 , an insulating layer 151 and a plurality of pixel electrodes 160 . The substrate 110 is a transparent plate, such as a glass plate or a transparent plastic plate (such as an acrylic plate), and has a surface 112 , and the signal lines 120d and 120s and the transistors 130 are disposed on the surface 112 . Therefore, each of the signal lines 120d and 120s has a signal line projection area on the surface 112, the shape and range of which are shown in FIG. 1A for the signal lines 120d and 120s.

The signal lines 120d and 120s are electrically connected to the transistors 130 . Specifically, the signal lines 120d may be multiple data lines parallel to each other, and the signal lines 120s may be multiple scan lines parallel to each other. These signal lines 120d and 120s intersect each other to form a plurality of pixel regions P1. The transistors 130 are respectively formed in the pixel regions P1, and each of the transistors 130 may be a field-effect transistor (Field-Effect Transistor, FET). Therefore, each transistor 130 has a channel layer (channel) 130c, a gate (gate) 130g, a source (source) 130s, and a drain (drain) 130d, wherein these signal lines 120s (ie scan lines) are respectively connected to these gates 130g , and these signal lines 120d (ie, data lines) are respectively connected to these sources. In this way, the signal lines 120d and 120s can be electrically connected to the transistor 130 .

The insulating layer 151 is disposed on the signal lines 120d and 120s and the transistors 130 . The transistor array substrate 100 may further include another insulating layer 152 , wherein the insulating layer 152 covers the signal lines 120 d , 120 s and the transistors 130 , and is located between the insulating layer 151 and the substrate 110 . The insulating layer 152 covers the signal lines 120d, 120s and the transistor 130, and the insulating layer 151 covers the insulating layer 152, as shown in FIG. 1B. In addition, the transistor array substrate 100 may further include a gate insulating layer 170 (see FIG. 1B ). The gate insulating layer 170 is formed on the substrate 110 and covers the substrate 110 , the signal line 120s and the gate 130g. The gate insulating layer 170 can separate the gate 130g from the channel layer 130C to generate a gate capacitive effect, so that the transistor 130 can have a switch function.

The pixel electrodes 160 are formed on the insulating layer 151 and electrically connected to the transistors 130 . In detail, a plurality of contact windows H (only shown in FIG. 1B , and FIG. 1B shows only one) are formed in the insulating layers 151 and 152 . The contact window H is formed through the insulating layer 151 and the insulating layer 152, and is located directly above the drain electrodes 130d. The pixel electrodes 160 respectively extend from the upper surface of the insulating layer 151 into the contact windows H, so as to be connected to the drain 130 d of the transistor 130 .

Since the signal line 120s (that is, the scanning line) is connected to the gate 130g, the signal line 120d (that is, the data line) is connected to the source, and the pixel electrode 160 is connected to the drain 130d, these signal lines 120s can turn on and off these transistors 130, thereby controlling The signal line 120d inputs the pixel voltage to the pixel electrode 160 so that the pixel electrode 160 can drive the liquid crystal molecules to deflect. In addition, each pixel electrode 160 has a plurality of slots 160s juxtaposed to each other, and the extending directions of these slots 160s are the same as each other.

The common electrode 140 can provide a common voltage and is disposed under the insulating layer 151 , wherein the common electrode 140 can be sandwiched between the insulating layers 151 and 152 . The pixel electrode 160 passes through the common electrode 140 from the contact window H, but is not in contact with the common electrode 140 , so the pixel electrode 160 is electrically insulated from the common electrode 140 . In addition, the common electrode 140 overlaps with these pixel electrodes 160, and the distribution range of the common electrode 140 covers these slots 160s, that is, the area occupied by the common electrode 140 on the substrate 110 covers the area occupied by these slots 160s on the substrate 110 .

When the pixel voltage is input to the pixel electrode 160 , the pixel electrode 160 can generate a horizontal electric field by using the common voltage provided by the slots 160 s and the common electrode 140 , so that the liquid crystal molecules can be deflected on a plane parallel to the substrate 110 . In this way, the transistor array substrate 100 can be used to manufacture fringe field switching displays or lateral field effect displays. In addition, it should be noted that, in the embodiment shown in FIG. 1A , the slot 160s may extend along the signal line 120d, but in other embodiments, the slot 160s may also extend along the signal line 120s.

FIG. 1C is a schematic cross-sectional view along line II-II in FIG. 1A . 1A and 1C, each pixel electrode 160 has a pixel projection area on the surface 112, the shape and range of which are the pixel electrodes 160 shown in FIG. 160e. The pixel edges 160e all extend toward the same direction, and the slot 160s extends along the pixel edge 160e, that is, the direction of the pixel edge 160e and the slot 160s are the same. In addition, in the embodiment of FIG. 1A, the pixel edges 160e can also extend along the signal lines 120d. However, in other embodiments, when the slot 160s extends along the signal line 120s, the pixel edge 160e may also extend along the signal line 120s.

The common electrode 140 has a plurality of grooves S1 , and one of the grooves S1 is located directly below one of the pixel edges 160 e and partially covered by the pixel electrode 160 , that is, the groove S1 partially overlaps the pixel electrode 160 . In detail, the trench S1 has a first edge E11 and a second edge E12 , wherein the second edge E12 is opposite to the first edge E11 . From FIG. 1A and FIG. 1C, the first edge E11 extends along the adjacent pixel edge 160e, and is parallel to the adjacent pixel edge 160e, wherein these first edges E11 are not covered by these pixel electrodes 160, but these The second edge E12 is covered by the pixel electrodes 160 .

Specifically, the first edge E11 and the second edge E12 each have a projection section on the surface 112, wherein the projection section of the first edge E11 is located in the adjacent pixel projection area (the pixel electrode 160 shown in FIG. 1A ) and the projection area of the signal line 120d (as shown in FIG. A segment then overlaps its adjacent pixel projection area.

Based on the above, in the same groove S1, the pixel edge 160e will be located between the first edge E11 and the second edge E12, that is, the distance L2 between the first edge E11 and the pixel edge 160e and the distance between the second edge E12 and the pixel Neither of the distances L1 between the edges 160e will be equal to zero. In addition, one or two trenches S1 may be stored in a pixel region P1, and these trenches S1 are not intersected with the signal lines 120d, 120s, that is, the trenches S1 are completely located in the pixel region P1. In addition, in the same pixel region P1 , the slot 160s does not overlap with the trench S1 , that is, the trench S1 is not directly below the slot 160s.

Since the common electrode 140 has these grooves S1 located directly below the pixel edge 160e, and each groove S1 has a first edge E11 extending along the pixel edge 160e and not covered by the pixel electrode 160, therefore, in the same groove In the slot S1, an electric field with a strong horizontal component is generated between the pixel edge 160e and the first edge E11. In this way, the grooves S1 can increase the intensity of the horizontal electric field generated by the pixel electrode 160 to increase the deflection range of the liquid crystal molecules, thereby improving the liquid crystal efficiency of the display.

It is worth mentioning that, in this embodiment, the common electrode 140 may overlap the signal lines 120d, 120s and the transistor 130, and the common electrode 140 may completely cover the signal lines 120d. In this way, when the transistor array substrate 100 is in operation, the common electrode 140 can serve as an electromagnetic shielding layer to reduce the interference of the signal lines 120d and 120s on the pixel electrode 160 .

FIG. 2A is a schematic wiring diagram of a transistor array substrate according to another embodiment of the present invention, and FIG. 2B is a schematic cross-sectional view along line III-III in FIG. 2A . Please refer to FIG. 2A and FIG. 2B , the structure of the transistor array substrate 200 of this embodiment is similar to that of the aforementioned transistor array substrate 100 , and the functions are basically the same. Therefore, the differences between the transistor array substrate 200 and the transistor array substrate 100 are mainly introduced below. As for the same features of the two, no more detailed description will be given.

The transistor array substrate 200 includes a common electrode 240 , and the common electrode 240 also has a plurality of trenches S2 parallel to each other. However, unlike the common electrodes 140 in the foregoing embodiments, the trenches S2 intersect with the signal lines 120s. That is to say, the trench S2 extends from one pixel region P1 to the other pixel region P1 and passes through at least two pixel regions P1 , as shown in FIG. 2A . In addition, in this embodiment, the direction of both the groove S2 and the slot 160s can be the same as the direction of the signal line 120d (that is, the data line), but in other embodiments, the direction of both the groove S2 and the slot 160s The direction may also be the same as that of the signal line 120s (ie, the scanning line).

Some pixel electrodes 160 can be arranged in a straight line along one of the trenches S2 , and some edges of the pixel electrodes 160 are aligned with the edges of the adjacent trenches S2 . In detail, each groove S2 has a first edge E21 and a second edge E22, and the second edge E22 is located opposite to the first edge E21. The first edge E21 is not covered by the pixel electrode 160 and extends along the adjacent pixel edge 160e, while the second edge E22 is aligned with the pixel edge 160e of the pixel electrode 160, as shown in FIG. 2A and FIG. 2B. Utilizing the first edge E11, the grooves S2 can also increase the intensity of the horizontal electric field generated by the pixel electrode 160, thereby improving the liquid crystal efficiency of the display.

It should be noted that although the trenches S2 intersect with the signal lines 120s, and the trenches S2 pass through at least two pixel regions P1, these trenches S2 do not split the common electrode 240 into more than two parts. Therefore, the overall edges of trenches S2 are continuous rather than separated from each other. That is to say, both the first edge E21 and the second edge E22 of the trench S2 are connected via other edges.

In addition, in the embodiment shown in FIG. 2A , the common electrode 240 only has the groove S2 instead of the groove S1 in the previous embodiment, but in other embodiments, the common electrode 240 can also have two different lengths. The grooves, that is, the common electrode 240 not only has the groove S2, but may also have the groove S1. In addition, according to various product requirements and specifications, the grooves S1 and S2 may have various designs in terms of quantity and arrangement. For example, at least one of the grooves S2 in FIG. 2A can be replaced with a groove S1. Alternatively, the common electrode 240 may have the same number of grooves S1 and S2 , and the grooves S1 and S2 are juxtaposed alternately. Therefore, the grooves S1 and S2 shown in FIG. 1A and FIG. 2A are only for illustration, not limiting the present invention.

The common electrode 240 may further have a plurality of openings H1 and a plurality of electrode strips 242 . In detail, each opening H1 is formed directly above one of the signal lines 120d (ie, the data line), and extends along the signal line 120d. These openings H1 are not connected to any trench S2, so part of the common electrode 240 will be formed between one of the openings H1 and its adjacent trench S2, and this part of the common electrode 240 is an electrode strip 242, and some of the common electrodes 240 are first The edge E21 becomes the edge of the electrode strips 242, and each electrode strip 242 extends along the pixel edge 160e. These electrode strips 242 will not be covered by the pixel electrodes 160 , and a strong horizontal electric field will be generated between the electrode strips 242 and the pixel electrodes 160 , thereby increasing the deflection range of the liquid crystal molecules.

In addition, since each opening H1 is formed directly above one of the signal lines 120d, these openings H1 will reduce the overlapping area between the common electrode 240 and the signal line 120d, so as to weaken the interference caused between the common electrode 240 and the signal line 120d. Capacitive coupling effect, thereby reducing the signal delay in the signal line 120d. In addition, in this embodiment, the multiple openings H1 are arranged along the signal line 120d, but in other embodiments, these signal lines 120d located directly above the same signal line 120d can be connected to each other to form a long and narrow groove.

In addition, according to various product requirements and specifications, at least one of the openings H1 in FIG. 2A can be filled by the common electrode 240, and even like the embodiment shown in FIG. 1A, the common electrode 240 can also completely cover these openings. Signal line 120d. Therefore, the openings H1 shown in FIG. 2A are only for illustration, not limiting the present invention.

FIG. 3 is a schematic diagram of wiring of a transistor array substrate according to another embodiment of the present invention. Referring to FIG. 3 , the structure of the transistor array substrate 300 of this embodiment is similar to that of the aforementioned transistor array substrate 100 , and their functions are substantially the same, and the same features of the two will not be described in detail below. However, there are still differences between the transistor array substrate 300 and 100, which are that the shape of the pixel electrode 360 of the transistor array substrate 300 is different from that of the pixel electrode 160, and the common electrode 340 of the transistor array substrate 300 has a shape different from that of the pixel electrode 160. trench S1 to trench S3.

Specifically, in the transistor array substrate 300, the pixel electrode 360 has a plurality of slots 360s. The shape of the slots 360s is V-shaped, and these slots 360s are juxtaposed to each other, and the directions of these slots 360s in the same pixel electrode 360 are the same as each other, as shown in FIG. 3 . In this embodiment, the slots 360s of the same pixel electrode 360 can be arranged along the signal line 120d, but in other embodiments, the slots 360s of the same pixel electrode 360 can also be arranged along the signal line 120s. arrangement. Therefore, the arrangement direction of the slots 360s in a single pixel electrode 360 is not limited by the disclosure of FIG. 3 . In addition, each pixel electrode 360 also has a pair of pixel edges 360e opposite to each other, and the pixel edges 360e extend along the adjacent slot 360s, so the shape of the pixel edges 360e is also V-shaped, as shown in FIG. 3 .

The common electrode 340 has a plurality of trenches S3 parallel to each other, and the trench S3 is located directly below one of the pixel edges 360e. The trench S3 has a first edge E31 and a second edge E32, wherein the second edge E32 is opposite to the first edge E31. The first edge E31 extends along the adjacent pixel edge 360 e and is not covered by the pixel electrode 360 . Since the shape of the pixel edge 360e is V-shaped, the shape of the first edge E31 extending along the pixel edge 360e is also V-shaped.

In this embodiment, the second edge E32 is covered by the pixel electrode 360 , but in other embodiments, the second edge E32 can also be aligned with the pixel edge 360 e of the pixel electrode 360 . In addition, in the embodiment shown in FIG. 3 , the common electrode 340 may overlap the signal lines 120d, 120s and the transistor 130, and the common electrode 340 may completely cover the signal lines 120d. In this way, when the transistor array substrate 300 is in operation, the common electrode 340 can serve as an electromagnetic shielding layer to reduce the interference of the signal lines 120d and 120s on the pixel electrode 360 .

However, in other embodiments, the common electrode 340 may also have a plurality of openings H1 and a plurality of electrode strips 242 as shown in FIG. 2A , wherein the openings H1 may be arranged along the signal line 120d or 120s. In this way, the overlapping area between the common electrode 340 and the signal line 120d or 120s can be reduced, thereby weakening the capacitive coupling effect caused between the common electrode 340 and the signal line 120d or 120s. In addition, the openings H1 of the common electrode 340 may be connected to each other to form a long and narrow trench.

FIG. 4A is a perspective view of a display device according to an embodiment of the present invention, and FIG. 4B is an exploded view of the display device in FIG. 4A . Referring to FIG. 4A and FIG. 4B , the display device 400 of this embodiment may be a computer screen (as shown in FIG. 4A and FIG. 4B ) or a display such as a TV. Alternatively, the display device 400 may be a screen of a portable electronic device, such as a mobile phone, a smart phone, a tablet computer, a notebook computer, a digital camera, a digital video camera, or a handheld game console.

The display device 400 includes an assembly case 410 , a liquid crystal display panel 420 , a backlight module 440 and a circuit board assembly 430 , wherein the assembly case 410 may include two case assemblies 412 and 414 . By combining the housing components 412 and 414 , the liquid crystal display panel 420 , the backlight module 440 and the circuit board component 430 are installed in the assembled housing 410 . The liquid crystal display panel 420 is electrically connected to the circuit board assembly 430 . The backlight module 440 is disposed opposite to the liquid crystal display panel 420 , and the backlight module 440 can be used as a backlight source of the liquid crystal display panel 420 .

The circuit board assembly 430 can be a flex-rigid circuit board (flex-rigid circuit board) with multiple electronic components installed (mount), and includes a rigid circuit board (rigid circuit board) 432 and a flexible circuit board (flexible circuit board) 434, wherein the above-mentioned electronic components include a plurality of passive components and a plurality of active components, and these passive components and these active components can constitute a driving circuit and a power supply circuit, wherein the driving circuit can drive the liquid crystal display panel 420 to display image images, and The power supply circuit can control external power input to the backlight module 440 and the liquid crystal display panel 420 .

In addition, the flexible circuit board 434 is connected between the rigid circuit board 432 and the liquid crystal display panel 420 . Using the flexible circuit board 434 , the circuit board assembly 430 can be electrically connected to the liquid crystal display panel 420 . In addition, the circuit board assembly 430 can also use a plurality of wires to electrically connect the liquid crystal display panel 420 , so the circuit board assembly 430 is not limited to be only a soft and hard circuit board.

FIG. 4C is a schematic cross-sectional view of the liquid crystal display panel in FIG. 4B . Please refer to FIG. 4C, the liquid crystal display panel 420 includes a transistor array substrate 422, an opposite substrate 424 and a liquid crystal layer 426, wherein the liquid crystal layer 426 is arranged between the transistor array substrate 422 and the opposite substrate 424, and the transistor array substrate 422 and the opposite The substrates 424 can be combined with each other through a sealant (not shown), wherein the sealant will surround and seal the liquid crystal layer 426 .

The transistor array substrate 422 can be the transistor array substrate 100 , 200 or 300 in the foregoing embodiments, and the liquid crystal display panel 420 can be a fringe field switching (FFS) display or a panel dedicated to lateral field effect (IPS). Accordingly, the liquid crystal layer 426 may include a horizontally aligned liquid crystal material. In addition, the opposite substrate 424 may be a color filter array substrate.

To sum up, the common electrode in the embodiment of the present invention has a plurality of grooves, and the groove is located directly below one of the pixel edges of the pixel electrode, and has a part of the edge not covered by the pixel electrode (for example, the first edge ), wherein the part of the edge extends along the pixel edge of the pixel electrode. Therefore, these grooves can increase the intensity of the horizontal electric field generated by the pixel electrodes, so as to increase the deflection range of the liquid crystal molecules, thereby improving the liquid crystal efficiency of the display.

The above descriptions are only preferred feasible embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A transistor array substrate, characterized in that, the transistor array substrate comprises: a substrate having a surface; A plurality of signal lines arranged on the surface, each of the signal lines has a signal line projection area on the surface; a plurality of transistors configured on the surface and electrically connected to the signal line; an insulating layer configured on the signal line and the transistor; a plurality of pixel electrodes formed on the insulating layer and electrically connected to the transistor, each of the pixel electrodes has a plurality of pixel edges facing each other on the periphery, and each of the pixel electrodes has a pixel projection on the surface area; and A common electrode is arranged under the insulating layer and has a plurality of grooves, one of the grooves is located directly below one of the pixel edges, and the groove has a first edge, the A first edge extends along an edge of the pixel adjacent to the first edge and has a projected section on the surface between the projected area of the pixel adjacent to the projected section and between the signal line projection areas. 2 . The transistor array substrate according to claim 1 , wherein the projection section is located outside the pixel projection area adjacent to the projection section. 3. The transistor array substrate according to claim 1, wherein the first edge is parallel to the pixel edge adjacent to the first edge. 4. The transistor array substrate according to claim 1, wherein the groove further has a second edge, the second edge is located opposite to the first edge, and is connected to the second edge Edges of adjacent pixels are aligned. 5. The transistor array substrate according to claim 1, wherein each of the pixel electrodes has a plurality of slits, the slits are juxtaposed with each other and extend along the edge of the pixel, and the slits are aligned with the pixel electrodes. The grooves do not overlap. 6 . The transistor array substrate according to claim 1 , wherein a part of the signal lines are juxtaposed to each other, and the part of the signal lines juxtaposed to each other are intersected with the grooves. 7. The transistor array substrate according to claim 1, wherein the signal lines include a plurality of data lines and a plurality of scan lines, the data lines are parallel to each other, and the scan lines are parallel to each other, wherein the The data lines and the scan lines are interlaced with each other. 8. The transistor array substrate according to claim 7, wherein the common electrode further has a plurality of openings and a plurality of electrode strips, each of the openings is formed directly above one of the data lines, and each of the The electrode strip is formed between one of the openings and the groove adjacent to the electrode strip, and extends along the edge of the pixel. 9. The transistor array substrate according to claim 7, wherein the common electrode overlaps with the data line. 10. A display device, characterized in that the display device comprises: A liquid crystal display panel, comprising; A transistor array substrate according to claim 1; a pair of substrates; a liquid crystal layer disposed between the transistor array substrate and the opposite substrate; and a backlight module; and A circuit board assembly drives the liquid crystal display panel to display an image frame.